Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	355797292	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	355797292	0	0
T1	23800	841	0	0
T2	47551784	1037319	0	0
T3	17748696	395081	0	0
T4	168168	10472	0	0
T5	6847064	298290	0	0
T14	11356632	1547302	0	0
T15	0	12590	0	0
T16	2838248	59128	0	0
T17	6076728	189638	0	0
T18	6134408	1323768	0	0
T19	37296	585	0	0
T20	0	533	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23800	23296	0	0
T2	47551784	47547920	0	0
T3	17748696	17743432	0	0
T4	168168	164920	0	0
T5	6847064	6762280	0	0
T14	11356632	11356464	0	0
T16	2838248	2834944	0	0
T17	6076728	6074880	0	0
T18	6134408	6134128	0	0
T19	37296	33544	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23800	23296	0	0
T2	47551784	47547920	0	0
T3	17748696	17743432	0	0
T4	168168	164920	0	0
T5	6847064	6762280	0	0
T14	11356632	11356464	0	0
T16	2838248	2834944	0	0
T17	6076728	6074880	0	0
T18	6134408	6134128	0	0
T19	37296	33544	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23800	23296	0	0
T2	47551784	47547920	0	0
T3	17748696	17743432	0	0
T4	168168	164920	0	0
T5	6847064	6762280	0	0
T14	11356632	11356464	0	0
T16	2838248	2834944	0	0
T17	6076728	6074880	0	0
T18	6134408	6134128	0	0
T19	37296	33544	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T14	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	128694383	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	128694383	0	0
T1	425	325	0	0
T2	849139	413388	0	0
T3	316941	149969	0	0
T4	3003	2618	0	0
T5	122269	112044	0	0
T14	202797	9557	0	0
T16	50683	26727	0	0
T17	108513	106100	0	0
T18	109543	533593	0	0
T19	666	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	93784826	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	93784826	0	0
T1	425	172	0	0
T2	849139	206788	0	0
T3	316941	90277	0	0
T4	3003	2618	0	0
T5	122269	66545	0	0
T14	202797	764094	0	0
T16	50683	7691	0	0
T17	108513	41525	0	0
T18	109543	253712	0	0
T19	666	119	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1495052	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1495052	0	0
T1	425	4	0	0
T2	849139	5718	0	0
T3	316941	2536	0	0
T4	3003	0	0	0
T5	122269	3199	0	0
T14	202797	0	0	0
T15	0	569	0	0
T16	50683	844	0	0
T17	108513	17	0	0
T18	109543	14868	0	0
T19	666	9	0	0
T20	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	4163271	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	4163271	0	0
T1	425	4	0	0
T2	849139	4283	0	0
T3	316941	2562	0	0
T4	3003	0	0	0
T5	122269	3199	0	0
T14	202797	0	0	0
T15	0	179	0	0
T16	50683	252	0	0
T17	108513	1146	0	0
T18	109543	11420	0	0
T19	666	9	0	0
T20	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1510743	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1510743	0	0
T1	425	6	0	0
T2	849139	6590	0	0
T3	316941	2258	0	0
T4	3003	232	0	0
T5	122269	1707	0	0
T14	202797	0	0	0
T15	0	448	0	0
T16	50683	597	0	0
T17	108513	56	0	0
T18	109543	8655	0	0
T19	666	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3797995	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3797995	0	0
T1	425	6	0	0
T2	849139	8503	0	0
T3	316941	2399	0	0
T4	3003	232	0	0
T5	122269	1707	0	0
T14	202797	0	0	0
T15	0	224	0	0
T16	50683	232	0	0
T17	108513	4226	0	0
T18	109543	8320	0	0
T19	666	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1520859	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1520859	0	0
T1	425	2	0	0
T2	849139	4173	0	0
T3	316941	2270	0	0
T4	3003	0	0	0
T5	122269	2253	0	0
T14	202797	1113	0	0
T15	0	316	0	0
T16	50683	533	0	0
T17	108513	11	0	0
T18	109543	17275	0	0
T19	666	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3927920	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3927920	0	0
T1	425	2	0	0
T2	849139	4163	0	0
T3	316941	2338	0	0
T4	3003	0	0	0
T5	122269	2253	0	0
T14	202797	89074	0	0
T15	0	188	0	0
T16	50683	273	0	0
T17	108513	206	0	0
T18	109543	14703	0	0
T19	666	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1515157	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1515157	0	0
T1	425	9	0	0
T2	849139	8809	0	0
T3	316941	2532	0	0
T4	3003	0	0	0
T5	122269	2161	0	0
T14	202797	0	0	0
T15	0	388	0	0
T16	50683	512	0	0
T17	108513	20	0	0
T18	109543	7277	0	0
T19	666	4	0	0
T20	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	2453012	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	2453012	0	0
T1	425	9	0	0
T2	849139	7345	0	0
T3	316941	2484	0	0
T4	3003	0	0	0
T5	122269	2161	0	0
T14	202797	0	0	0
T15	0	176	0	0
T16	50683	227	0	0
T17	108513	2110	0	0
T18	109543	6445	0	0
T19	666	4	0	0
T20	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1514088	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1514088	0	0
T1	425	2	0	0
T2	849139	9494	0	0
T3	316941	2429	0	0
T4	3003	233	0	0
T5	122269	2567	0	0
T14	202797	999	0	0
T16	50683	688	0	0
T17	108513	16	0	0
T18	109543	10244	0	0
T19	666	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3842169	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3842169	0	0
T1	425	2	0	0
T2	849139	6209	0	0
T3	316941	2358	0	0
T4	3003	233	0	0
T5	122269	2567	0	0
T14	202797	90406	0	0
T16	50683	299	0	0
T17	108513	2576	0	0
T18	109543	8976	0	0
T19	666	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1480546	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1480546	0	0
T1	425	6	0	0
T2	849139	8367	0	0
T3	316941	2441	0	0
T4	3003	0	0	0
T5	122269	1739	0	0
T14	202797	0	0	0
T15	0	247	0	0
T16	50683	560	0	0
T17	108513	29	0	0
T18	109543	11770	0	0
T19	666	4	0	0
T20	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3318131	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3318131	0	0
T1	425	6	0	0
T2	849139	5985	0	0
T3	316941	2504	0	0
T4	3003	0	0	0
T5	122269	1739	0	0
T14	202797	0	0	0
T15	0	130	0	0
T16	50683	252	0	0
T17	108513	1665	0	0
T18	109543	9466	0	0
T19	666	4	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1473076	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1473076	0	0
T1	425	6	0	0
T2	849139	8031	0	0
T3	316941	2400	0	0
T4	3003	496	0	0
T5	122269	1680	0	0
T14	202797	0	0	0
T15	0	405	0	0
T16	50683	731	0	0
T17	108513	0	0	0
T18	109543	10513	0	0
T19	666	2	0	0
T20	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3433897	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3433897	0	0
T1	425	6	0	0
T2	849139	7976	0	0
T3	316941	2527	0	0
T4	3003	496	0	0
T5	122269	1680	0	0
T14	202797	0	0	0
T15	0	203	0	0
T16	50683	264	0	0
T17	108513	0	0	0
T18	109543	7447	0	0
T19	666	2	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1516054	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1516054	0	0
T1	425	6	0	0
T2	849139	9749	0	0
T3	316941	2632	0	0
T4	3003	0	0	0
T5	122269	1845	0	0
T14	202797	0	0	0
T15	0	417	0	0
T16	50683	641	0	0
T17	108513	15	0	0
T18	109543	12174	0	0
T19	666	7	0	0
T20	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3703503	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3703503	0	0
T1	425	6	0	0
T2	849139	12383	0	0
T3	316941	2837	0	0
T4	3003	0	0	0
T5	122269	1845	0	0
T14	202797	0	0	0
T15	0	143	0	0
T16	50683	330	0	0
T17	108513	2247	0	0
T18	109543	9533	0	0
T19	666	7	0	0
T20	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1506687	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1506687	0	0
T1	425	10	0	0
T2	849139	5317	0	0
T3	316941	4123	0	0
T4	3003	230	0	0
T5	122269	2935	0	0
T14	202797	0	0	0
T15	0	329	0	0
T16	50683	676	0	0
T17	108513	20	0	0
T18	109543	6799	0	0
T19	666	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3613203	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3613203	0	0
T1	425	10	0	0
T2	849139	4725	0	0
T3	316941	4117	0	0
T4	3003	230	0	0
T5	122269	2935	0	0
T14	202797	0	0	0
T15	0	139	0	0
T16	50683	297	0	0
T17	108513	1852	0	0
T18	109543	8608	0	0
T19	666	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1528504	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1528504	0	0
T1	425	4	0	0
T2	849139	4537	0	0
T3	316941	2605	0	0
T4	3003	0	0	0
T5	122269	2222	0	0
T14	202797	0	0	0
T15	0	310	0	0
T16	50683	585	0	0
T17	108513	4	0	0
T18	109543	14024	0	0
T19	666	9	0	0
T20	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3585710	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3585710	0	0
T1	425	4	0	0
T2	849139	3129	0	0
T3	316941	2784	0	0
T4	3003	0	0	0
T5	122269	2222	0	0
T14	202797	0	0	0
T15	0	159	0	0
T16	50683	303	0	0
T17	108513	392	0	0
T18	109543	10507	0	0
T19	666	9	0	0
T20	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1519302	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1519302	0	0
T1	425	5	0	0
T2	849139	9962	0	0
T3	316941	2423	0	0
T4	3003	235	0	0
T5	122269	2165	0	0
T14	202797	0	0	0
T15	0	405	0	0
T16	50683	550	0	0
T17	108513	12	0	0
T18	109543	7416	0	0
T19	666	0	0	0
T20	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3260767	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3260767	0	0
T1	425	5	0	0
T2	849139	9882	0	0
T3	316941	2409	0	0
T4	3003	235	0	0
T5	122269	2165	0	0
T14	202797	0	0	0
T15	0	160	0	0
T16	50683	251	0	0
T17	108513	1686	0	0
T18	109543	5699	0	0
T19	666	0	0	0
T20	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1495315	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1495315	0	0
T1	425	8	0	0
T2	849139	7062	0	0
T3	316941	4197	0	0
T4	3003	0	0	0
T5	122269	2517	0	0
T14	202797	1157	0	0
T15	0	353	0	0
T16	50683	721	0	0
T17	108513	19	0	0
T18	109543	9018	0	0
T19	666	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3775089	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3775089	0	0
T1	425	8	0	0
T2	849139	8560	0	0
T3	316941	4173	0	0
T4	3003	0	0	0
T5	122269	2516	0	0
T14	202797	85576	0	0
T15	0	158	0	0
T16	50683	259	0	0
T17	108513	1057	0	0
T18	109543	10500	0	0
T19	666	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1513992	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1513992	0	0
T1	425	9	0	0
T2	849139	7394	0	0
T3	316941	2206	0	0
T4	3003	263	0	0
T5	122269	1927	0	0
T14	202797	0	0	0
T15	0	227	0	0
T16	50683	622	0	0
T17	108513	27	0	0
T18	109543	10670	0	0
T19	666	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3983844	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3983844	0	0
T1	425	9	0	0
T2	849139	7087	0	0
T3	316941	2489	0	0
T4	3003	263	0	0
T5	122269	1927	0	0
T14	202797	0	0	0
T15	0	134	0	0
T16	50683	305	0	0
T17	108513	2201	0	0
T18	109543	12724	0	0
T19	666	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1538106	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1538106	0	0
T1	425	7	0	0
T2	849139	12161	0	0
T3	316941	2282	0	0
T4	3003	0	0	0
T5	122269	3248	0	0
T14	202797	0	0	0
T15	0	326	0	0
T16	50683	638	0	0
T17	108513	18	0	0
T18	109543	13417	0	0
T19	666	6	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	2792684	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	2792684	0	0
T1	425	7	0	0
T2	849139	10579	0	0
T3	316941	2237	0	0
T4	3003	0	0	0
T5	122269	3248	0	0
T14	202797	0	0	0
T15	0	153	0	0
T16	50683	297	0	0
T17	108513	1508	0	0
T18	109543	8683	0	0
T19	666	6	0	0
T20	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1526933	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1526933	0	0
T1	425	7	0	0
T2	849139	6805	0	0
T3	316941	4895	0	0
T4	3003	0	0	0
T5	122269	2078	0	0
T14	202797	1226	0	0
T15	0	291	0	0
T16	50683	597	0	0
T17	108513	10	0	0
T18	109543	10263	0	0
T19	666	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3881083	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3881083	0	0
T1	425	7	0	0
T2	849139	5339	0	0
T3	316941	4920	0	0
T4	3003	0	0	0
T5	122269	2078	0	0
T14	202797	103839	0	0
T15	0	80	0	0
T16	50683	256	0	0
T17	108513	1214	0	0
T18	109543	9118	0	0
T19	666	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1520619	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1520619	0	0
T1	425	4	0	0
T2	849139	6068	0	0
T3	316941	2359	0	0
T4	3003	255	0	0
T5	122269	2184	0	0
T14	202797	1073	0	0
T16	50683	641	0	0
T17	108513	24	0	0
T18	109543	12576	0	0
T19	666	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	2973250	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	2973250	0	0
T1	425	4	0	0
T2	849139	6335	0	0
T3	316941	2257	0	0
T4	3003	255	0	0
T5	122269	2184	0	0
T14	202797	80038	0	0
T16	50683	223	0	0
T17	108513	2821	0	0
T18	109543	10787	0	0
T19	666	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1504397	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1504397	0	0
T1	425	10	0	0
T2	849139	9058	0	0
T3	316941	4204	0	0
T4	3003	0	0	0
T5	122269	2240	0	0
T14	202797	2581	0	0
T15	0	309	0	0
T16	50683	686	0	0
T17	108513	13	0	0
T18	109543	10320	0	0
T19	666	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3760843	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3760843	0	0
T1	425	10	0	0
T2	849139	7028	0	0
T3	316941	5018	0	0
T4	3003	0	0	0
T5	122269	2240	0	0
T14	202797	205220	0	0
T15	0	135	0	0
T16	50683	262	0	0
T17	108513	1303	0	0
T18	109543	10117	0	0
T19	666	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1464737	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1464737	0	0
T1	425	7	0	0
T2	849139	7908	0	0
T3	316941	4127	0	0
T4	3003	0	0	0
T5	122269	2458	0	0
T14	202797	0	0	0
T15	0	471	0	0
T16	50683	689	0	0
T17	108513	7	0	0
T18	109543	7818	0	0
T19	666	2	0	0
T20	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3125057	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3125057	0	0
T1	425	7	0	0
T2	849139	6383	0	0
T3	316941	4293	0	0
T4	3003	0	0	0
T5	122269	2457	0	0
T14	202797	0	0	0
T15	0	129	0	0
T16	50683	332	0	0
T17	108513	562	0	0
T18	109543	8480	0	0
T19	666	2	0	0
T20	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1475175	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1475175	0	0
T1	425	9	0	0
T2	849139	9727	0	0
T3	316941	2314	0	0
T4	3003	215	0	0
T5	122269	2188	0	0
T14	202797	0	0	0
T15	0	256	0	0
T16	50683	441	0	0
T17	108513	20	0	0
T18	109543	6160	0	0
T19	666	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3177462	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3177462	0	0
T1	425	9	0	0
T2	849139	9424	0	0
T3	316941	2144	0	0
T4	3003	215	0	0
T5	122269	2188	0	0
T14	202797	0	0	0
T15	0	103	0	0
T16	50683	255	0	0
T17	108513	1934	0	0
T18	109543	6451	0	0
T19	666	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1503984	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1503984	0	0
T1	425	7	0	0
T2	849139	8654	0	0
T3	316941	4380	0	0
T4	3003	0	0	0
T5	122269	2234	0	0
T14	202797	1408	0	0
T15	0	377	0	0
T16	50683	628	0	0
T17	108513	3	0	0
T18	109543	7730	0	0
T19	666	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3593366	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3593366	0	0
T1	425	7	0	0
T2	849139	9953	0	0
T3	316941	4413	0	0
T4	3003	0	0	0
T5	122269	2234	0	0
T14	202797	109941	0	0
T15	0	157	0	0
T16	50683	341	0	0
T17	108513	497	0	0
T18	109543	9446	0	0
T19	666	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1440528	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1440528	0	0
T1	425	5	0	0
T2	849139	10822	0	0
T3	316941	2009	0	0
T4	3003	0	0	0
T5	122269	2665	0	0
T14	202797	0	0	0
T15	0	413	0	0
T16	50683	553	0	0
T17	108513	15	0	0
T18	109543	12518	0	0
T19	666	2	0	0
T20	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	2944974	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	2944974	0	0
T1	425	5	0	0
T2	849139	11756	0	0
T3	316941	2312	0	0
T4	3003	0	0	0
T5	122269	2664	0	0
T14	202797	0	0	0
T15	0	179	0	0
T16	50683	272	0	0
T17	108513	1298	0	0
T18	109543	9690	0	0
T19	666	2	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1473373	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1473373	0	0
T1	425	6	0	0
T2	849139	8975	0	0
T3	316941	2274	0	0
T4	3003	0	0	0
T5	122269	1409	0	0
T14	202797	0	0	0
T15	0	359	0	0
T16	50683	757	0	0
T17	108513	28	0	0
T18	109543	12940	0	0
T19	666	3	0	0
T20	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3102911	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3102911	0	0
T1	425	6	0	0
T2	849139	9126	0	0
T3	316941	2553	0	0
T4	3003	0	0	0
T5	122269	1409	0	0
T14	202797	0	0	0
T15	0	166	0	0
T16	50683	393	0	0
T17	108513	1917	0	0
T18	109543	12015	0	0
T19	666	3	0	0
T20	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1512985	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1512985	0	0
T1	425	7	0	0
T2	849139	5656	0	0
T3	316941	2347	0	0
T4	3003	0	0	0
T5	122269	2431	0	0
T14	202797	0	0	0
T15	0	351	0	0
T16	50683	531	0	0
T17	108513	37	0	0
T18	109543	12394	0	0
T19	666	8	0	0
T20	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3403363	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3403363	0	0
T1	425	7	0	0
T2	849139	5122	0	0
T3	316941	2517	0	0
T4	3003	0	0	0
T5	122269	2431	0	0
T14	202797	0	0	0
T15	0	131	0	0
T16	50683	280	0	0
T17	108513	2074	0	0
T18	109543	9798	0	0
T19	666	8	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1514616	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1514616	0	0
T1	425	10	0	0
T2	849139	7656	0	0
T3	316941	2225	0	0
T4	3003	237	0	0
T5	122269	2110	0	0
T14	202797	0	0	0
T15	0	381	0	0
T16	50683	680	0	0
T17	108513	18	0	0
T18	109543	9181	0	0
T19	666	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	2842917	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	2842917	0	0
T1	425	10	0	0
T2	849139	8706	0	0
T3	316941	2474	0	0
T4	3003	237	0	0
T5	122269	2110	0	0
T14	202797	0	0	0
T15	0	186	0	0
T16	50683	286	0	0
T17	108513	1215	0	0
T18	109543	10394	0	0
T19	666	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1463152	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1463152	0	0
T1	425	7	0	0
T2	849139	6702	0	0
T3	316941	2413	0	0
T4	3003	0	0	0
T5	122269	1601	0	0
T14	202797	0	0	0
T15	0	269	0	0
T16	50683	648	0	0
T17	108513	4	0	0
T18	109543	9587	0	0
T19	666	4	0	0
T20	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3441276	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3441276	0	0
T1	425	7	0	0
T2	849139	8020	0	0
T3	316941	2495	0	0
T4	3003	0	0	0
T5	122269	1601	0	0
T14	202797	0	0	0
T15	0	91	0	0
T16	50683	349	0	0
T17	108513	417	0	0
T18	109543	10488	0	0
T19	666	4	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1523896	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1523896	0	0
T1	425	4	0	0
T2	849139	8292	0	0
T3	316941	2522	0	0
T4	3003	222	0	0
T5	122269	1924	0	0
T14	202797	0	0	0
T15	0	278	0	0
T16	50683	615	0	0
T17	108513	29	0	0
T18	109543	11224	0	0
T19	666	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3530741	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3530741	0	0
T1	425	4	0	0
T2	849139	8101	0	0
T3	316941	2729	0	0
T4	3003	222	0	0
T5	122269	1924	0	0
T14	202797	0	0	0
T15	0	157	0	0
T16	50683	291	0	0
T17	108513	2148	0	0
T18	109543	8743	0	0
T19	666	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	1456331	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	1456331	0	0
T1	425	5	0	0
T2	849139	6668	0	0
T3	316941	2519	0	0
T4	3003	0	0	0
T5	122269	2165	0	0
T14	202797	0	0	0
T15	0	296	0	0
T16	50683	656	0	0
T17	108513	16	0	0
T18	109543	5920	0	0
T19	666	2	0	0
T20	0	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316333919	3381438	0	0
DepthKnown_A	316333919	316200558	0	0
RvalidKnown_A	316333919	316200558	0	0
WreadyKnown_A	316333919	316200558	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	3381438	0	0
T1	425	5	0	0
T2	849139	10686	0	0
T3	316941	2570	0	0
T4	3003	0	0	0
T5	122269	2165	0	0
T14	202797	0	0	0
T15	0	139	0	0
T16	50683	309	0	0
T17	108513	1253	0	0
T18	109543	5154	0	0
T19	666	2	0	0
T20	0	180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316333919	316200558	0	0
T1	425	416	0	0
T2	849139	849070	0	0
T3	316941	316847	0	0
T4	3003	2945	0	0
T5	122269	120755	0	0
T14	202797	202794	0	0
T16	50683	50624	0	0
T17	108513	108480	0	0
T18	109543	109538	0	0
T19	666	599	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0