Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1656028	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

260766

1

T1

204

T2

127

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	648022	1			T1	592		T2	295		T3	53
values[0x0]	620241	1			T1	573		T2	310		T3	62
values[0x1]	648531	1			T1	594		T2	272		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1283595	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

633199

1

T1

546

T2

296

T3

61

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7299	1			T1	12		T2	7		T15	39
valid_sources[0x01]	7946	1			T1	8		T2	11		T15	75
valid_sources[0x02]	7675	1			T1	11		T2	3		T15	62
valid_sources[0x03]	7443	1			T1	4		T2	2		T15	39
valid_sources[0x04]	7335	1			T1	5		T2	8		T15	44
valid_sources[0x05]	6981	1			T1	5		T2	3		T15	56
valid_sources[0x06]	8614	1			T1	9		T2	2		T15	38
valid_sources[0x07]	7353	1			T1	7		T2	4		T15	61
valid_sources[0x08]	7101	1			T1	7		T2	4		T15	54
valid_sources[0x09]	7381	1			T1	7		T2	4		T15	56
valid_sources[0x0a]	7373	1			T1	2		T2	1		T15	47
valid_sources[0x0b]	9150	1			T1	5		T2	5		T15	52
valid_sources[0x0c]	7869	1			T1	7		T2	1		T15	56
valid_sources[0x0d]	6598	1			T1	4		T2	2		T15	48
valid_sources[0x0e]	7273	1			T1	4		T2	3		T3	2
valid_sources[0x0f]	7784	1			T1	7		T2	1		T15	62
valid_sources[0x10]	7623	1			T1	10		T2	1		T15	50
valid_sources[0x11]	6920	1			T1	8		T2	1		T15	51
valid_sources[0x12]	7084	1			T1	5		T2	2		T15	65
valid_sources[0x13]	6504	1			T1	12		T2	2		T15	66
valid_sources[0x14]	7534	1			T1	8		T2	5		T15	57
valid_sources[0x15]	7183	1			T1	12		T2	4		T15	68
valid_sources[0x16]	7631	1			T1	11		T15	58		T13	4
valid_sources[0x17]	7044	1			T1	9		T2	6		T15	60
valid_sources[0x18]	6735	1			T1	3		T2	7		T15	50
valid_sources[0x19]	9128	1			T1	2		T2	5		T15	55
valid_sources[0x1a]	7107	1			T1	8		T2	2		T15	43
valid_sources[0x1b]	7425	1			T1	6		T2	2		T15	40
valid_sources[0x1c]	7747	1			T1	16		T2	3		T15	51
valid_sources[0x1d]	8985	1			T1	5		T2	1		T15	43
valid_sources[0x1e]	7530	1			T1	1		T2	6		T15	36
valid_sources[0x1f]	8269	1			T1	9		T2	1		T15	65
valid_sources[0x20]	6875	1			T1	5		T2	3		T3	11
valid_sources[0x21]	6757	1			T1	10		T2	3		T15	69
valid_sources[0x22]	6935	1			T1	6		T2	3		T15	62
valid_sources[0x23]	6927	1			T1	6		T2	2		T15	51
valid_sources[0x24]	6402	1			T1	8		T2	5		T15	78
valid_sources[0x25]	7332	1			T1	3		T2	3		T15	63
valid_sources[0x26]	7845	1			T1	8		T2	5		T15	60
valid_sources[0x27]	6841	1			T1	8		T2	6		T15	31
valid_sources[0x28]	6553	1			T1	11		T2	4		T15	58
valid_sources[0x29]	8038	1			T1	10		T2	2		T15	71
valid_sources[0x2a]	7632	1			T1	6		T2	1		T15	65
valid_sources[0x2b]	6330	1			T1	3		T2	5		T15	60
valid_sources[0x2c]	7411	1			T1	11		T2	6		T3	3
valid_sources[0x2d]	7411	1			T1	4		T2	2		T15	61
valid_sources[0x2e]	6797	1			T1	1		T2	6		T15	44
valid_sources[0x2f]	7175	1			T1	5		T15	68		T13	18
valid_sources[0x30]	9554	1			T1	4		T2	4		T15	43
valid_sources[0x31]	7137	1			T1	8		T2	3		T15	79
valid_sources[0x32]	6751	1			T1	5		T2	1		T15	53
valid_sources[0x33]	6748	1			T1	7		T2	5		T15	58
valid_sources[0x34]	8970	1			T1	7		T2	2		T3	11
valid_sources[0x35]	7633	1			T1	10		T2	3		T15	70
valid_sources[0x36]	7473	1			T1	6		T2	10		T15	83
valid_sources[0x37]	7928	1			T1	5		T2	2		T15	59
valid_sources[0x38]	7152	1			T1	5		T2	3		T3	9
valid_sources[0x39]	8035	1			T1	12		T2	2		T15	47
valid_sources[0x3a]	6873	1			T1	3		T2	2		T15	101
valid_sources[0x3b]	7021	1			T1	9		T2	1		T15	33
valid_sources[0x3c]	7102	1			T1	7		T2	5		T15	61
valid_sources[0x3d]	8451	1			T1	4		T15	58		T4	3
valid_sources[0x3e]	9180	1			T1	6		T2	7		T3	5
valid_sources[0x3f]	7131	1			T1	8		T2	3		T15	67
valid_sources[0x40]	6528	1			T1	7		T2	9		T3	7
valid_sources[0x41]	6368	1			T1	7		T2	4		T15	74
valid_sources[0x42]	7152	1			T1	4		T15	74		T13	5
valid_sources[0x43]	6764	1			T1	9		T2	2		T15	36
valid_sources[0x44]	7169	1			T1	4		T2	2		T15	55
valid_sources[0x45]	7809	1			T1	7		T2	1		T15	76
valid_sources[0x46]	8488	1			T1	5		T2	4		T15	38
valid_sources[0x47]	7328	1			T1	7		T2	3		T15	44
valid_sources[0x48]	8063	1			T1	9		T2	4		T15	65
valid_sources[0x49]	7718	1			T1	2		T2	2		T15	73
valid_sources[0x4a]	7344	1			T1	6		T2	2		T15	46
valid_sources[0x4b]	7874	1			T1	8		T2	6		T15	54
valid_sources[0x4c]	7481	1			T1	10		T2	3		T15	32
valid_sources[0x4d]	7292	1			T1	6		T2	10		T15	53
valid_sources[0x4e]	8203	1			T1	3		T2	3		T3	11
valid_sources[0x4f]	7207	1			T1	12		T2	5		T15	43
valid_sources[0x50]	7923	1			T1	7		T2	7		T15	67
valid_sources[0x51]	8508	1			T1	3		T2	8		T15	49
valid_sources[0x52]	7307	1			T1	4		T2	2		T3	2
valid_sources[0x53]	7183	1			T1	6		T2	4		T15	49
valid_sources[0x54]	6926	1			T1	11		T2	1		T15	59
valid_sources[0x55]	7142	1			T1	4		T2	3		T3	2
valid_sources[0x56]	6073	1			T1	6		T2	4		T15	52
valid_sources[0x57]	9754	1			T1	5		T2	5		T3	1
valid_sources[0x58]	7846	1			T1	10		T2	2		T15	51
valid_sources[0x59]	6307	1			T1	15		T2	8		T3	3
valid_sources[0x5a]	7237	1			T1	8		T2	5		T15	57
valid_sources[0x5b]	6785	1			T1	5		T2	2		T15	64
valid_sources[0x5c]	7790	1			T1	6		T2	3		T15	72
valid_sources[0x5d]	7163	1			T1	6		T2	2		T15	63
valid_sources[0x5e]	7893	1			T1	9		T2	6		T15	64
valid_sources[0x5f]	7474	1			T1	7		T2	4		T3	3
valid_sources[0x60]	7824	1			T1	8		T2	7		T15	57
valid_sources[0x61]	8632	1			T1	5		T2	3		T15	59
valid_sources[0x62]	7992	1			T1	5		T2	5		T15	79
valid_sources[0x63]	7225	1			T1	5		T15	62		T13	6
valid_sources[0x64]	7291	1			T1	8		T2	4		T15	39
valid_sources[0x65]	6806	1			T1	3		T2	3		T3	1
valid_sources[0x66]	6577	1			T1	2		T2	3		T15	58
valid_sources[0x67]	6879	1			T1	4		T2	5		T15	68
valid_sources[0x68]	7604	1			T1	5		T2	2		T15	56
valid_sources[0x69]	7312	1			T1	5		T2	1		T15	76
valid_sources[0x6a]	7441	1			T1	4		T2	3		T15	57
valid_sources[0x6b]	8027	1			T1	7		T2	1		T3	12
valid_sources[0x6c]	7934	1			T1	12		T2	4		T15	42
valid_sources[0x6d]	8609	1			T1	7		T2	5		T15	50
valid_sources[0x6e]	7024	1			T1	7		T2	1		T15	58
valid_sources[0x6f]	7195	1			T1	2		T2	4		T15	80
valid_sources[0x70]	6800	1			T1	11		T2	2		T15	58
valid_sources[0x71]	8146	1			T1	5		T2	3		T3	3
valid_sources[0x72]	8515	1			T1	10		T2	2		T15	86
valid_sources[0x73]	7908	1			T1	11		T2	8		T3	10
valid_sources[0x74]	7851	1			T1	3		T2	3		T15	55
valid_sources[0x75]	7038	1			T1	10		T2	2		T15	54
valid_sources[0x76]	7725	1			T1	7		T2	4		T15	65
valid_sources[0x77]	6836	1			T1	7		T2	5		T3	2
valid_sources[0x78]	7129	1			T1	3		T2	3		T15	76
valid_sources[0x79]	7044	1			T1	6		T2	2		T15	72
valid_sources[0x7a]	6715	1			T1	9		T2	2		T15	37
valid_sources[0x7b]	7509	1			T1	6		T2	2		T15	40
valid_sources[0x7c]	7001	1			T1	8		T2	2		T15	110
valid_sources[0x7d]	7836	1			T1	7		T2	1		T3	6
valid_sources[0x7e]	6891	1			T1	9		T2	7		T15	76
valid_sources[0x7f]	6957	1			T1	2		T2	1		T15	51
valid_sources[0x80]	8536	1			T1	3		T2	2		T15	73

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27348

1

T1

23

T2

16

T15

174

values[0x0]

all_enables

biggest_size

206030

1

T1

157

T2

91

T3

19

values[0x1]

all_enables

biggest_size

27388

1

T1

24

T2

20

T3

1