Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	349328541	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	349328541	0	0
T1	7854224	961894	0	0
T2	122024	4309	0	0
T3	11317600	197936	0	0
T4	5499872	95364	0	0
T13	238560	8593	0	0
T14	27055504	481859	0	0
T15	1664040	68607	0	0
T16	811328	19933	0	0
T17	18488120	2619406	0	0
T18	6774096	163878	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7854224	7854056	0	0
T2	122024	117824	0	0
T3	11317600	11316480	0	0
T4	5499872	5496288	0	0
T13	238560	224560	0	0
T14	27055504	27054048	0	0
T15	1664040	1610840	0	0
T16	811328	805672	0	0
T17	18488120	18488008	0	0
T18	6774096	6748112	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7854224	7854056	0	0
T2	122024	117824	0	0
T3	11317600	11316480	0	0
T4	5499872	5496288	0	0
T13	238560	224560	0	0
T14	27055504	27054048	0	0
T15	1664040	1610840	0	0
T16	811328	805672	0	0
T17	18488120	18488008	0	0
T18	6774096	6748112	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7854224	7854056	0	0
T2	122024	117824	0	0
T3	11317600	11316480	0	0
T4	5499872	5496288	0	0
T13	238560	224560	0	0
T14	27055504	27054048	0	0
T15	1664040	1610840	0	0
T16	811328	805672	0	0
T17	18488120	18488008	0	0
T18	6774096	6748112	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	123931143	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	123931143	0	0
T1	140254	137548	0	0
T2	2179	1678	0	0
T3	202100	88063	0	0
T4	98212	37291	0	0
T13	4260	3500	0	0
T14	483134	472071	0	0
T15	29715	27933	0	0
T16	14488	8672	0	0
T17	330145	187000	0	0
T18	120966	67573	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	93432054	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	93432054	0	0
T1	140254	408389	0	0
T2	2179	877	0	0
T3	202100	24087	0	0
T4	98212	15745	0	0
T13	4260	1787	0	0
T14	483134	2838	0	0
T15	29715	14749	0	0
T16	14488	3623	0	0
T17	330145	757011	0	0
T18	120966	43568	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1431951	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1431951	0	0
T1	140254	243	0	0
T2	2179	34	0	0
T3	202100	1954	0	0
T4	98212	1051	0	0
T13	4260	58	0	0
T14	483134	151	0	0
T15	29715	359	0	0
T16	14488	175	0	0
T17	330145	36357	0	0
T18	120966	840	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	2998946	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	2998946	0	0
T1	140254	14210	0	0
T2	2179	34	0	0
T3	202100	209	0	0
T4	98212	629	0	0
T13	4260	58	0	0
T14	483134	30	0	0
T15	29715	359	0	0
T16	14488	174	0	0
T17	330145	31137	0	0
T18	120966	913	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1459188	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1459188	0	0
T1	140254	317	0	0
T2	2179	34	0	0
T3	202100	715	0	0
T4	98212	971	0	0
T13	4260	49	0	0
T14	483134	179	0	0
T15	29715	606	0	0
T16	14488	160	0	0
T17	330145	33753	0	0
T18	120966	764	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3503978	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3503978	0	0
T1	140254	14299	0	0
T2	2179	34	0	0
T3	202100	426	0	0
T4	98212	554	0	0
T13	4260	49	0	0
T14	483134	38	0	0
T15	29715	606	0	0
T16	14488	172	0	0
T17	330145	23238	0	0
T18	120966	721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1525863	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1525863	0	0
T1	140254	318	0	0
T2	2179	28	0	0
T3	202100	3557	0	0
T4	98212	1164	0	0
T13	4260	48	0	0
T14	483134	193	0	0
T15	29715	835	0	0
T16	14488	196	0	0
T17	330145	39838	0	0
T18	120966	611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3785596	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3785596	0	0
T1	140254	14715	0	0
T2	2179	28	0	0
T3	202100	1333	0	0
T4	98212	533	0	0
T13	4260	48	0	0
T14	483134	36	0	0
T15	29715	835	0	0
T16	14488	131	0	0
T17	330145	33557	0	0
T18	120966	675	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1454044	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1454044	0	0
T1	140254	242	0	0
T2	2179	23	0	0
T3	202100	1343	0	0
T4	98212	1156	0	0
T13	4260	330	0	0
T14	483134	128	0	0
T15	29715	339	0	0
T16	14488	165	0	0
T17	330145	30681	0	0
T18	120966	798	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3710221	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3710221	0	0
T1	140254	17685	0	0
T2	2179	23	0	0
T3	202100	361	0	0
T4	98212	679	0	0
T13	4260	330	0	0
T14	483134	34	0	0
T15	29715	339	0	0
T16	14488	143	0	0
T17	330145	28383	0	0
T18	120966	924	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1501395	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1501395	0	0
T1	140254	260	0	0
T2	2179	43	0	0
T3	202100	1372	0	0
T4	98212	1012	0	0
T13	4260	41	0	0
T14	483134	159	0	0
T15	29715	606	0	0
T16	14488	124	0	0
T17	330145	35446	0	0
T18	120966	692	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3231613	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3231613	0	0
T1	140254	15073	0	0
T2	2179	43	0	0
T3	202100	908	0	0
T4	98212	587	0	0
T13	4260	41	0	0
T14	483134	353	0	0
T15	29715	606	0	0
T16	14488	100	0	0
T17	330145	32403	0	0
T18	120966	742	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1502202	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1502202	0	0
T1	140254	248	0	0
T2	2179	33	0	0
T3	202100	2172	0	0
T4	98212	1071	0	0
T13	4260	51	0	0
T14	483134	172	0	0
T15	29715	338	0	0
T16	14488	106	0	0
T17	330145	38889	0	0
T18	120966	880	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	4307442	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	4307442	0	0
T1	140254	16260	0	0
T2	2179	33	0	0
T3	202100	277	0	0
T4	98212	684	0	0
T13	4260	51	0	0
T14	483134	36	0	0
T15	29715	338	0	0
T16	14488	101	0	0
T17	330145	30637	0	0
T18	120966	1035	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1426035	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1426035	0	0
T1	140254	309	0	0
T2	2179	34	0	0
T3	202100	2121	0	0
T4	98212	986	0	0
T13	4260	54	0	0
T14	483134	235	0	0
T15	29715	344	0	0
T16	14488	195	0	0
T17	330145	27843	0	0
T18	120966	781	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	2661177	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	2661177	0	0
T1	140254	14364	0	0
T2	2179	34	0	0
T3	202100	973	0	0
T4	98212	546	0	0
T13	4260	54	0	0
T14	483134	46	0	0
T15	29715	344	0	0
T16	14488	164	0	0
T17	330145	24188	0	0
T18	120966	755	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1368778	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1368778	0	0
T1	140254	253	0	0
T2	2179	32	0	0
T3	202100	1607	0	0
T4	98212	955	0	0
T13	4260	48	0	0
T14	483134	129	0	0
T15	29715	321	0	0
T16	14488	142	0	0
T17	330145	31871	0	0
T18	120966	708	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	2870387	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	2870387	0	0
T1	140254	16795	0	0
T2	2179	32	0	0
T3	202100	70	0	0
T4	98212	557	0	0
T13	4260	48	0	0
T14	483134	220	0	0
T15	29715	321	0	0
T16	14488	146	0	0
T17	330145	27177	0	0
T18	120966	684	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1481601	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1481601	0	0
T1	140254	275	0	0
T2	2179	41	0	0
T3	202100	1665	0	0
T4	98212	1116	0	0
T13	4260	45	0	0
T14	483134	143	0	0
T15	29715	598	0	0
T16	14488	179	0	0
T17	330145	30204	0	0
T18	120966	3069	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3715886	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3715886	0	0
T1	140254	17088	0	0
T2	2179	41	0	0
T3	202100	107	0	0
T4	98212	535	0	0
T13	4260	45	0	0
T14	483134	35	0	0
T15	29715	598	0	0
T16	14488	145	0	0
T17	330145	26386	0	0
T18	120966	3074	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1452676	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1452676	0	0
T1	140254	364	0	0
T2	2179	47	0	0
T3	202100	2291	0	0
T4	98212	1055	0	0
T13	4260	40	0	0
T14	483134	147	0	0
T15	29715	607	0	0
T16	14488	160	0	0
T17	330145	30746	0	0
T18	120966	862	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3037801	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3037801	0	0
T1	140254	18106	0	0
T2	2179	47	0	0
T3	202100	1436	0	0
T4	98212	584	0	0
T13	4260	40	0	0
T14	483134	35	0	0
T15	29715	607	0	0
T16	14488	125	0	0
T17	330145	23191	0	0
T18	120966	830	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1495371	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1495371	0	0
T1	140254	309	0	0
T2	2179	25	0	0
T3	202100	3803	0	0
T4	98212	917	0	0
T13	4260	64	0	0
T14	483134	172	0	0
T15	29715	334	0	0
T16	14488	106	0	0
T17	330145	38694	0	0
T18	120966	3003	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3321335	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3321335	0	0
T1	140254	17318	0	0
T2	2179	25	0	0
T3	202100	2098	0	0
T4	98212	620	0	0
T13	4260	64	0	0
T14	483134	45	0	0
T15	29715	334	0	0
T16	14488	103	0	0
T17	330145	28718	0	0
T18	120966	3066	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1509765	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1509765	0	0
T1	140254	252	0	0
T2	2179	30	0	0
T3	202100	2421	0	0
T4	98212	901	0	0
T13	4260	63	0	0
T14	483134	157	0	0
T15	29715	654	0	0
T16	14488	108	0	0
T17	330145	35924	0	0
T18	120966	777	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3188705	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3188705	0	0
T1	140254	10564	0	0
T2	2179	30	0	0
T3	202100	1106	0	0
T4	98212	622	0	0
T13	4260	63	0	0
T14	483134	30	0	0
T15	29715	654	0	0
T16	14488	100	0	0
T17	330145	24672	0	0
T18	120966	765	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1493910	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1493910	0	0
T1	140254	184	0	0
T2	2179	23	0	0
T3	202100	2174	0	0
T4	98212	1092	0	0
T13	4260	51	0	0
T14	483134	139	0	0
T15	29715	354	0	0
T16	14488	131	0	0
T17	330145	35632	0	0
T18	120966	841	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3660482	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3660482	0	0
T1	140254	9222	0	0
T2	2179	23	0	0
T3	202100	1033	0	0
T4	98212	636	0	0
T13	4260	51	0	0
T14	483134	45	0	0
T15	29715	354	0	0
T16	14488	66	0	0
T17	330145	30425	0	0
T18	120966	749	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1456150	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1456150	0	0
T1	140254	230	0	0
T2	2179	37	0	0
T3	202100	1690	0	0
T4	98212	916	0	0
T13	4260	62	0	0
T14	483134	103	0	0
T15	29715	337	0	0
T16	14488	190	0	0
T17	330145	35359	0	0
T18	120966	867	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	2940701	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	2940701	0	0
T1	140254	12744	0	0
T2	2179	37	0	0
T3	202100	262	0	0
T4	98212	562	0	0
T13	4260	62	0	0
T14	483134	29	0	0
T15	29715	337	0	0
T16	14488	158	0	0
T17	330145	31609	0	0
T18	120966	903	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1480049	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1480049	0	0
T1	140254	273	0	0
T2	2179	28	0	0
T3	202100	2820	0	0
T4	98212	785	0	0
T13	4260	49	0	0
T14	483134	140	0	0
T15	29715	338	0	0
T16	14488	153	0	0
T17	330145	32859	0	0
T18	120966	795	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	4022207	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	4022207	0	0
T1	140254	15063	0	0
T2	2179	28	0	0
T3	202100	1225	0	0
T4	98212	545	0	0
T13	4260	49	0	0
T14	483134	39	0	0
T15	29715	338	0	0
T16	14488	144	0	0
T17	330145	27090	0	0
T18	120966	839	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1444163	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1444163	0	0
T1	140254	251	0	0
T2	2179	32	0	0
T3	202100	1574	0	0
T4	98212	878	0	0
T13	4260	48	0	0
T14	483134	143	0	0
T15	29715	572	0	0
T16	14488	127	0	0
T17	330145	36592	0	0
T18	120966	752	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3468369	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3468369	0	0
T1	140254	11529	0	0
T2	2179	32	0	0
T3	202100	290	0	0
T4	98212	638	0	0
T13	4260	48	0	0
T14	483134	34	0	0
T15	29715	571	0	0
T16	14488	129	0	0
T17	330145	32713	0	0
T18	120966	847	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1542059	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1542059	0	0
T1	140254	325	0	0
T2	2179	29	0	0
T3	202100	4020	0	0
T4	98212	959	0	0
T13	4260	47	0	0
T14	483134	108	0	0
T15	29715	835	0	0
T16	14488	146	0	0
T17	330145	31763	0	0
T18	120966	824	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3361242	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3361242	0	0
T1	140254	14521	0	0
T2	2179	29	0	0
T3	202100	1431	0	0
T4	98212	570	0	0
T13	4260	47	0	0
T14	483134	25	0	0
T15	29715	833	0	0
T16	14488	144	0	0
T17	330145	22777	0	0
T18	120966	949	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1468090	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1468090	0	0
T1	140254	431	0	0
T2	2179	26	0	0
T3	202100	4885	0	0
T4	98212	878	0	0
T13	4260	63	0	0
T14	483134	190	0	0
T15	29715	334	0	0
T16	14488	198	0	0
T17	330145	30891	0	0
T18	120966	698	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	4220785	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	4220785	0	0
T1	140254	21214	0	0
T2	2179	26	0	0
T3	202100	1327	0	0
T4	98212	651	0	0
T13	4260	63	0	0
T14	483134	526	0	0
T15	29715	334	0	0
T16	14488	121	0	0
T17	330145	29546	0	0
T18	120966	794	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1466688	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1466688	0	0
T1	140254	301	0	0
T2	2179	28	0	0
T3	202100	295	0	0
T4	98212	879	0	0
T13	4260	65	0	0
T14	483134	146	0	0
T15	29715	346	0	0
T16	14488	210	0	0
T17	330145	28232	0	0
T18	120966	671	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3570057	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3570057	0	0
T1	140254	16316	0	0
T2	2179	28	0	0
T3	202100	302	0	0
T4	98212	506	0	0
T13	4260	65	0	0
T14	483134	29	0	0
T15	29715	346	0	0
T16	14488	271	0	0
T17	330145	23455	0	0
T18	120966	683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1438657	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1438657	0	0
T1	140254	261	0	0
T2	2179	27	0	0
T3	202100	1147	0	0
T4	98212	885	0	0
T13	4260	43	0	0
T14	483134	123	0	0
T15	29715	317	0	0
T16	14488	184	0	0
T17	330145	33104	0	0
T18	120966	682	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3576302	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3576302	0	0
T1	140254	15821	0	0
T2	2179	27	0	0
T3	202100	917	0	0
T4	98212	514	0	0
T13	4260	43	0	0
T14	483134	571	0	0
T15	29715	317	0	0
T16	14488	209	0	0
T17	330145	30329	0	0
T18	120966	764	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1478287	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1478287	0	0
T1	140254	310	0	0
T2	2179	41	0	0
T3	202100	1087	0	0
T4	98212	974	0	0
T13	4260	55	0	0
T14	483134	172	0	0
T15	29715	653	0	0
T16	14488	93	0	0
T17	330145	37436	0	0
T18	120966	936	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	2851499	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	2851499	0	0
T1	140254	14479	0	0
T2	2179	41	0	0
T3	202100	1456	0	0
T4	98212	637	0	0
T13	4260	55	0	0
T14	483134	44	0	0
T15	29715	653	0	0
T16	14488	36	0	0
T17	330145	28493	0	0
T18	120966	921	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1461064	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1461064	0	0
T1	140254	272	0	0
T2	2179	30	0	0
T3	202100	3598	0	0
T4	98212	974	0	0
T13	4260	46	0	0
T14	483134	149	0	0
T15	29715	311	0	0
T16	14488	140	0	0
T17	330145	37619	0	0
T18	120966	858	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3997597	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3997597	0	0
T1	140254	13360	0	0
T2	2179	30	0	0
T3	202100	2836	0	0
T4	98212	556	0	0
T13	4260	46	0	0
T14	483134	36	0	0
T15	29715	311	0	0
T16	14488	152	0	0
T17	330145	24255	0	0
T18	120966	839	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1434554	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1434554	0	0
T1	140254	292	0	0
T2	2179	37	0	0
T3	202100	3477	0	0
T4	98212	857	0	0
T13	4260	45	0	0
T14	483134	128	0	0
T15	29715	518	0	0
T16	14488	107	0	0
T17	330145	34472	0	0
T18	120966	811	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3182084	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3182084	0	0
T1	140254	13541	0	0
T2	2179	37	0	0
T3	202100	1036	0	0
T4	98212	498	0	0
T13	4260	45	0	0
T14	483134	35	0	0
T15	29715	518	0	0
T16	14488	111	0	0
T17	330145	33128	0	0
T18	120966	930	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1464110	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1464110	0	0
T1	140254	240	0	0
T2	2179	32	0	0
T3	202100	4170	0	0
T4	98212	1177	0	0
T13	4260	46	0	0
T14	483134	186	0	0
T15	29715	337	0	0
T16	14488	144	0	0
T17	330145	33279	0	0
T18	120966	751	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3701597	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3701597	0	0
T1	140254	14921	0	0
T2	2179	32	0	0
T3	202100	1339	0	0
T4	98212	644	0	0
T13	4260	46	0	0
T14	483134	394	0	0
T15	29715	337	0	0
T16	14488	140	0	0
T17	330145	28616	0	0
T18	120966	864	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1463666	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1463666	0	0
T1	140254	241	0	0
T2	2179	37	0	0
T3	202100	1473	0	0
T4	98212	976	0	0
T13	4260	42	0	0
T14	483134	166	0	0
T15	29715	910	0	0
T16	14488	98	0	0
T17	330145	29955	0	0
T18	120966	891	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	2954030	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	2954030	0	0
T1	140254	16478	0	0
T2	2179	37	0	0
T3	202100	448	0	0
T4	98212	527	0	0
T13	4260	42	0	0
T14	483134	32	0	0
T15	29715	910	0	0
T16	14488	78	0	0
T17	330145	27024	0	0
T18	120966	948	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1429931	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1429931	0	0
T1	140254	298	0	0
T2	2179	33	0	0
T3	202100	1795	0	0
T4	98212	1014	0	0
T13	4260	55	0	0
T14	483134	90	0	0
T15	29715	532	0	0
T16	14488	110	0	0
T17	330145	40082	0	0
T18	120966	857	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	2758370	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	2758370	0	0
T1	140254	17377	0	0
T2	2179	33	0	0
T3	202100	690	0	0
T4	98212	548	0	0
T13	4260	55	0	0
T14	483134	23	0	0
T15	29715	532	0	0
T16	14488	91	0	0
T17	330145	31109	0	0
T18	120966	874	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	1461582	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	1461582	0	0
T1	140254	269	0	0
T2	2179	33	0	0
T3	202100	2473	0	0
T4	98212	993	0	0
T13	4260	45	0	0
T14	483134	164	0	0
T15	29715	329	0	0
T16	14488	168	0	0
T17	330145	30863	0	0
T18	120966	765	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319792223	3775106	0	0
DepthKnown_A	319792223	319674004	0	0
RvalidKnown_A	319792223	319674004	0	0
WreadyKnown_A	319792223	319674004	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	3775106	0	0
T1	140254	15326	0	0
T2	2179	33	0	0
T3	202100	191	0	0
T4	98212	574	0	0
T13	4260	45	0	0
T14	483134	38	0	0
T15	29715	329	0	0
T16	14488	169	0	0
T17	330145	22755	0	0
T18	120966	865	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319792223	319674004	0	0
T1	140254	140251	0	0
T2	2179	2104	0	0
T3	202100	202080	0	0
T4	98212	98148	0	0
T13	4260	4010	0	0
T14	483134	483108	0	0
T15	29715	28765	0	0
T16	14488	14387	0	0
T17	330145	330143	0	0
T18	120966	120502	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0