Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1931720	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

304712

1

T1

390

T2

19

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	755326	1			T1	956		T2	85		T3	38
values[0x0]	726421	1			T1	912		T2	23		T3	38
values[0x1]	754685	1			T1	930		T2	92		T3	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1498594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

737838

1

T1

946

T2

68

T3

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9157	1			T1	17		T3	1		T4	1
valid_sources[0x01]	8488	1			T1	10		T2	1		T4	7
valid_sources[0x02]	9167	1			T1	4		T2	2		T4	7
valid_sources[0x03]	8736	1			T1	7		T4	9		T17	4
valid_sources[0x04]	8315	1			T1	7		T4	5		T17	1
valid_sources[0x05]	8346	1			T1	10		T4	6		T17	1
valid_sources[0x06]	9558	1			T1	11		T2	2		T3	1
valid_sources[0x07]	8059	1			T1	9		T2	1		T4	7
valid_sources[0x08]	8240	1			T1	11		T2	1		T4	4
valid_sources[0x09]	8419	1			T1	7		T4	16		T15	2
valid_sources[0x0a]	8469	1			T1	9		T2	1		T4	16
valid_sources[0x0b]	7879	1			T1	7		T4	7		T15	2
valid_sources[0x0c]	9704	1			T1	15		T2	1		T3	2
valid_sources[0x0d]	8832	1			T1	11		T4	9		T17	8
valid_sources[0x0e]	8588	1			T1	10		T2	2		T4	8
valid_sources[0x0f]	8792	1			T1	12		T3	2		T4	14
valid_sources[0x10]	8286	1			T1	13		T2	1		T3	2
valid_sources[0x11]	8076	1			T1	7		T4	12		T18	2
valid_sources[0x12]	8375	1			T1	14		T2	1		T4	3
valid_sources[0x13]	8202	1			T1	18		T2	2		T4	7
valid_sources[0x14]	9917	1			T1	9		T2	1		T4	8
valid_sources[0x15]	8079	1			T1	11		T3	4		T4	12
valid_sources[0x16]	8422	1			T1	12		T4	8		T17	5
valid_sources[0x17]	10704	1			T1	13		T4	7		T17	7
valid_sources[0x18]	8203	1			T1	12		T4	6		T15	6
valid_sources[0x19]	9240	1			T1	9		T4	9		T17	15
valid_sources[0x1a]	8023	1			T1	9		T2	1		T4	8
valid_sources[0x1b]	8426	1			T1	5		T2	3		T3	1
valid_sources[0x1c]	8380	1			T1	12		T4	17		T17	1
valid_sources[0x1d]	9044	1			T1	8		T2	2		T4	7
valid_sources[0x1e]	8885	1			T1	17		T3	1		T4	5
valid_sources[0x1f]	8159	1			T1	10		T2	3		T4	9
valid_sources[0x20]	8117	1			T1	13		T4	6		T15	1
valid_sources[0x21]	10091	1			T1	13		T3	1		T17	1
valid_sources[0x22]	10784	1			T1	12		T3	1		T4	18
valid_sources[0x23]	10604	1			T1	6		T3	1		T4	12
valid_sources[0x24]	8100	1			T1	21		T4	4		T15	4
valid_sources[0x25]	8805	1			T1	8		T2	2		T3	1
valid_sources[0x26]	8684	1			T1	12		T4	11		T18	1
valid_sources[0x27]	8929	1			T1	7		T2	1		T4	5
valid_sources[0x28]	8862	1			T1	16		T4	5		T17	17
valid_sources[0x29]	8214	1			T1	11		T4	7		T17	9
valid_sources[0x2a]	8852	1			T1	7		T4	12		T17	3
valid_sources[0x2b]	8028	1			T1	12		T3	1		T4	10
valid_sources[0x2c]	7709	1			T1	16		T2	1		T4	6
valid_sources[0x2d]	9013	1			T1	9		T4	3		T19	5
valid_sources[0x2e]	8919	1			T1	15		T2	1		T4	11
valid_sources[0x2f]	9477	1			T1	15		T2	3		T3	4
valid_sources[0x30]	9811	1			T1	9		T2	2		T4	1
valid_sources[0x31]	7550	1			T1	11		T2	1		T4	4
valid_sources[0x32]	8193	1			T1	10		T2	1		T3	1
valid_sources[0x33]	9345	1			T1	15		T2	1		T4	9
valid_sources[0x34]	9039	1			T1	12		T2	1		T3	1
valid_sources[0x35]	8146	1			T1	9		T2	1		T3	1
valid_sources[0x36]	9162	1			T1	8		T4	8		T19	10
valid_sources[0x37]	8642	1			T1	17		T2	2		T4	3
valid_sources[0x38]	7950	1			T1	17		T3	2		T4	8
valid_sources[0x39]	8142	1			T1	4		T2	2		T3	1
valid_sources[0x3a]	8075	1			T1	15		T4	6		T17	24
valid_sources[0x3b]	8162	1			T1	3		T2	5		T4	12
valid_sources[0x3c]	9758	1			T1	7		T3	1		T4	2
valid_sources[0x3d]	8337	1			T1	10		T3	1		T4	6
valid_sources[0x3e]	8600	1			T1	13		T2	1		T3	1
valid_sources[0x3f]	8383	1			T1	14		T2	4		T3	1
valid_sources[0x40]	8408	1			T1	7		T4	9		T19	9
valid_sources[0x41]	9227	1			T1	8		T2	1		T4	5
valid_sources[0x42]	9786	1			T1	13		T2	1		T4	4
valid_sources[0x43]	7821	1			T1	13		T4	11		T15	2
valid_sources[0x44]	8276	1			T1	14		T4	19		T17	5
valid_sources[0x45]	7988	1			T1	10		T2	1		T4	11
valid_sources[0x46]	8323	1			T1	10		T2	1		T3	1
valid_sources[0x47]	8376	1			T1	9		T4	11		T19	4
valid_sources[0x48]	9001	1			T1	13		T2	2		T3	1
valid_sources[0x49]	9757	1			T1	12		T4	4		T15	4
valid_sources[0x4a]	8874	1			T1	11		T2	1		T4	11
valid_sources[0x4b]	8879	1			T1	6		T4	9		T17	13
valid_sources[0x4c]	10084	1			T1	6		T4	8		T15	1
valid_sources[0x4d]	7849	1			T1	13		T2	2		T4	8
valid_sources[0x4e]	8842	1			T1	14		T3	1		T4	6
valid_sources[0x4f]	8269	1			T1	9		T3	1		T4	6
valid_sources[0x50]	8018	1			T1	17		T3	2		T4	12
valid_sources[0x51]	9506	1			T1	9		T4	9		T17	1
valid_sources[0x52]	8537	1			T1	10		T2	1		T4	4
valid_sources[0x53]	8576	1			T1	12		T3	1		T4	15
valid_sources[0x54]	8022	1			T1	14		T3	1		T4	11
valid_sources[0x55]	8585	1			T1	5		T2	2		T4	5
valid_sources[0x56]	9794	1			T1	14		T4	8		T17	4
valid_sources[0x57]	8262	1			T1	13		T4	7		T17	6
valid_sources[0x58]	8128	1			T1	14		T3	1		T4	12
valid_sources[0x59]	8791	1			T1	9		T2	2		T4	6
valid_sources[0x5a]	9335	1			T1	8		T2	2		T3	2
valid_sources[0x5b]	9263	1			T1	7		T4	8		T19	9
valid_sources[0x5c]	9059	1			T1	12		T2	2		T4	7
valid_sources[0x5d]	8893	1			T1	11		T4	6		T17	7
valid_sources[0x5e]	8858	1			T1	12		T4	15		T19	25
valid_sources[0x5f]	8334	1			T1	11		T2	1		T4	8
valid_sources[0x60]	8552	1			T1	12		T2	1		T4	10
valid_sources[0x61]	9333	1			T1	11		T4	10		T17	3
valid_sources[0x62]	7782	1			T1	12		T3	1		T4	7
valid_sources[0x63]	8231	1			T1	12		T2	2		T4	6
valid_sources[0x64]	8538	1			T1	16		T4	5		T17	3
valid_sources[0x65]	8313	1			T1	16		T4	8		T18	2
valid_sources[0x66]	8033	1			T1	14		T4	9		T17	2
valid_sources[0x67]	11200	1			T1	10		T2	1		T3	2
valid_sources[0x68]	9175	1			T1	14		T2	3		T4	14
valid_sources[0x69]	8049	1			T1	15		T3	3		T4	8
valid_sources[0x6a]	8173	1			T1	7		T2	1		T4	12
valid_sources[0x6b]	7758	1			T1	17		T3	1		T4	11
valid_sources[0x6c]	8430	1			T1	6		T3	1		T4	5
valid_sources[0x6d]	12235	1			T1	15		T2	2		T4	4
valid_sources[0x6e]	8373	1			T1	13		T2	1		T4	5
valid_sources[0x6f]	8657	1			T1	10		T2	1		T4	8
valid_sources[0x70]	8125	1			T1	16		T2	1		T3	2
valid_sources[0x71]	7910	1			T1	6		T3	2		T4	7
valid_sources[0x72]	9412	1			T1	6		T2	1		T3	1
valid_sources[0x73]	11046	1			T1	12		T2	1		T3	1
valid_sources[0x74]	8482	1			T1	15		T2	1		T4	3
valid_sources[0x75]	9352	1			T1	8		T3	1		T4	5
valid_sources[0x76]	8415	1			T1	11		T4	9		T18	1
valid_sources[0x77]	7862	1			T1	11		T3	1		T4	6
valid_sources[0x78]	8819	1			T1	15		T3	1		T4	8
valid_sources[0x79]	9357	1			T1	16		T2	1		T4	6
valid_sources[0x7a]	8969	1			T1	10		T2	1		T3	2
valid_sources[0x7b]	8306	1			T1	11		T2	3		T4	3
valid_sources[0x7c]	9338	1			T1	8		T3	1		T4	11
valid_sources[0x7d]	8415	1			T1	12		T2	1		T4	8
valid_sources[0x7e]	8675	1			T1	9		T2	1		T3	1
valid_sources[0x7f]	8713	1			T1	9		T2	2		T4	10
valid_sources[0x80]	8037	1			T1	19		T2	1		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31849

1

T1

33

T2

4

T3

1

values[0x0]

all_enables

biggest_size

240906

1

T1

323

T2

8

T3

15

values[0x1]

all_enables

biggest_size

31957

1

T1

34

T2

7

T3

2