Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	341698722	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	341698722	0	0
T1	3510752	73384	0	0
T2	483728	18589	0	0
T3	223888	4952	0	0
T4	2766568	55175	0	0
T13	40600	0	0	0
T14	8525104	161589	0	0
T15	11850104	217196	0	0
T16	0	10526	0	0
T17	7676424	1892672	0	0
T18	3763256	72786	0	0
T19	14067536	1471415	0	0
T20	0	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3510752	3510080	0	0
T2	483728	465920	0	0
T3	223888	221144	0	0
T4	2766568	2765280	0	0
T13	40600	28336	0	0
T14	8525104	8520848	0	0
T15	11850104	11761288	0	0
T17	7676424	7676312	0	0
T18	3763256	3762360	0	0
T19	14067536	14067424	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3510752	3510080	0	0
T2	483728	465920	0	0
T3	223888	221144	0	0
T4	2766568	2765280	0	0
T13	40600	28336	0	0
T14	8525104	8520848	0	0
T15	11850104	11761288	0	0
T17	7676424	7676312	0	0
T18	3763256	3762360	0	0
T19	14067536	14067424	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3510752	3510080	0	0
T2	483728	465920	0	0
T3	223888	221144	0	0
T4	2766568	2765280	0	0
T13	40600	28336	0	0
T14	8525104	8520848	0	0
T15	11850104	11761288	0	0
T17	7676424	7676312	0	0
T18	3763256	3762360	0	0
T19	14067536	14067424	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	127638835	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	127638835	0	0
T1	62692	32857	0	0
T2	8638	6482	0	0
T3	3998	2012	0	0
T4	49403	22815	0	0
T13	725	0	0	0
T14	152234	75304	0	0
T15	211609	92493	0	0
T16	0	4052	0	0
T17	137079	780195	0	0
T18	67201	32943	0	0
T19	251206	121357	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	86616834	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	86616834	0	0
T1	62692	9653	0	0
T2	8638	4164	0	0
T3	3998	1017	0	0
T4	49403	7830	0	0
T13	725	0	0	0
T14	152234	18740	0	0
T15	211609	31395	0	0
T16	0	3371	0	0
T17	137079	367128	0	0
T18	67201	9274	0	0
T19	251206	275587	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1538835	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1538835	0	0
T1	62692	758	0	0
T2	8638	130	0	0
T3	3998	24	0	0
T4	49403	273	0	0
T13	725	0	0	0
T14	152234	3951	0	0
T15	211609	1455	0	0
T16	0	39	0	0
T17	137079	12021	0	0
T18	67201	882	0	0
T19	251206	26155	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	2709688	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	2709688	0	0
T1	62692	367	0	0
T2	8638	130	0	0
T3	3998	43	0	0
T4	49403	122	0	0
T13	725	0	0	0
T14	152234	1019	0	0
T15	211609	686	0	0
T16	0	71	0	0
T17	137079	16733	0	0
T18	67201	421	0	0
T19	251206	8846	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1601928	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1601928	0	0
T1	62692	874	0	0
T2	8638	111	0	0
T3	3998	22	0	0
T4	49403	190	0	0
T13	725	0	0	0
T14	152234	555	0	0
T15	211609	5354	0	0
T16	0	32	0	0
T17	137079	14115	0	0
T18	67201	711	0	0
T19	251206	29914	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3906297	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3906297	0	0
T1	62692	303	0	0
T2	8638	111	0	0
T3	3998	10	0	0
T4	49403	87	0	0
T13	725	0	0	0
T14	152234	50	0	0
T15	211609	2398	0	0
T16	0	33	0	0
T17	137079	15231	0	0
T18	67201	320	0	0
T19	251206	11865	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1608340	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1608340	0	0
T1	62692	704	0	0
T2	8638	114	0	0
T3	3998	20	0	0
T4	49403	2569	0	0
T13	725	0	0	0
T14	152234	2445	0	0
T15	211609	1490	0	0
T16	0	92	0	0
T17	137079	9595	0	0
T18	67201	701	0	0
T19	251206	24433	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3442235	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3442235	0	0
T1	62692	400	0	0
T2	8638	114	0	0
T3	3998	57	0	0
T4	49403	1334	0	0
T13	725	0	0	0
T14	152234	699	0	0
T15	211609	566	0	0
T16	0	85	0	0
T17	137079	13649	0	0
T18	67201	355	0	0
T19	251206	10823	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1547679	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1547679	0	0
T1	62692	767	0	0
T2	8638	110	0	0
T3	3998	39	0	0
T4	49403	265	0	0
T13	725	0	0	0
T14	152234	1580	0	0
T15	211609	1922	0	0
T16	0	67	0	0
T17	137079	12598	0	0
T18	67201	716	0	0
T19	251206	34651	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3281931	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3281931	0	0
T1	62692	379	0	0
T2	8638	110	0	0
T3	3998	26	0	0
T4	49403	100	0	0
T13	725	0	0	0
T14	152234	248	0	0
T15	211609	941	0	0
T16	0	53	0	0
T17	137079	9751	0	0
T18	67201	309	0	0
T19	251206	9165	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1540121	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1540121	0	0
T1	62692	841	0	0
T2	8638	97	0	0
T3	3998	42	0	0
T4	49403	135	0	0
T13	725	0	0	0
T14	152234	823	0	0
T15	211609	1516	0	0
T16	0	100	0	0
T17	137079	14364	0	0
T18	67201	618	0	0
T19	251206	28508	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	2798846	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	2798846	0	0
T1	62692	404	0	0
T2	8638	97	0	0
T3	3998	38	0	0
T4	49403	79	0	0
T13	725	0	0	0
T14	152234	871	0	0
T15	211609	763	0	0
T16	0	62	0	0
T17	137079	14663	0	0
T18	67201	275	0	0
T19	251206	11135	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1523214	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1523214	0	0
T1	62692	778	0	0
T2	8638	770	0	0
T3	3998	24	0	0
T4	49403	254	0	0
T13	725	0	0	0
T14	152234	1203	0	0
T15	211609	1095	0	0
T16	0	102	0	0
T17	137079	15477	0	0
T18	67201	740	0	0
T19	251206	23849	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	2825958	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	2825958	0	0
T1	62692	347	0	0
T2	8638	770	0	0
T3	3998	57	0	0
T4	49403	103	0	0
T13	725	0	0	0
T14	152234	581	0	0
T15	211609	568	0	0
T16	0	73	0	0
T17	137079	15152	0	0
T18	67201	238	0	0
T19	251206	7422	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1560970	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1560970	0	0
T1	62692	835	0	0
T2	8638	108	0	0
T3	3998	39	0	0
T4	49403	204	0	0
T13	725	0	0	0
T14	152234	832	0	0
T15	211609	1477	0	0
T16	0	58	0	0
T17	137079	16067	0	0
T18	67201	757	0	0
T19	251206	30137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3818899	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3818899	0	0
T1	62692	450	0	0
T2	8638	108	0	0
T3	3998	46	0	0
T4	49403	71	0	0
T13	725	0	0	0
T14	152234	362	0	0
T15	211609	660	0	0
T16	0	52	0	0
T17	137079	17445	0	0
T18	67201	322	0	0
T19	251206	10559	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1560504	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1560504	0	0
T1	62692	813	0	0
T2	8638	124	0	0
T3	3998	10	0	0
T4	49403	195	0	0
T13	725	0	0	0
T14	152234	3903	0	0
T15	211609	1165	0	0
T16	0	62	0	0
T17	137079	14878	0	0
T18	67201	1053	0	0
T19	251206	30495	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3556074	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3556074	0	0
T1	62692	325	0	0
T2	8638	124	0	0
T3	3998	23	0	0
T4	49403	97	0	0
T13	725	0	0	0
T14	152234	1610	0	0
T15	211609	610	0	0
T16	0	52	0	0
T17	137079	12844	0	0
T18	67201	423	0	0
T19	251206	11000	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1587334	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1587334	0	0
T1	62692	740	0	0
T2	8638	110	0	0
T3	3998	10	0	0
T4	49403	248	0	0
T13	725	0	0	0
T14	152234	389	0	0
T15	211609	1368	0	0
T16	0	21	0	0
T17	137079	14134	0	0
T18	67201	822	0	0
T19	251206	29503	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3313720	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3313720	0	0
T1	62692	373	0	0
T2	8638	110	0	0
T3	3998	13	0	0
T4	49403	117	0	0
T13	725	0	0	0
T14	152234	539	0	0
T15	211609	671	0	0
T16	0	27	0	0
T17	137079	12030	0	0
T18	67201	380	0	0
T19	251206	12772	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1546285	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1546285	0	0
T1	62692	888	0	0
T2	8638	112	0	0
T3	3998	81	0	0
T4	49403	109	0	0
T13	725	0	0	0
T14	152234	1277	0	0
T15	211609	3427	0	0
T16	0	108	0	0
T17	137079	19143	0	0
T18	67201	797	0	0
T19	251206	30392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	2788496	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	2788496	0	0
T1	62692	410	0	0
T2	8638	112	0	0
T3	3998	57	0	0
T4	49403	61	0	0
T13	725	0	0	0
T14	152234	190	0	0
T15	211609	1712	0	0
T16	0	90	0	0
T17	137079	16965	0	0
T18	67201	325	0	0
T19	251206	11010	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1517409	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1517409	0	0
T1	62692	852	0	0
T2	8638	118	0	0
T3	3998	23	0	0
T4	49403	222	0	0
T13	725	0	0	0
T14	152234	765	0	0
T15	211609	1530	0	0
T16	0	100	0	0
T17	137079	19123	0	0
T18	67201	866	0	0
T19	251206	24717	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3001725	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3001725	0	0
T1	62692	407	0	0
T2	8638	118	0	0
T3	3998	21	0	0
T4	49403	59	0	0
T13	725	0	0	0
T14	152234	933	0	0
T15	211609	591	0	0
T16	0	73	0	0
T17	137079	17474	0	0
T18	67201	368	0	0
T19	251206	9098	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1511190	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1511190	0	0
T1	62692	721	0	0
T2	8638	110	0	0
T3	3998	15	0	0
T4	49403	2376	0	0
T13	725	0	0	0
T14	152234	3260	0	0
T15	211609	1279	0	0
T16	0	34	0	0
T17	137079	15978	0	0
T18	67201	636	0	0
T19	251206	32826	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3253887	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3253887	0	0
T1	62692	353	0	0
T2	8638	110	0	0
T3	3998	34	0	0
T4	49403	1126	0	0
T13	725	0	0	0
T14	152234	630	0	0
T15	211609	604	0	0
T16	0	9	0	0
T17	137079	10943	0	0
T18	67201	197	0	0
T19	251206	11400	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1631323	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1631323	0	0
T1	62692	714	0	0
T2	8638	109	0	0
T3	3998	29	0	0
T4	49403	182	0	0
T13	725	0	0	0
T14	152234	1750	0	0
T15	211609	1469	0	0
T16	0	44	0	0
T17	137079	10633	0	0
T18	67201	888	0	0
T19	251206	35055	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3123665	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3123665	0	0
T1	62692	277	0	0
T2	8638	109	0	0
T3	3998	60	0	0
T4	49403	94	0	0
T13	725	0	0	0
T14	152234	473	0	0
T15	211609	643	0	0
T16	0	44	0	0
T17	137079	11910	0	0
T18	67201	453	0	0
T19	251206	7632	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1575695	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1575695	0	0
T1	62692	923	0	0
T2	8638	113	0	0
T3	3998	34	0	0
T4	49403	171	0	0
T13	725	0	0	0
T14	152234	1439	0	0
T15	211609	7441	0	0
T16	0	41	0	0
T17	137079	16468	0	0
T18	67201	624	0	0
T19	251206	28616	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	2490511	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	2490511	0	0
T1	62692	352	0	0
T2	8638	113	0	0
T3	3998	32	0	0
T4	49403	114	0	0
T13	725	0	0	0
T14	152234	135	0	0
T15	211609	3451	0	0
T16	0	32	0	0
T17	137079	14596	0	0
T18	67201	336	0	0
T19	251206	8348	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1493295	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1493295	0	0
T1	62692	793	0	0
T2	8638	103	0	0
T3	3998	21	0	0
T4	49403	203	0	0
T13	725	0	0	0
T14	152234	448	0	0
T15	211609	3549	0	0
T16	0	44	0	0
T17	137079	15666	0	0
T18	67201	679	0	0
T19	251206	29110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	2557002	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	2557002	0	0
T1	62692	464	0	0
T2	8638	102	0	0
T3	3998	36	0	0
T4	49403	88	0	0
T13	725	0	0	0
T14	152234	606	0	0
T15	211609	1641	0	0
T16	0	46	0	0
T17	137079	14906	0	0
T18	67201	262	0	0
T19	251206	12832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1582888	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1582888	0	0
T1	62692	966	0	0
T2	8638	103	0	0
T3	3998	41	0	0
T4	49403	256	0	0
T13	725	0	0	0
T14	152234	1770	0	0
T15	211609	1411	0	0
T16	0	137	0	0
T17	137079	15866	0	0
T18	67201	726	0	0
T19	251206	34083	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	2945433	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	2945433	0	0
T1	62692	403	0	0
T2	8638	103	0	0
T3	3998	51	0	0
T4	49403	87	0	0
T13	725	0	0	0
T14	152234	840	0	0
T15	211609	658	0	0
T16	0	64	0	0
T17	137079	12147	0	0
T18	67201	324	0	0
T19	251206	10255	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1515583	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1515583	0	0
T1	62692	662	0	0
T2	8638	389	0	0
T3	3998	0	0	0
T4	49403	277	0	0
T13	725	0	0	0
T14	152234	1649	0	0
T15	211609	1806	0	0
T16	0	49	0	0
T17	137079	13730	0	0
T18	67201	839	0	0
T19	251206	25249	0	0
T20	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3678118	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3678118	0	0
T1	62692	251	0	0
T2	8638	389	0	0
T3	3998	0	0	0
T4	49403	126	0	0
T13	725	0	0	0
T14	152234	587	0	0
T15	211609	931	0	0
T16	0	46	0	0
T17	137079	11642	0	0
T18	67201	350	0	0
T19	251206	7656	0	0
T20	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1526000	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1526000	0	0
T1	62692	902	0	0
T2	8638	97	0	0
T3	3998	68	0	0
T4	49403	2575	0	0
T13	725	0	0	0
T14	152234	1183	0	0
T15	211609	4916	0	0
T16	0	16	0	0
T17	137079	7149	0	0
T18	67201	904	0	0
T19	251206	23870	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3151040	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3151040	0	0
T1	62692	364	0	0
T2	8638	97	0	0
T3	3998	87	0	0
T4	49403	1154	0	0
T13	725	0	0	0
T14	152234	305	0	0
T15	211609	2557	0	0
T16	0	16	0	0
T17	137079	8987	0	0
T18	67201	369	0	0
T19	251206	6580	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1611438	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1611438	0	0
T1	62692	857	0	0
T2	8638	102	0	0
T3	3998	18	0	0
T4	49403	233	0	0
T13	725	0	0	0
T14	152234	1556	0	0
T15	211609	3514	0	0
T16	0	85	0	0
T17	137079	12970	0	0
T18	67201	845	0	0
T19	251206	27979	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3148654	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3148654	0	0
T1	62692	316	0	0
T2	8638	102	0	0
T3	3998	18	0	0
T4	49403	75	0	0
T13	725	0	0	0
T14	152234	413	0	0
T15	211609	1679	0	0
T16	0	70	0	0
T17	137079	14704	0	0
T18	67201	393	0	0
T19	251206	9224	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1509230	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1509230	0	0
T1	62692	690	0	0
T2	8638	129	0	0
T3	3998	13	0	0
T4	49403	2466	0	0
T13	725	0	0	0
T14	152234	1844	0	0
T15	211609	1228	0	0
T16	0	84	0	0
T17	137079	16093	0	0
T18	67201	841	0	0
T19	251206	30573	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3130555	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3130555	0	0
T1	62692	343	0	0
T2	8638	129	0	0
T3	3998	38	0	0
T4	49403	1115	0	0
T13	725	0	0	0
T14	152234	375	0	0
T15	211609	662	0	0
T16	0	42	0	0
T17	137079	13407	0	0
T18	67201	338	0	0
T19	251206	10662	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1600699	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1600699	0	0
T1	62692	833	0	0
T2	8638	109	0	0
T3	3998	31	0	0
T4	49403	191	0	0
T13	725	0	0	0
T14	152234	1682	0	0
T15	211609	3656	0	0
T16	0	46	0	0
T17	137079	12483	0	0
T18	67201	989	0	0
T19	251206	29565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3572490	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3572490	0	0
T1	62692	406	0	0
T2	8638	109	0	0
T3	3998	22	0	0
T4	49403	109	0	0
T13	725	0	0	0
T14	152234	338	0	0
T15	211609	1684	0	0
T16	0	60	0	0
T17	137079	15231	0	0
T18	67201	394	0	0
T19	251206	8369	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1530925	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1530925	0	0
T1	62692	713	0	0
T2	8638	116	0	0
T3	3998	49	0	0
T4	49403	166	0	0
T13	725	0	0	0
T14	152234	3053	0	0
T15	211609	1924	0	0
T16	0	58	0	0
T17	137079	14220	0	0
T18	67201	724	0	0
T19	251206	26251	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3097125	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3097125	0	0
T1	62692	255	0	0
T2	8638	116	0	0
T3	3998	53	0	0
T4	49403	77	0	0
T13	725	0	0	0
T14	152234	693	0	0
T15	211609	956	0	0
T16	0	68	0	0
T17	137079	16417	0	0
T18	67201	291	0	0
T19	251206	9100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1558709	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1558709	0	0
T1	62692	666	0	0
T2	8638	109	0	0
T3	3998	99	0	0
T4	49403	163	0	0
T13	725	0	0	0
T14	152234	3125	0	0
T15	211609	1431	0	0
T16	0	32	0	0
T17	137079	12495	0	0
T18	67201	864	0	0
T19	251206	34291	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3748177	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3748177	0	0
T1	62692	312	0	0
T2	8638	109	0	0
T3	3998	54	0	0
T4	49403	76	0	0
T13	725	0	0	0
T14	152234	1293	0	0
T15	211609	728	0	0
T16	0	22	0	0
T17	137079	11799	0	0
T18	67201	463	0	0
T19	251206	14462	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1552267	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1552267	0	0
T1	62692	801	0	0
T2	8638	117	0	0
T3	3998	21	0	0
T4	49403	2051	0	0
T13	725	0	0	0
T14	152234	3126	0	0
T15	211609	1284	0	0
T16	0	66	0	0
T17	137079	9403	0	0
T18	67201	701	0	0
T19	251206	34738	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	2435973	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	2435973	0	0
T1	62692	354	0	0
T2	8638	117	0	0
T3	3998	18	0	0
T4	49403	1057	0	0
T13	725	0	0	0
T14	152234	1083	0	0
T15	211609	675	0	0
T16	0	56	0	0
T17	137079	8997	0	0
T18	67201	333	0	0
T19	251206	10975	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1555460	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1555460	0	0
T1	62692	664	0	0
T2	8638	130	0	0
T3	3998	67	0	0
T4	49403	262	0	0
T13	725	0	0	0
T14	152234	1929	0	0
T15	211609	1317	0	0
T16	0	64	0	0
T17	137079	17307	0	0
T18	67201	735	0	0
T19	251206	35773	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	2504269	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	2504269	0	0
T1	62692	345	0	0
T2	8638	130	0	0
T3	3998	65	0	0
T4	49403	108	0	0
T13	725	0	0	0
T14	152234	1705	0	0
T15	211609	660	0	0
T16	0	84	0	0
T17	137079	16264	0	0
T18	67201	321	0	0
T19	251206	10279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1555211	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1555211	0	0
T1	62692	612	0	0
T2	8638	119	0	0
T3	3998	36	0	0
T4	49403	275	0	0
T13	725	0	0	0
T14	152234	1669	0	0
T15	211609	3714	0	0
T16	0	41	0	0
T17	137079	13772	0	0
T18	67201	963	0	0
T19	251206	31399	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3685792	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3685792	0	0
T1	62692	285	0	0
T2	8638	119	0	0
T3	3998	50	0	0
T4	49403	109	0	0
T13	725	0	0	0
T14	152234	670	0	0
T15	211609	1849	0	0
T16	0	54	0	0
T17	137079	11146	0	0
T18	67201	416	0	0
T19	251206	14040	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	1562221	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	1562221	0	0
T1	62692	857	0	0
T2	8638	113	0	0
T3	3998	30	0	0
T4	49403	189	0	0
T13	725	0	0	0
T14	152234	1599	0	0
T15	211609	1305	0	0
T16	0	46	0	0
T17	137079	12473	0	0
T18	67201	675	0	0
T19	251206	26752	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312450193	3471740	0	0
DepthKnown_A	312450193	312321284	0	0
RvalidKnown_A	312450193	312321284	0	0
WreadyKnown_A	312450193	312321284	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	3471740	0	0
T1	62692	405	0	0
T2	8638	113	0	0
T3	3998	8	0	0
T4	49403	85	0	0
T13	725	0	0	0
T14	152234	1492	0	0
T15	211609	721	0	0
T16	0	51	0	0
T17	137079	12095	0	0
T18	67201	297	0	0
T19	251206	10078	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312450193	312321284	0	0
T1	62692	62680	0	0
T2	8638	8320	0	0
T3	3998	3949	0	0
T4	49403	49380	0	0
T13	725	506	0	0
T14	152234	152158	0	0
T15	211609	210023	0	0
T17	137079	137077	0	0
T18	67201	67185	0	0
T19	251206	251204	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0