Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1661589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261211

1

T1

2

T2

8

T3

187

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	650787	1			T1	19		T2	29		T3	493
values[0x0]	621289	1			T1	2		T2	5		T3	488
values[0x1]	650724	1			T1	16		T2	39		T3	506

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1287747	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

635053

1

T1

9

T2

28

T3

468

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7799	1			T18	4		T14	8		T19	18
valid_sources[0x01]	7244	1			T18	9		T14	2		T19	2
valid_sources[0x02]	7055	1			T17	2		T18	1		T14	7
valid_sources[0x03]	7739	1			T17	2		T18	6		T19	34
valid_sources[0x04]	7723	1			T3	8		T4	1		T17	1
valid_sources[0x05]	6954	1			T3	20		T18	10		T14	2
valid_sources[0x06]	7277	1			T1	3		T3	8		T17	2
valid_sources[0x07]	7145	1			T3	32		T18	10		T14	7
valid_sources[0x08]	7784	1			T3	13		T18	4		T14	9
valid_sources[0x09]	6832	1			T18	5		T14	6		T20	1
valid_sources[0x0a]	7185	1			T3	13		T18	6		T14	3
valid_sources[0x0b]	7267	1			T18	5		T14	1		T19	52
valid_sources[0x0c]	7708	1			T18	4		T14	7		T19	14
valid_sources[0x0d]	6901	1			T18	12		T14	8		T24	165
valid_sources[0x0e]	7352	1			T18	8		T14	13		T19	11
valid_sources[0x0f]	8654	1			T3	9		T18	5		T14	4
valid_sources[0x10]	7737	1			T4	1		T17	1		T18	3
valid_sources[0x11]	6822	1			T3	15		T18	5		T14	9
valid_sources[0x12]	8128	1			T3	25		T18	2		T14	7
valid_sources[0x13]	7645	1			T1	3		T18	6		T14	7
valid_sources[0x14]	7336	1			T1	2		T18	5		T14	7
valid_sources[0x15]	7990	1			T18	5		T14	4		T24	157
valid_sources[0x16]	7259	1			T3	14		T18	5		T14	14
valid_sources[0x17]	7908	1			T3	7		T4	1		T17	2
valid_sources[0x18]	7305	1			T18	6		T14	13		T21	1
valid_sources[0x19]	7069	1			T18	7		T14	8		T24	177
valid_sources[0x1a]	7072	1			T18	8		T14	13		T19	1
valid_sources[0x1b]	7213	1			T17	1		T18	5		T14	5
valid_sources[0x1c]	7596	1			T13	7		T16	140		T18	5
valid_sources[0x1d]	7512	1			T18	10		T14	10		T19	53
valid_sources[0x1e]	7292	1			T18	10		T14	13		T20	3
valid_sources[0x1f]	7690	1			T17	3		T18	6		T14	11
valid_sources[0x20]	7301	1			T3	7		T17	2		T18	6
valid_sources[0x21]	7537	1			T4	1		T18	5		T20	1
valid_sources[0x22]	7742	1			T18	8		T14	3		T19	53
valid_sources[0x23]	7363	1			T3	9		T17	2		T18	8
valid_sources[0x24]	7890	1			T3	7		T4	1		T18	5
valid_sources[0x25]	7061	1			T3	5		T18	4		T14	4
valid_sources[0x26]	7398	1			T3	5		T18	6		T14	5
valid_sources[0x27]	6726	1			T18	5		T14	10		T19	5
valid_sources[0x28]	7950	1			T2	8		T3	22		T18	3
valid_sources[0x29]	7498	1			T18	5		T14	3		T19	1
valid_sources[0x2a]	7108	1			T4	1		T17	3		T18	9
valid_sources[0x2b]	7239	1			T3	37		T17	1		T18	6
valid_sources[0x2c]	7053	1			T17	2		T18	3		T14	9
valid_sources[0x2d]	6794	1			T3	9		T4	2		T18	6
valid_sources[0x2e]	6920	1			T18	4		T20	2		T21	2
valid_sources[0x2f]	7022	1			T3	15		T17	1		T18	5
valid_sources[0x30]	8915	1			T3	7		T16	275		T18	5
valid_sources[0x31]	8529	1			T3	16		T4	1		T18	7
valid_sources[0x32]	6697	1			T3	13		T4	1		T17	1
valid_sources[0x33]	6769	1			T3	31		T18	4		T14	9
valid_sources[0x34]	6980	1			T18	5		T14	12		T21	1
valid_sources[0x35]	9522	1			T3	28		T13	17		T18	5
valid_sources[0x36]	9637	1			T17	5		T18	7		T14	5
valid_sources[0x37]	7504	1			T17	1		T18	7		T14	8
valid_sources[0x38]	7435	1			T3	16		T17	2		T18	5
valid_sources[0x39]	7045	1			T3	25		T18	11		T14	3
valid_sources[0x3a]	7331	1			T18	7		T14	11		T20	2
valid_sources[0x3b]	6843	1			T4	1		T18	7		T14	3
valid_sources[0x3c]	7000	1			T18	8		T14	3		T19	25
valid_sources[0x3d]	8051	1			T3	15		T18	4		T14	6
valid_sources[0x3e]	8139	1			T17	2		T14	7		T22	13
valid_sources[0x3f]	6975	1			T4	1		T18	6		T14	7
valid_sources[0x40]	7246	1			T17	1		T18	5		T14	17
valid_sources[0x41]	6817	1			T3	5		T18	2		T14	9
valid_sources[0x42]	8240	1			T4	1		T18	8		T14	10
valid_sources[0x43]	8151	1			T4	1		T17	1		T18	2
valid_sources[0x44]	7334	1			T3	14		T17	1		T18	6
valid_sources[0x45]	8003	1			T3	14		T18	4		T14	7
valid_sources[0x46]	9660	1			T18	6		T14	4		T19	5
valid_sources[0x47]	7309	1			T1	1		T4	1		T18	5
valid_sources[0x48]	7557	1			T3	27		T4	3		T17	1
valid_sources[0x49]	7325	1			T18	11		T14	7		T19	17
valid_sources[0x4a]	7742	1			T18	3		T14	1		T19	44
valid_sources[0x4b]	7856	1			T13	3		T18	6		T14	12
valid_sources[0x4c]	7046	1			T17	1		T18	5		T14	6
valid_sources[0x4d]	6911	1			T17	1		T18	5		T14	15
valid_sources[0x4e]	7170	1			T18	4		T14	11		T22	15
valid_sources[0x4f]	8201	1			T18	5		T14	4		T24	163
valid_sources[0x50]	7693	1			T4	1		T18	7		T14	5
valid_sources[0x51]	9250	1			T17	3		T18	4		T14	9
valid_sources[0x52]	8002	1			T17	2		T18	6		T14	4
valid_sources[0x53]	7344	1			T3	4		T18	4		T14	4
valid_sources[0x54]	8099	1			T4	1		T18	4		T14	8
valid_sources[0x55]	7268	1			T17	1		T18	8		T14	11
valid_sources[0x56]	7149	1			T18	9		T14	2		T24	181
valid_sources[0x57]	8172	1			T4	1		T17	2		T18	7
valid_sources[0x58]	8813	1			T18	8		T14	6		T21	2
valid_sources[0x59]	8657	1			T18	6		T14	2		T20	2
valid_sources[0x5a]	6983	1			T17	3		T18	3		T14	3
valid_sources[0x5b]	8608	1			T13	5		T18	4		T14	5
valid_sources[0x5c]	8373	1			T18	8		T14	5		T19	2
valid_sources[0x5d]	7462	1			T18	6		T14	4		T24	177
valid_sources[0x5e]	6900	1			T17	2		T18	6		T14	9
valid_sources[0x5f]	6882	1			T3	13		T17	1		T18	5
valid_sources[0x60]	7219	1			T18	7		T14	3		T20	3
valid_sources[0x61]	7801	1			T3	8		T17	1		T18	4
valid_sources[0x62]	7420	1			T3	11		T18	4		T14	8
valid_sources[0x63]	7834	1			T3	27		T4	1		T17	1
valid_sources[0x64]	8102	1			T18	3		T14	3		T19	4
valid_sources[0x65]	7016	1			T18	7		T14	10		T21	1
valid_sources[0x66]	7596	1			T4	1		T16	118		T18	2
valid_sources[0x67]	6762	1			T17	4		T18	3		T14	7
valid_sources[0x68]	8160	1			T17	2		T18	6		T14	7
valid_sources[0x69]	6715	1			T3	5		T18	3		T14	5
valid_sources[0x6a]	7500	1			T3	17		T4	1		T18	4
valid_sources[0x6b]	7380	1			T3	56		T18	10		T21	1
valid_sources[0x6c]	7156	1			T3	17		T18	9		T14	6
valid_sources[0x6d]	6989	1			T18	9		T14	8		T19	5
valid_sources[0x6e]	8197	1			T17	1		T18	8		T14	4
valid_sources[0x6f]	6805	1			T18	9		T14	7		T20	3
valid_sources[0x70]	7710	1			T18	6		T14	8		T19	2
valid_sources[0x71]	7993	1			T3	18		T18	2		T14	1
valid_sources[0x72]	7549	1			T2	7		T3	9		T18	5
valid_sources[0x73]	8013	1			T3	10		T18	5		T14	1
valid_sources[0x74]	7340	1			T18	9		T14	1		T19	4
valid_sources[0x75]	9535	1			T4	2		T18	6		T14	5
valid_sources[0x76]	6807	1			T18	6		T14	2		T20	2
valid_sources[0x77]	7805	1			T3	27		T17	3		T18	6
valid_sources[0x78]	6848	1			T4	1		T18	8		T14	2
valid_sources[0x79]	7061	1			T18	2		T14	17		T21	1
valid_sources[0x7a]	6397	1			T1	5		T18	8		T14	8
valid_sources[0x7b]	8355	1			T3	13		T16	376		T14	5
valid_sources[0x7c]	6776	1			T2	3		T3	6		T18	2
valid_sources[0x7d]	7988	1			T3	8		T18	7		T14	5
valid_sources[0x7e]	7135	1			T17	2		T18	8		T14	2
valid_sources[0x7f]	7764	1			T18	2		T14	14		T20	2
valid_sources[0x80]	7682	1			T4	1		T18	5		T14	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27574

1

T2

2

T3

14

T4

3

values[0x0]

all_enables

biggest_size

206024

1

T2

1

T3

150

T4

2

values[0x1]

all_enables

biggest_size

27613

1

T1

2

T2

5

T3

23