Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	352737763	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352737763	0	0
T1	1144472	26078	0	0
T2	230944	8449	0	0
T3	3187016	46696	0	0
T4	1589504	32498	0	0
T13	7881328	186406	0	0
T14	1733984	39958	0	0
T16	178752	11199	0	0
T17	7729288	253501	0	0
T18	154616	6872	0	0
T19	16064608	2519948	0	0
T20	0	2576	0	0
T21	0	6171	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1144472	1142904	0	0
T2	230944	216328	0	0
T3	3187016	3184776	0	0
T4	1589504	1587880	0	0
T13	7881328	7878192	0	0
T14	1733984	1731016	0	0
T16	178752	176512	0	0
T17	7729288	7726600	0	0
T18	154616	154112	0	0
T19	16064608	16064496	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1144472	1142904	0	0
T2	230944	216328	0	0
T3	3187016	3184776	0	0
T4	1589504	1587880	0	0
T13	7881328	7878192	0	0
T14	1733984	1731016	0	0
T16	178752	176512	0	0
T17	7729288	7726600	0	0
T18	154616	154112	0	0
T19	16064608	16064496	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1144472	1142904	0	0
T2	230944	216328	0	0
T3	3187016	3184776	0	0
T4	1589504	1587880	0	0
T13	7881328	7878192	0	0
T14	1733984	1731016	0	0
T16	178752	176512	0	0
T17	7729288	7726600	0	0
T18	154616	154112	0	0
T19	16064608	16064496	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	124606628	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	124606628	0	0
T1	20437	10077	0	0
T2	4124	3683	0	0
T3	56911	11435	0	0
T4	28384	12353	0	0
T13	140738	86033	0	0
T14	30964	13801	0	0
T16	3192	2801	0	0
T17	138023	136140	0	0
T18	2761	2669	0	0
T19	286868	165776	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	93966323	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	93966323	0	0
T1	20437	8726	0	0
T2	4124	1864	0	0
T3	56911	11925	0	0
T4	28384	10531	0	0
T13	140738	29961	0	0
T14	30964	6180	0	0
T16	3192	2800	0	0
T17	138023	58389	0	0
T18	2761	1401	0	0
T19	286868	786971	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1574063	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1574063	0	0
T1	20437	114	0	0
T2	4124	44	0	0
T3	56911	450	0	0
T4	28384	237	0	0
T13	140738	162	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	34	0	0
T18	2761	51	0	0
T19	286868	33212	0	0
T20	0	22	0	0
T21	0	201	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3559523	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3559523	0	0
T1	20437	93	0	0
T2	4124	44	0	0
T3	56911	421	0	0
T4	28384	243	0	0
T13	140738	858	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	1514	0	0
T18	2761	51	0	0
T19	286868	31157	0	0
T20	0	26	0	0
T21	0	210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1531501	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1531501	0	0
T1	20437	178	0	0
T2	4124	39	0	0
T3	56911	358	0	0
T4	28384	206	0	0
T13	140738	616	0	0
T14	30964	1847	0	0
T16	3192	204	0	0
T17	138023	16	0	0
T18	2761	56	0	0
T19	286868	26311	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3657127	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3657127	0	0
T1	20437	191	0	0
T2	4124	39	0	0
T3	56911	366	0	0
T4	28384	186	0	0
T13	140738	1147	0	0
T14	30964	854	0	0
T16	3192	204	0	0
T17	138023	1562	0	0
T18	2761	56	0	0
T19	286868	26448	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1515823	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1515823	0	0
T1	20437	118	0	0
T2	4124	37	0	0
T3	56911	444	0	0
T4	28384	152	0	0
T13	140738	757	0	0
T14	30964	5551	0	0
T16	3192	0	0	0
T17	138023	5	0	0
T18	2761	41	0	0
T19	286868	32180	0	0
T20	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3666217	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3666217	0	0
T1	20437	160	0	0
T2	4124	37	0	0
T3	56911	479	0	0
T4	28384	122	0	0
T13	140738	189	0	0
T14	30964	2610	0	0
T16	3192	0	0	0
T17	138023	13	0	0
T18	2761	41	0	0
T19	286868	36255	0	0
T20	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1529413	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1529413	0	0
T1	20437	48	0	0
T2	4124	323	0	0
T3	56911	449	0	0
T4	28384	290	0	0
T13	140738	1401	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	26	0	0
T18	2761	47	0	0
T19	286868	28405	0	0
T20	0	71	0	0
T21	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3575073	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3575073	0	0
T1	20437	81	0	0
T2	4124	323	0	0
T3	56911	495	0	0
T4	28384	254	0	0
T13	140738	984	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	3022	0	0
T18	2761	47	0	0
T19	286868	26650	0	0
T20	0	88	0	0
T21	0	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1469070	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1469070	0	0
T1	20437	149	0	0
T2	4124	29	0	0
T3	56911	403	0	0
T4	28384	219	0	0
T13	140738	2897	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	36	0	0
T18	2761	47	0	0
T19	286868	22528	0	0
T20	0	28	0	0
T21	0	137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3650058	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3650058	0	0
T1	20437	145	0	0
T2	4124	29	0	0
T3	56911	409	0	0
T4	28384	171	0	0
T13	140738	1657	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	2954	0	0
T18	2761	47	0	0
T19	286868	20856	0	0
T20	0	57	0	0
T21	0	204	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1518648	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1518648	0	0
T1	20437	138	0	0
T2	4124	49	0	0
T3	56911	469	0	0
T4	28384	168	0	0
T13	140738	3318	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	16	0	0
T18	2761	59	0	0
T19	286868	27897	0	0
T20	0	73	0	0
T21	0	270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3940267	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3940267	0	0
T1	20437	186	0	0
T2	4124	49	0	0
T3	56911	443	0	0
T4	28384	223	0	0
T13	140738	2437	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	1386	0	0
T18	2761	59	0	0
T19	286868	27130	0	0
T20	0	83	0	0
T21	0	240	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1516783	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1516783	0	0
T1	20437	120	0	0
T2	4124	38	0	0
T3	56911	472	0	0
T4	28384	203	0	0
T13	140738	996	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	34	0	0
T18	2761	57	0	0
T19	286868	32569	0	0
T20	0	30	0	0
T21	0	244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3485839	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3485839	0	0
T1	20437	129	0	0
T2	4124	37	0	0
T3	56911	487	0	0
T4	28384	155	0	0
T13	140738	1234	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	2837	0	0
T18	2761	57	0	0
T19	286868	31472	0	0
T20	0	28	0	0
T21	0	188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1494339	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1494339	0	0
T1	20437	141	0	0
T2	4124	25	0	0
T3	56911	491	0	0
T4	28384	218	0	0
T13	140738	1282	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	18	0	0
T18	2761	59	0	0
T19	286868	37029	0	0
T20	0	84	0	0
T21	0	181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3524560	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3524560	0	0
T1	20437	109	0	0
T2	4124	25	0	0
T3	56911	472	0	0
T4	28384	155	0	0
T13	140738	1379	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	940	0	0
T18	2761	59	0	0
T19	286868	31211	0	0
T20	0	65	0	0
T21	0	170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1522199	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1522199	0	0
T1	20437	67	0	0
T2	4124	35	0	0
T3	56911	454	0	0
T4	28384	238	0	0
T13	140738	4450	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	10	0	0
T18	2761	63	0	0
T19	286868	28205	0	0
T20	0	72	0	0
T21	0	239	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	4151943	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	4151943	0	0
T1	20437	99	0	0
T2	4124	35	0	0
T3	56911	533	0	0
T4	28384	163	0	0
T13	140738	1816	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	543	0	0
T18	2761	63	0	0
T19	286868	24040	0	0
T20	0	78	0	0
T21	0	134	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1546708	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1546708	0	0
T1	20437	140	0	0
T2	4124	29	0	0
T3	56911	441	0	0
T4	28384	151	0	0
T13	140738	1417	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	23	0	0
T18	2761	51	0	0
T19	286868	31677	0	0
T20	0	61	0	0
T21	0	208	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3503811	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3503811	0	0
T1	20437	108	0	0
T2	4124	29	0	0
T3	56911	428	0	0
T4	28384	172	0	0
T13	140738	86	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	2088	0	0
T18	2761	51	0	0
T19	286868	28366	0	0
T20	0	43	0	0
T21	0	182	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1531815	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1531815	0	0
T1	20437	117	0	0
T2	4124	41	0	0
T3	56911	394	0	0
T4	28384	151	0	0
T13	140738	119	0	0
T14	30964	2179	0	0
T16	3192	236	0	0
T17	138023	13	0	0
T18	2761	51	0	0
T19	286868	25394	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3182351	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3182351	0	0
T1	20437	107	0	0
T2	4124	41	0	0
T3	56911	402	0	0
T4	28384	124	0	0
T13	140738	387	0	0
T14	30964	989	0	0
T16	3192	236	0	0
T17	138023	1627	0	0
T18	2761	51	0	0
T19	286868	25668	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1508077	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1508077	0	0
T1	20437	153	0	0
T2	4124	47	0	0
T3	56911	310	0	0
T4	28384	185	0	0
T13	140738	3350	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	37	0	0
T18	2761	50	0	0
T19	286868	26257	0	0
T20	0	73	0	0
T21	0	230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3677407	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3677407	0	0
T1	20437	93	0	0
T2	4124	47	0	0
T3	56911	450	0	0
T4	28384	196	0	0
T13	140738	3214	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	2998	0	0
T18	2761	50	0	0
T19	286868	28281	0	0
T20	0	101	0	0
T21	0	243	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1488851	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1488851	0	0
T1	20437	158	0	0
T2	4124	26	0	0
T3	56911	375	0	0
T4	28384	191	0	0
T13	140738	1439	0	0
T14	30964	0	0	0
T16	3192	206	0	0
T17	138023	7	0	0
T18	2761	52	0	0
T19	286868	26669	0	0
T20	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3394842	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3394842	0	0
T1	20437	139	0	0
T2	4124	26	0	0
T3	56911	477	0	0
T4	28384	155	0	0
T13	140738	675	0	0
T14	30964	0	0	0
T16	3192	206	0	0
T17	138023	87	0	0
T18	2761	52	0	0
T19	286868	26208	0	0
T20	0	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1580667	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1580667	0	0
T1	20437	125	0	0
T2	4124	37	0	0
T3	56911	469	0	0
T4	28384	75	0	0
T13	140738	20	0	0
T14	30964	0	0	0
T16	3192	278	0	0
T17	138023	7	0	0
T18	2761	41	0	0
T19	286868	29250	0	0
T20	0	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3790301	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3790301	0	0
T1	20437	114	0	0
T2	4124	37	0	0
T3	56911	384	0	0
T4	28384	106	0	0
T13	140738	929	0	0
T14	30964	0	0	0
T16	3192	278	0	0
T17	138023	2015	0	0
T18	2761	41	0	0
T19	286868	31241	0	0
T20	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1564186	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1564186	0	0
T1	20437	137	0	0
T2	4124	41	0	0
T3	56911	318	0	0
T4	28384	200	0	0
T13	140738	813	0	0
T14	30964	1649	0	0
T16	3192	0	0	0
T17	138023	18	0	0
T18	2761	52	0	0
T19	286868	33401	0	0
T20	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3156259	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3156259	0	0
T1	20437	136	0	0
T2	4124	41	0	0
T3	56911	337	0	0
T4	28384	203	0	0
T13	140738	253	0	0
T14	30964	703	0	0
T16	3192	0	0	0
T17	138023	1734	0	0
T18	2761	52	0	0
T19	286868	31574	0	0
T20	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1491123	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1491123	0	0
T1	20437	214	0	0
T2	4124	27	0	0
T3	56911	373	0	0
T4	28384	178	0	0
T13	140738	2863	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	29	0	0
T18	2761	58	0	0
T19	286868	30370	0	0
T20	0	32	0	0
T21	0	161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	2830943	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	2830943	0	0
T1	20437	227	0	0
T2	4124	26	0	0
T3	56911	376	0	0
T4	28384	110	0	0
T13	140738	1050	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	1990	0	0
T18	2761	58	0	0
T19	286868	34156	0	0
T20	0	57	0	0
T21	0	177	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1494706	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1494706	0	0
T1	20437	145	0	0
T2	4124	36	0	0
T3	56911	310	0	0
T4	28384	132	0	0
T13	140738	1269	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	19	0	0
T18	2761	54	0	0
T19	286868	18416	0	0
T20	0	61	0	0
T21	0	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	4039252	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	4039252	0	0
T1	20437	110	0	0
T2	4124	36	0	0
T3	56911	352	0	0
T4	28384	96	0	0
T13	140738	967	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	1744	0	0
T18	2761	54	0	0
T19	286868	23862	0	0
T20	0	54	0	0
T21	0	206	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1527156	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1527156	0	0
T1	20437	124	0	0
T2	4124	32	0	0
T3	56911	423	0	0
T4	28384	178	0	0
T13	140738	1111	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	37	0	0
T18	2761	55	0	0
T19	286868	29161	0	0
T20	0	49	0	0
T21	0	221	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3394894	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3394894	0	0
T1	20437	170	0	0
T2	4124	32	0	0
T3	56911	460	0	0
T4	28384	156	0	0
T13	140738	905	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	3243	0	0
T18	2761	55	0	0
T19	286868	31979	0	0
T20	0	47	0	0
T21	0	199	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1484260	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1484260	0	0
T1	20437	118	0	0
T2	4124	37	0	0
T3	56911	399	0	0
T4	28384	260	0	0
T13	140738	1234	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	11	0	0
T18	2761	49	0	0
T19	286868	29683	0	0
T20	0	10	0	0
T21	0	137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3378067	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3378067	0	0
T1	20437	163	0	0
T2	4124	37	0	0
T3	56911	394	0	0
T4	28384	154	0	0
T13	140738	227	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	1618	0	0
T18	2761	49	0	0
T19	286868	34387	0	0
T20	0	21	0	0
T21	0	142	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1534918	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1534918	0	0
T1	20437	185	0	0
T2	4124	33	0	0
T3	56911	372	0	0
T4	28384	208	0	0
T13	140738	742	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	21	0	0
T18	2761	44	0	0
T19	286868	26309	0	0
T20	0	94	0	0
T21	0	233	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3045734	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3045734	0	0
T1	20437	168	0	0
T2	4124	33	0	0
T3	56911	401	0	0
T4	28384	191	0	0
T13	140738	449	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	4397	0	0
T18	2761	44	0	0
T19	286868	26209	0	0
T20	0	96	0	0
T21	0	226	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1493493	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1493493	0	0
T1	20437	112	0	0
T2	4124	36	0	0
T3	56911	502	0	0
T4	28384	138	0	0
T13	140738	2521	0	0
T14	30964	0	0	0
T16	3192	541	0	0
T17	138023	19	0	0
T18	2761	48	0	0
T19	286868	25114	0	0
T20	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	2911330	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	2911330	0	0
T1	20437	113	0	0
T2	4124	36	0	0
T3	56911	494	0	0
T4	28384	128	0	0
T13	140738	1495	0	0
T14	30964	0	0	0
T16	3192	541	0	0
T17	138023	2935	0	0
T18	2761	48	0	0
T19	286868	21355	0	0
T20	0	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1525231	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1525231	0	0
T1	20437	131	0	0
T2	4124	38	0	0
T3	56911	533	0	0
T4	28384	168	0	0
T13	140738	1152	0	0
T14	30964	2573	0	0
T16	3192	272	0	0
T17	138023	15	0	0
T18	2761	40	0	0
T19	286868	33170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	2633819	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	2633819	0	0
T1	20437	168	0	0
T2	4124	38	0	0
T3	56911	529	0	0
T4	28384	175	0	0
T13	140738	1090	0	0
T14	30964	1022	0	0
T16	3192	272	0	0
T17	138023	2003	0	0
T18	2761	40	0	0
T19	286868	32116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1543924	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1543924	0	0
T1	20437	140	0	0
T2	4124	245	0	0
T3	56911	483	0	0
T4	28384	175	0	0
T13	140738	1066	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	17	0	0
T18	2761	51	0	0
T19	286868	38387	0	0
T20	0	69	0	0
T21	0	217	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3234043	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3234043	0	0
T1	20437	146	0	0
T2	4124	245	0	0
T3	56911	457	0	0
T4	28384	241	0	0
T13	140738	1033	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	2021	0	0
T18	2761	51	0	0
T19	286868	37766	0	0
T20	0	44	0	0
T21	0	158	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1510786	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1510786	0	0
T1	20437	133	0	0
T2	4124	30	0	0
T3	56911	411	0	0
T4	28384	127	0	0
T13	140738	1575	0	0
T14	30964	0	0	0
T16	3192	272	0	0
T17	138023	50	0	0
T18	2761	53	0	0
T19	286868	29024	0	0
T20	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3360039	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3360039	0	0
T1	20437	91	0	0
T2	4124	30	0	0
T3	56911	403	0	0
T4	28384	92	0	0
T13	140738	1807	0	0
T14	30964	0	0	0
T16	3192	272	0	0
T17	138023	4606	0	0
T18	2761	53	0	0
T19	286868	32902	0	0
T20	0	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1535717	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1535717	0	0
T1	20437	92	0	0
T2	4124	36	0	0
T3	56911	422	0	0
T4	28384	188	0	0
T13	140738	3045	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	30	0	0
T18	2761	54	0	0
T19	286868	29745	0	0
T20	0	25	0	0
T21	0	205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3638898	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3638898	0	0
T1	20437	173	0	0
T2	4124	36	0	0
T3	56911	546	0	0
T4	28384	155	0	0
T13	140738	1712	0	0
T14	30964	0	0	0
T16	3192	0	0	0
T17	138023	3241	0	0
T18	2761	54	0	0
T19	286868	30929	0	0
T20	0	40	0	0
T21	0	205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1516769	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1516769	0	0
T1	20437	90	0	0
T2	4124	32	0	0
T3	56911	431	0	0
T4	28384	219	0	0
T13	140738	161	0	0
T14	30964	0	0	0
T16	3192	287	0	0
T17	138023	26	0	0
T18	2761	64	0	0
T19	286868	23106	0	0
T20	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3513045	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3513045	0	0
T1	20437	137	0	0
T2	4124	32	0	0
T3	56911	406	0	0
T4	28384	224	0	0
T13	140738	1083	0	0
T14	30964	0	0	0
T16	3192	287	0	0
T17	138023	3659	0	0
T18	2761	64	0	0
T19	286868	25562	0	0
T20	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	1500072	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	1500072	0	0
T1	20437	151	0	0
T2	4124	30	0	0
T3	56911	467	0	0
T4	28384	200	0	0
T13	140738	675	0	0
T14	30964	0	0	0
T16	3192	503	0	0
T17	138023	9	0	0
T18	2761	54	0	0
T19	286868	27008	0	0
T20	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324394680	3218872	0	0
DepthKnown_A	324394680	324268616	0	0
RvalidKnown_A	324394680	324268616	0	0
WreadyKnown_A	324394680	324268616	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	3218872	0	0
T1	20437	181	0	0
T2	4124	30	0	0
T3	56911	512	0	0
T4	28384	209	0	0
T13	140738	898	0	0
T14	30964	0	0	0
T16	3192	503	0	0
T17	138023	1612	0	0
T18	2761	54	0	0
T19	286868	28944	0	0
T20	0	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324394680	324268616	0	0
T1	20437	20409	0	0
T2	4124	3863	0	0
T3	56911	56871	0	0
T4	28384	28355	0	0
T13	140738	140682	0	0
T14	30964	30911	0	0
T16	3192	3152	0	0
T17	138023	137975	0	0
T18	2761	2752	0	0
T19	286868	286866	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0