Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1802579	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

284209

1

T1

11

T2

99

T3

409

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	705878	1			T1	39		T2	429		T3	999
values[0x0]	674548	1			T1	31		T2	60		T3	931
values[0x1]	706362	1			T1	55		T2	459		T3	1028

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1397737	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

689051

1

T1

37

T2

366

T3

987

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8414	1			T1	1		T2	6		T3	11
valid_sources[0x01]	7851	1			T1	1		T2	1		T3	7
valid_sources[0x02]	7212	1			T2	5		T3	16		T4	2
valid_sources[0x03]	9653	1			T2	6		T3	8		T4	2
valid_sources[0x04]	7990	1			T2	5		T3	11		T4	7
valid_sources[0x05]	7345	1			T2	1		T3	12		T4	1
valid_sources[0x06]	9287	1			T1	2		T2	2		T3	18
valid_sources[0x07]	7655	1			T1	2		T2	3		T3	5
valid_sources[0x08]	7390	1			T2	2		T3	17		T4	41
valid_sources[0x09]	8151	1			T1	1		T2	4		T3	9
valid_sources[0x0a]	8559	1			T2	5		T3	34		T19	1
valid_sources[0x0b]	7430	1			T3	7		T4	2		T19	13
valid_sources[0x0c]	8291	1			T2	8		T3	6		T4	3
valid_sources[0x0d]	7862	1			T2	4		T3	7		T4	8
valid_sources[0x0e]	7754	1			T1	2		T2	7		T3	3
valid_sources[0x0f]	7758	1			T1	1		T2	3		T3	5
valid_sources[0x10]	8076	1			T2	3		T3	13		T4	13
valid_sources[0x11]	7561	1			T2	2		T3	20		T4	4
valid_sources[0x12]	7829	1			T2	1		T3	11		T4	3
valid_sources[0x13]	8662	1			T2	3		T3	14		T4	5
valid_sources[0x14]	7627	1			T2	5		T3	10		T4	19
valid_sources[0x15]	7584	1			T1	3		T2	7		T3	14
valid_sources[0x16]	8042	1			T1	1		T2	4		T3	11
valid_sources[0x17]	9064	1			T1	1		T2	6		T3	11
valid_sources[0x18]	7834	1			T1	1		T2	3		T3	16
valid_sources[0x19]	8348	1			T2	6		T3	5		T4	17
valid_sources[0x1a]	8016	1			T2	8		T3	7		T4	4
valid_sources[0x1b]	7598	1			T2	2		T3	4		T4	6
valid_sources[0x1c]	8161	1			T1	1		T2	2		T3	10
valid_sources[0x1d]	8262	1			T2	4		T3	2		T4	13
valid_sources[0x1e]	8221	1			T2	2		T3	14		T4	4
valid_sources[0x1f]	8280	1			T2	6		T3	10		T4	1
valid_sources[0x20]	10175	1			T1	1		T2	4		T3	14
valid_sources[0x21]	8113	1			T2	4		T3	9		T4	23
valid_sources[0x22]	7746	1			T2	1		T3	7		T4	2
valid_sources[0x23]	7957	1			T1	1		T2	7		T3	8
valid_sources[0x24]	7868	1			T2	3		T3	9		T17	2
valid_sources[0x25]	8363	1			T1	1		T2	1		T3	8
valid_sources[0x26]	8121	1			T2	2		T3	5		T4	25
valid_sources[0x27]	7575	1			T1	2		T2	3		T3	16
valid_sources[0x28]	7966	1			T1	1		T2	2		T3	11
valid_sources[0x29]	8197	1			T1	1		T2	5		T3	7
valid_sources[0x2a]	8039	1			T2	4		T3	5		T17	1
valid_sources[0x2b]	8549	1			T2	6		T3	8		T4	2
valid_sources[0x2c]	8770	1			T1	1		T2	3		T3	2
valid_sources[0x2d]	8604	1			T1	1		T2	7		T3	12
valid_sources[0x2e]	7176	1			T1	2		T2	5		T3	16
valid_sources[0x2f]	7543	1			T2	2		T3	16		T4	9
valid_sources[0x30]	8682	1			T1	1		T2	2		T3	13
valid_sources[0x31]	8695	1			T2	4		T3	9		T4	7
valid_sources[0x32]	7828	1			T1	2		T2	3		T3	15
valid_sources[0x33]	8357	1			T1	1		T2	1		T3	10
valid_sources[0x34]	8003	1			T1	1		T2	2		T3	17
valid_sources[0x35]	8712	1			T1	1		T2	4		T3	16
valid_sources[0x36]	8437	1			T2	6		T3	11		T19	1
valid_sources[0x37]	7984	1			T1	1		T2	6		T3	12
valid_sources[0x38]	8359	1			T2	2		T3	10		T4	12
valid_sources[0x39]	7869	1			T2	1		T3	15		T4	28
valid_sources[0x3a]	8235	1			T2	1		T3	6		T4	73
valid_sources[0x3b]	7978	1			T2	6		T3	11		T16	90
valid_sources[0x3c]	7367	1			T2	3		T3	7		T4	2
valid_sources[0x3d]	8593	1			T2	8		T3	15		T4	16
valid_sources[0x3e]	9163	1			T2	5		T3	13		T4	22
valid_sources[0x3f]	7986	1			T1	1		T2	3		T3	15
valid_sources[0x40]	7405	1			T1	1		T2	3		T3	21
valid_sources[0x41]	8148	1			T2	3		T3	17		T4	34
valid_sources[0x42]	8703	1			T2	4		T3	6		T4	6
valid_sources[0x43]	8267	1			T2	2		T3	5		T4	17
valid_sources[0x44]	7798	1			T2	7		T3	7		T4	5
valid_sources[0x45]	9887	1			T1	1		T2	2		T3	16
valid_sources[0x46]	8058	1			T2	4		T3	23		T4	2
valid_sources[0x47]	7509	1			T2	4		T3	21		T4	6
valid_sources[0x48]	8284	1			T2	3		T3	14		T4	17
valid_sources[0x49]	8369	1			T1	1		T2	6		T3	20
valid_sources[0x4a]	7903	1			T2	4		T3	12		T4	23
valid_sources[0x4b]	8940	1			T1	2		T2	4		T3	17
valid_sources[0x4c]	7980	1			T1	2		T2	2		T3	7
valid_sources[0x4d]	7823	1			T1	1		T2	3		T3	2
valid_sources[0x4e]	7764	1			T1	1		T2	2		T3	19
valid_sources[0x4f]	7523	1			T1	1		T2	3		T3	15
valid_sources[0x50]	7763	1			T2	4		T3	7		T19	3
valid_sources[0x51]	7857	1			T2	3		T3	10		T4	4
valid_sources[0x52]	7881	1			T1	1		T2	2		T3	13
valid_sources[0x53]	7408	1			T2	4		T3	6		T4	22
valid_sources[0x54]	7690	1			T2	1		T3	16		T4	5
valid_sources[0x55]	8001	1			T3	12		T4	46		T18	8
valid_sources[0x56]	7977	1			T1	1		T2	4		T3	6
valid_sources[0x57]	7580	1			T1	1		T2	5		T3	20
valid_sources[0x58]	8277	1			T1	1		T2	1		T3	7
valid_sources[0x59]	8218	1			T1	1		T2	3		T3	6
valid_sources[0x5a]	7507	1			T2	2		T3	9		T18	6
valid_sources[0x5b]	8952	1			T1	1		T2	3		T3	20
valid_sources[0x5c]	7964	1			T2	2		T3	10		T4	24
valid_sources[0x5d]	8633	1			T2	3		T3	12		T4	25
valid_sources[0x5e]	7935	1			T1	1		T2	2		T3	6
valid_sources[0x5f]	8499	1			T2	6		T3	13		T4	9
valid_sources[0x60]	8296	1			T2	2		T3	11		T4	11
valid_sources[0x61]	7975	1			T2	1		T3	15		T4	8
valid_sources[0x62]	8074	1			T1	1		T2	4		T3	6
valid_sources[0x63]	8468	1			T2	10		T3	9		T4	6
valid_sources[0x64]	7599	1			T2	10		T3	13		T4	27
valid_sources[0x65]	8153	1			T1	1		T2	4		T3	11
valid_sources[0x66]	10589	1			T1	3		T2	9		T3	14
valid_sources[0x67]	7873	1			T2	4		T3	11		T4	5
valid_sources[0x68]	7603	1			T2	6		T3	8		T4	3
valid_sources[0x69]	7857	1			T2	4		T3	14		T4	2
valid_sources[0x6a]	8327	1			T1	1		T2	4		T3	6
valid_sources[0x6b]	8015	1			T2	2		T3	6		T20	9
valid_sources[0x6c]	8169	1			T1	1		T2	5		T3	11
valid_sources[0x6d]	8117	1			T2	6		T3	13		T4	12
valid_sources[0x6e]	10072	1			T2	3		T3	21		T4	9
valid_sources[0x6f]	7342	1			T2	6		T3	8		T16	4
valid_sources[0x70]	7847	1			T1	1		T2	10		T3	12
valid_sources[0x71]	7858	1			T1	1		T2	3		T3	3
valid_sources[0x72]	8112	1			T2	2		T3	2		T4	5
valid_sources[0x73]	7267	1			T1	1		T3	16		T4	11
valid_sources[0x74]	7658	1			T2	4		T3	11		T4	5
valid_sources[0x75]	8105	1			T2	4		T3	3		T4	4
valid_sources[0x76]	7604	1			T2	5		T3	9		T4	11
valid_sources[0x77]	8169	1			T2	5		T3	13		T17	1
valid_sources[0x78]	8136	1			T1	1		T2	8		T3	8
valid_sources[0x79]	7513	1			T2	2		T3	8		T4	16
valid_sources[0x7a]	7798	1			T1	1		T2	3		T3	9
valid_sources[0x7b]	8786	1			T2	9		T3	11		T4	12
valid_sources[0x7c]	8978	1			T2	6		T3	7		T4	9
valid_sources[0x7d]	8189	1			T2	1		T3	13		T4	1
valid_sources[0x7e]	8416	1			T2	5		T3	22		T4	7
valid_sources[0x7f]	8616	1			T2	3		T3	10		T4	18
valid_sources[0x80]	9565	1			T2	5		T3	6		T19	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29832

1

T2

29

T3

41

T4

30

values[0x0]

all_enables

biggest_size

224379

1

T1

10

T2

31

T3

334

values[0x1]

all_enables

biggest_size

29998

1

T1

1

T2

39

T3

34