Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	332764022	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	332764022	0	0
T1	8399376	221595	0	0
T2	25043032	527029	0	0
T3	3610376	82283	0	0
T4	3443216	73063	0	0
T16	3380720	76800	0	0
T17	239680	5267	0	0
T18	3219104	57231	0	0
T19	49887208	867228	0	0
T20	216104	7408	0	0
T21	14020216	1174003	0	0
T22	438668	82661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8710464	8707552	0	0
T2	25043032	24957912	0	0
T3	3610376	3606120	0	0
T4	3443216	3442152	0	0
T16	3380720	3377976	0	0
T17	239680	237608	0	0
T18	3219104	3215632	0	0
T19	49887208	49885696	0	0
T20	216104	214872	0	0
T21	14020216	14020048	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8710464	8707552	0	0
T2	25043032	24957912	0	0
T3	3610376	3606120	0	0
T4	3443216	3442152	0	0
T16	3380720	3377976	0	0
T17	239680	237608	0	0
T18	3219104	3215632	0	0
T19	49887208	49885696	0	0
T20	216104	214872	0	0
T21	14020216	14020048	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8710464	8707552	0	0
T2	25043032	24957912	0	0
T3	3610376	3606120	0	0
T4	3443216	3442152	0	0
T16	3380720	3377976	0	0
T17	239680	237608	0	0
T18	3219104	3215632	0	0
T19	49887208	49885696	0	0
T20	216104	214872	0	0
T21	14020216	14020048	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	127693990	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	127693990	0	0
T1	155544	91116	0	0
T2	447197	218041	0	0
T3	64471	32570	0	0
T4	61486	32481	0	0
T16	60370	30294	0	0
T17	4280	2057	0	0
T18	57484	55892	0	0
T19	890843	384736	0	0
T20	3859	1856	0	0
T21	250361	13368	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	83164176	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	83164176	0	0
T1	155544	41869	0	0
T2	447197	74499	0	0
T3	64471	26354	0	0
T4	61486	9724	0	0
T16	60370	24599	0	0
T17	4280	1045	0	0
T18	57484	418	0	0
T19	890843	104985	0	0
T20	3859	1856	0	0
T21	250361	104297	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1495579	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1495579	0	0
T2	447197	5326	0	0
T3	64471	432	0	0
T4	61486	635	0	0
T16	60370	382	0	0
T17	4280	12	0	0
T18	57484	24	0	0
T19	890843	12887	0	0
T20	3859	58	0	0
T21	250361	2056	0	0
T22	219334	1616	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3248298	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3248298	0	0
T2	447197	2440	0	0
T3	64471	422	0	0
T4	61486	311	0	0
T16	60370	397	0	0
T17	4280	31	0	0
T18	57484	7	0	0
T19	890843	3891	0	0
T20	3859	58	0	0
T21	250361	175753	0	0
T22	219334	1512	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1484750	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1484750	0	0
T1	155544	3152	0	0
T2	447197	4775	0	0
T3	64471	517	0	0
T4	61486	1077	0	0
T16	60370	273	0	0
T17	4280	38	0	0
T18	57484	13	0	0
T19	890843	14081	0	0
T20	3859	61	0	0
T21	250361	0	0	0
T22	0	1331	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2825687	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2825687	0	0
T1	155544	2626	0	0
T2	447197	2171	0	0
T3	64471	595	0	0
T4	61486	461	0	0
T16	60370	239	0	0
T17	4280	12	0	0
T18	57484	5	0	0
T19	890843	5674	0	0
T20	3859	61	0	0
T21	250361	0	0	0
T22	0	1357	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1515537	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1515537	0	0
T1	155544	2229	0	0
T2	447197	5245	0	0
T3	64471	337	0	0
T4	61486	649	0	0
T16	60370	333	0	0
T17	4280	26	0	0
T18	57484	10	0	0
T19	890843	9530	0	0
T20	3859	58	0	0
T21	250361	1208	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2889327	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2889327	0	0
T1	155544	1617	0	0
T2	447197	2608	0	0
T3	64471	372	0	0
T4	61486	269	0	0
T16	60370	307	0	0
T17	4280	46	0	0
T18	57484	4	0	0
T19	890843	4127	0	0
T20	3859	58	0	0
T21	250361	89341	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1449331	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1449331	0	0
T1	155544	2183	0	0
T2	447197	6439	0	0
T3	64471	388	0	0
T4	61486	705	0	0
T16	60370	422	0	0
T17	4280	41	0	0
T18	57484	14	0	0
T19	890843	9401	0	0
T20	3859	76	0	0
T21	250361	1208	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3137849	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3137849	0	0
T1	155544	2729	0	0
T2	447197	2864	0	0
T3	64471	464	0	0
T4	61486	361	0	0
T16	60370	441	0	0
T17	4280	29	0	0
T18	57484	3	0	0
T19	890843	4774	0	0
T20	3859	76	0	0
T21	250361	89740	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1494110	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1494110	0	0
T1	155544	1322	0	0
T2	447197	10588	0	0
T3	64471	362	0	0
T4	61486	741	0	0
T16	60370	414	0	0
T17	4280	49	0	0
T18	57484	23	0	0
T19	890843	7257	0	0
T20	3859	75	0	0
T21	250361	0	0	0
T22	0	3683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3774384	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3774384	0	0
T1	155544	1371	0	0
T2	447197	4661	0	0
T3	64471	435	0	0
T4	61486	398	0	0
T16	60370	389	0	0
T17	4280	36	0	0
T18	57484	4	0	0
T19	890843	3986	0	0
T20	3859	75	0	0
T21	250361	0	0	0
T22	0	3584	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1497400	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1497400	0	0
T1	155544	952	0	0
T2	447197	3899	0	0
T3	64471	370	0	0
T4	61486	698	0	0
T16	60370	475	0	0
T17	4280	30	0	0
T18	57484	25	0	0
T19	890843	12078	0	0
T20	3859	77	0	0
T21	250361	0	0	0
T22	0	1498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3163910	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3163910	0	0
T1	155544	1812	0	0
T2	447197	2028	0	0
T3	64471	432	0	0
T4	61486	323	0	0
T16	60370	527	0	0
T17	4280	15	0	0
T18	57484	9	0	0
T19	890843	3520	0	0
T20	3859	77	0	0
T21	250361	0	0	0
T22	0	1460	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1440633	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1440633	0	0
T1	155544	1251	0	0
T2	447197	2525	0	0
T3	64471	462	0	0
T4	61486	780	0	0
T16	60370	285	0	0
T17	4280	61	0	0
T18	57484	33	0	0
T19	890843	11731	0	0
T20	3859	64	0	0
T21	250361	0	0	0
T22	0	1319	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3256709	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3256709	0	0
T1	155544	456	0	0
T2	447197	1081	0	0
T3	64471	408	0	0
T4	61486	381	0	0
T16	60370	335	0	0
T17	4280	49	0	0
T18	57484	5	0	0
T19	890843	5289	0	0
T20	3859	64	0	0
T21	250361	0	0	0
T22	0	1264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1449449	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1449449	0	0
T1	155544	1580	0	0
T2	447197	14424	0	0
T3	64471	396	0	0
T4	61486	906	0	0
T16	60370	417	0	0
T17	4280	26	0	0
T18	57484	28	0	0
T19	890843	14509	0	0
T20	3859	67	0	0
T21	250361	0	0	0
T22	0	2300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2684151	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2684151	0	0
T1	155544	1442	0	0
T2	447197	6669	0	0
T3	64471	408	0	0
T4	61486	277	0	0
T16	60370	390	0	0
T17	4280	19	0	0
T18	57484	304	0	0
T19	890843	7229	0	0
T20	3859	67	0	0
T21	250361	0	0	0
T22	0	2308	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1439363	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1439363	0	0
T1	155544	4214	0	0
T2	447197	3757	0	0
T3	64471	404	0	0
T4	61486	764	0	0
T16	60370	456	0	0
T17	4280	36	0	0
T18	57484	11	0	0
T19	890843	9733	0	0
T20	3859	72	0	0
T21	250361	0	0	0
T22	0	1660	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3246108	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3246108	0	0
T1	155544	3930	0	0
T2	447197	1697	0	0
T3	64471	377	0	0
T4	61486	386	0	0
T16	60370	546	0	0
T17	4280	26	0	0
T18	57484	4	0	0
T19	890843	3591	0	0
T20	3859	72	0	0
T21	250361	0	0	0
T22	0	1606	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1502698	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1502698	0	0
T1	155544	2916	0	0
T2	447197	4949	0	0
T3	64471	326	0	0
T4	61486	803	0	0
T16	60370	402	0	0
T17	4280	27	0	0
T18	57484	4	0	0
T19	890843	8607	0	0
T20	3859	63	0	0
T21	250361	0	0	0
T22	0	1308	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3112567	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3112567	0	0
T1	155544	3195	0	0
T2	447197	2269	0	0
T3	64471	418	0	0
T4	61486	365	0	0
T16	60370	447	0	0
T17	4280	7	0	0
T18	57484	2	0	0
T19	890843	3789	0	0
T20	3859	63	0	0
T21	250361	0	0	0
T22	0	1293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1484117	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1484117	0	0
T1	155544	1014	0	0
T2	447197	2562	0	0
T3	64471	446	0	0
T4	61486	733	0	0
T16	60370	333	0	0
T17	4280	21	0	0
T18	57484	21	0	0
T19	890843	11016	0	0
T20	3859	61	0	0
T21	250361	0	0	0
T22	0	1778	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3496611	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3496611	0	0
T1	155544	217	0	0
T2	447197	1151	0	0
T3	64471	547	0	0
T4	61486	355	0	0
T16	60370	326	0	0
T17	4280	29	0	0
T18	57484	3	0	0
T19	890843	5256	0	0
T20	3859	61	0	0
T21	250361	0	0	0
T22	0	1778	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1470001	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1470001	0	0
T1	155544	2137	0	0
T2	447197	2356	0	0
T3	64471	487	0	0
T4	61486	826	0	0
T16	60370	412	0	0
T17	4280	11	0	0
T18	57484	29	0	0
T19	890843	7288	0	0
T20	3859	64	0	0
T21	250361	0	0	0
T22	0	1550	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3537344	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3537344	0	0
T1	155544	2413	0	0
T2	447197	1121	0	0
T3	64471	520	0	0
T4	61486	397	0	0
T16	60370	401	0	0
T17	4280	35	0	0
T18	57484	6	0	0
T19	890843	3180	0	0
T20	3859	64	0	0
T21	250361	0	0	0
T22	0	1412	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1479036	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1479036	0	0
T1	155544	2823	0	0
T2	447197	2450	0	0
T3	64471	449	0	0
T4	61486	852	0	0
T16	60370	428	0	0
T17	4280	36	0	0
T18	57484	41	0	0
T19	890843	7170	0	0
T20	3859	78	0	0
T21	250361	2323	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2965766	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2965766	0	0
T1	155544	2431	0	0
T2	447197	983	0	0
T3	64471	508	0	0
T4	61486	423	0	0
T16	60370	515	0	0
T17	4280	30	0	0
T18	57484	8	0	0
T19	890843	3130	0	0
T20	3859	78	0	0
T21	250361	186652	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1485247	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1485247	0	0
T1	155544	2130	0	0
T2	447197	8614	0	0
T3	64471	390	0	0
T4	61486	796	0	0
T16	60370	295	0	0
T17	4280	48	0	0
T18	57484	11	0	0
T19	890843	8921	0	0
T20	3859	79	0	0
T21	250361	0	0	0
T22	0	2812	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3014648	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3014648	0	0
T1	155544	1367	0	0
T2	447197	3692	0	0
T3	64471	411	0	0
T4	61486	378	0	0
T16	60370	429	0	0
T17	4280	40	0	0
T18	57484	3	0	0
T19	890843	4183	0	0
T20	3859	79	0	0
T21	250361	0	0	0
T22	0	2859	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1482254	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1482254	0	0
T1	155544	465	0	0
T2	447197	8485	0	0
T3	64471	407	0	0
T4	61486	715	0	0
T16	60370	354	0	0
T17	4280	10	0	0
T18	57484	25	0	0
T19	890843	10729	0	0
T20	3859	68	0	0
T21	250361	0	0	0
T22	0	1269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3165521	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3165521	0	0
T1	155544	305	0	0
T2	447197	4220	0	0
T3	64471	443	0	0
T4	61486	317	0	0
T16	60370	288	0	0
T17	4280	10	0	0
T18	57484	4	0	0
T19	890843	3428	0	0
T20	3859	68	0	0
T21	250361	0	0	0
T22	0	1401	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1505370	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1505370	0	0
T1	155544	1406	0	0
T2	447197	2517	0	0
T3	64471	443	0	0
T4	61486	568	0	0
T16	60370	461	0	0
T17	4280	66	0	0
T18	57484	7	0	0
T19	890843	10309	0	0
T20	3859	67	0	0
T21	250361	2074	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2814300	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2814300	0	0
T1	155544	1596	0	0
T2	447197	1105	0	0
T3	64471	455	0	0
T4	61486	307	0	0
T16	60370	389	0	0
T17	4280	34	0	0
T18	57484	2	0	0
T19	890843	4146	0	0
T20	3859	67	0	0
T21	250361	162863	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1473194	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1473194	0	0
T1	155544	1325	0	0
T2	447197	6731	0	0
T3	64471	368	0	0
T4	61486	978	0	0
T16	60370	393	0	0
T17	4280	18	0	0
T18	57484	9	0	0
T19	890843	9705	0	0
T20	3859	68	0	0
T21	250361	1229	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2473684	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2473684	0	0
T1	155544	930	0	0
T2	447197	2831	0	0
T3	64471	340	0	0
T4	61486	415	0	0
T16	60370	333	0	0
T17	4280	26	0	0
T18	57484	3	0	0
T19	890843	2283	0	0
T20	3859	68	0	0
T21	250361	87151	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1467504	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1467504	0	0
T1	155544	2850	0	0
T2	447197	10166	0	0
T3	64471	371	0	0
T4	61486	645	0	0
T16	60370	371	0	0
T17	4280	30	0	0
T18	57484	6	0	0
T19	890843	9352	0	0
T20	3859	72	0	0
T21	250361	892	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3388878	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3388878	0	0
T1	155544	1591	0	0
T2	447197	4798	0	0
T3	64471	396	0	0
T4	61486	300	0	0
T16	60370	353	0	0
T17	4280	41	0	0
T18	57484	2	0	0
T19	890843	1722	0	0
T20	3859	72	0	0
T21	250361	67091	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1468961	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1468961	0	0
T1	155544	1430	0	0
T2	447197	4317	0	0
T3	64471	588	0	0
T4	61486	896	0	0
T16	60370	432	0	0
T17	4280	42	0	0
T18	57484	24	0	0
T19	890843	7112	0	0
T20	3859	70	0	0
T21	250361	0	0	0
T22	0	6629	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2125284	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2125284	0	0
T1	155544	1865	0	0
T2	447197	2054	0	0
T3	64471	650	0	0
T4	61486	362	0	0
T16	60370	365	0	0
T17	4280	56	0	0
T18	57484	4	0	0
T19	890843	4648	0	0
T20	3859	70	0	0
T21	250361	0	0	0
T22	0	6824	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1481456	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1481456	0	0
T1	155544	3937	0	0
T2	447197	6312	0	0
T3	64471	438	0	0
T4	61486	800	0	0
T16	60370	373	0	0
T17	4280	59	0	0
T18	57484	25	0	0
T19	890843	11595	0	0
T20	3859	76	0	0
T21	250361	0	0	0
T22	0	1288	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2487741	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2487741	0	0
T1	155544	3389	0	0
T2	447197	2564	0	0
T3	64471	434	0	0
T4	61486	310	0	0
T16	60370	462	0	0
T17	4280	75	0	0
T18	57484	8	0	0
T19	890843	3192	0	0
T20	3859	76	0	0
T21	250361	0	0	0
T22	0	1453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1450257	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1450257	0	0
T1	155544	424	0	0
T2	447197	8772	0	0
T3	64471	372	0	0
T4	61486	742	0	0
T16	60370	464	0	0
T17	4280	77	0	0
T18	57484	1	0	0
T19	890843	7077	0	0
T20	3859	82	0	0
T21	250361	0	0	0
T22	0	1411	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3057123	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3057123	0	0
T1	155544	108	0	0
T2	447197	4189	0	0
T3	64471	411	0	0
T4	61486	394	0	0
T16	60370	396	0	0
T17	4280	57	0	0
T18	57484	1	0	0
T19	890843	2801	0	0
T20	3859	82	0	0
T21	250361	0	0	0
T22	0	1403	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1409080	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1409080	0	0
T1	155544	2206	0	0
T2	447197	4282	0	0
T3	64471	462	0	0
T4	61486	837	0	0
T16	60370	442	0	0
T17	4280	60	0	0
T18	57484	29	0	0
T19	890843	12248	0	0
T20	3859	64	0	0
T21	250361	0	0	0
T22	0	2491	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2615031	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2615031	0	0
T1	155544	563	0	0
T2	447197	1836	0	0
T3	64471	378	0	0
T4	61486	393	0	0
T16	60370	453	0	0
T17	4280	59	0	0
T18	57484	5	0	0
T19	890843	2837	0	0
T20	3859	64	0	0
T21	250361	0	0	0
T22	0	2504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1421992	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1421992	0	0
T1	155544	171	0	0
T2	447197	6035	0	0
T3	64471	389	0	0
T4	61486	717	0	0
T16	60370	343	0	0
T17	4280	57	0	0
T18	57484	13	0	0
T19	890843	9092	0	0
T20	3859	67	0	0
T21	250361	0	0	0
T22	0	1518	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3250482	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3250482	0	0
T1	155544	1865	0	0
T2	447197	2705	0	0
T3	64471	493	0	0
T4	61486	370	0	0
T16	60370	349	0	0
T17	4280	44	0	0
T18	57484	4	0	0
T19	890843	4084	0	0
T20	3859	67	0	0
T21	250361	0	0	0
T22	0	1578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1510830	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1510830	0	0
T1	155544	1625	0	0
T2	447197	5325	0	0
T3	64471	397	0	0
T4	61486	833	0	0
T16	60370	489	0	0
T17	4280	49	0	0
T18	57484	8	0	0
T19	890843	8864	0	0
T20	3859	76	0	0
T21	250361	0	0	0
T22	0	2901	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2988804	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2988804	0	0
T1	155544	1109	0	0
T2	447197	3185	0	0
T3	64471	463	0	0
T4	61486	362	0	0
T16	60370	365	0	0
T17	4280	53	0	0
T18	57484	2	0	0
T19	890843	3389	0	0
T20	3859	76	0	0
T21	250361	0	0	0
T22	0	2914	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1474442	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1474442	0	0
T1	155544	1153	0	0
T2	447197	7218	0	0
T3	64471	389	0	0
T4	61486	909	0	0
T16	60370	548	0	0
T17	4280	22	0	0
T18	57484	23	0	0
T19	890843	13487	0	0
T20	3859	58	0	0
T21	250361	2376	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3231274	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3231274	0	0
T1	155544	1273	0	0
T2	447197	3383	0	0
T3	64471	451	0	0
T4	61486	365	0	0
T16	60370	599	0	0
T17	4280	22	0	0
T18	57484	5	0	0
T19	890843	3767	0	0
T20	3859	58	0	0
T21	250361	184381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1440738	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1440738	0	0
T1	155544	737	0	0
T2	447197	7829	0	0
T3	64471	574	0	0
T4	61486	844	0	0
T16	60370	421	0	0
T17	4280	105	0	0
T18	57484	16	0	0
T19	890843	11795	0	0
T20	3859	67	0	0
T21	250361	0	0	0
T22	0	1496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	3247021	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	3247021	0	0
T1	155544	972	0	0
T2	447197	3803	0	0
T3	64471	424	0	0
T4	61486	432	0	0
T16	60370	483	0	0
T17	4280	104	0	0
T18	57484	5	0	0
T19	890843	3906	0	0
T20	3859	67	0	0
T21	250361	0	0	0
T22	0	1536	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	1478729	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	1478729	0	0
T1	155544	1109	0	0
T2	447197	4599	0	0
T3	64471	329	0	0
T4	61486	686	0	0
T16	60370	493	0	0
T17	4280	63	0	0
T18	57484	30	0	0
T19	890843	6948	0	0
T20	3859	60	0	0
T21	250361	0	0	0
T22	0	1376	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301170404	2955296	0	0
DepthKnown_A	301170404	301050117	0	0
RvalidKnown_A	301170404	301050117	0	0
WreadyKnown_A	301170404	301050117	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	2955296	0	0
T1	155544	697	0	0
T2	447197	1884	0	0
T3	64471	411	0	0
T4	61486	311	0	0
T16	60370	472	0	0
T17	4280	60	0	0
T18	57484	6	0	0
T19	890843	3163	0	0
T20	3859	60	0	0
T21	250361	0	0	0
T22	0	1381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301170404	301050117	0	0
T1	155544	155492	0	0
T2	447197	445677	0	0
T3	64471	64395	0	0
T4	61486	61467	0	0
T16	60370	60321	0	0
T17	4280	4243	0	0
T18	57484	57422	0	0
T19	890843	890816	0	0
T20	3859	3837	0	0
T21	250361	250358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0