Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1855740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

292782

1

T1

489

T2

152

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	724571	1			T1	1173		T2	390		T3	48
values[0x0]	698475	1			T1	1196		T2	375		T3	53
values[0x1]	725476	1			T1	1190		T2	350		T3	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1438100	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

710422

1

T1

1168

T2

356

T3

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7437	1			T1	14		T2	6		T3	7
valid_sources[0x01]	8093	1			T1	15		T4	1		T17	8
valid_sources[0x02]	9171	1			T1	12		T2	1		T3	1
valid_sources[0x03]	8949	1			T1	11		T2	3		T4	1
valid_sources[0x04]	8296	1			T1	15		T2	1		T17	8
valid_sources[0x05]	7946	1			T1	15		T2	4		T4	2
valid_sources[0x06]	8055	1			T1	16		T2	4		T17	9
valid_sources[0x07]	8225	1			T1	13		T2	7		T3	1
valid_sources[0x08]	7362	1			T1	15		T17	9		T14	11
valid_sources[0x09]	7732	1			T1	12		T2	3		T17	9
valid_sources[0x0a]	9245	1			T1	14		T2	9		T17	8
valid_sources[0x0b]	8285	1			T1	13		T17	9		T16	62
valid_sources[0x0c]	9075	1			T1	14		T2	12		T17	9
valid_sources[0x0d]	9009	1			T1	13		T2	9		T4	1
valid_sources[0x0e]	7715	1			T1	12		T2	3		T3	1
valid_sources[0x0f]	7722	1			T1	14		T17	9		T14	3
valid_sources[0x10]	8814	1			T1	14		T2	7		T3	1
valid_sources[0x11]	7170	1			T1	14		T2	4		T17	9
valid_sources[0x12]	8431	1			T1	16		T2	3		T3	1
valid_sources[0x13]	9380	1			T1	15		T2	12		T3	2
valid_sources[0x14]	7944	1			T1	15		T2	6		T17	9
valid_sources[0x15]	8520	1			T1	14		T2	3		T17	9
valid_sources[0x16]	7992	1			T1	16		T4	1		T17	9
valid_sources[0x17]	8228	1			T1	14		T2	2		T3	3
valid_sources[0x18]	8088	1			T1	14		T2	1		T4	1
valid_sources[0x19]	8202	1			T1	13		T2	5		T17	9
valid_sources[0x1a]	7526	1			T1	13		T2	14		T17	9
valid_sources[0x1b]	7979	1			T1	14		T2	9		T3	1
valid_sources[0x1c]	7691	1			T1	13		T2	1		T3	1
valid_sources[0x1d]	8326	1			T1	13		T2	2		T17	8
valid_sources[0x1e]	8046	1			T1	12		T2	2		T17	8
valid_sources[0x1f]	7740	1			T1	15		T2	5		T4	2
valid_sources[0x20]	7942	1			T1	14		T2	3		T4	1
valid_sources[0x21]	8457	1			T1	13		T2	1		T17	9
valid_sources[0x22]	7986	1			T1	14		T2	4		T17	9
valid_sources[0x23]	8259	1			T1	12		T2	9		T17	8
valid_sources[0x24]	8354	1			T1	14		T2	4		T3	2
valid_sources[0x25]	7851	1			T1	14		T2	4		T17	8
valid_sources[0x26]	8066	1			T1	15		T2	7		T4	1
valid_sources[0x27]	8010	1			T1	14		T2	3		T17	7
valid_sources[0x28]	10876	1			T1	14		T2	2		T4	3
valid_sources[0x29]	8631	1			T1	15		T17	7		T14	1
valid_sources[0x2a]	7677	1			T1	13		T2	9		T17	7
valid_sources[0x2b]	8360	1			T1	13		T2	3		T17	8
valid_sources[0x2c]	7823	1			T1	12		T2	2		T17	8
valid_sources[0x2d]	9082	1			T1	12		T2	5		T3	1
valid_sources[0x2e]	7628	1			T1	12		T4	1		T17	8
valid_sources[0x2f]	7994	1			T1	13		T2	10		T4	1
valid_sources[0x30]	8257	1			T1	15		T2	3		T3	1
valid_sources[0x31]	9568	1			T1	14		T17	11		T16	3
valid_sources[0x32]	9422	1			T1	14		T2	3		T17	9
valid_sources[0x33]	8209	1			T1	12		T2	5		T17	9
valid_sources[0x34]	8151	1			T1	13		T2	13		T17	9
valid_sources[0x35]	8397	1			T1	15		T2	2		T3	4
valid_sources[0x36]	9415	1			T1	12		T2	8		T17	9
valid_sources[0x37]	9172	1			T1	13		T2	2		T3	1
valid_sources[0x38]	10130	1			T1	14		T2	3		T17	7
valid_sources[0x39]	8044	1			T1	13		T2	2		T3	1
valid_sources[0x3a]	9537	1			T1	14		T2	2		T17	10
valid_sources[0x3b]	7902	1			T1	13		T2	2		T3	1
valid_sources[0x3c]	8597	1			T1	12		T2	2		T3	2
valid_sources[0x3d]	8085	1			T1	11		T2	16		T17	9
valid_sources[0x3e]	7516	1			T1	14		T2	4		T4	3
valid_sources[0x3f]	9987	1			T1	13		T2	3		T17	8
valid_sources[0x40]	8179	1			T1	12		T2	10		T17	8
valid_sources[0x41]	8910	1			T1	14		T2	7		T4	1
valid_sources[0x42]	8990	1			T1	17		T17	10		T14	4
valid_sources[0x43]	8769	1			T1	14		T17	10		T14	4
valid_sources[0x44]	8159	1			T1	15		T2	4		T4	1
valid_sources[0x45]	8466	1			T1	12		T2	1		T17	9
valid_sources[0x46]	7786	1			T1	13		T2	3		T17	8
valid_sources[0x47]	9694	1			T1	13		T2	5		T3	1
valid_sources[0x48]	8263	1			T1	14		T2	1		T17	7
valid_sources[0x49]	7283	1			T1	13		T2	6		T4	1
valid_sources[0x4a]	9348	1			T1	13		T17	8		T14	5
valid_sources[0x4b]	8735	1			T1	14		T2	19		T3	1
valid_sources[0x4c]	8653	1			T1	15		T2	2		T17	9
valid_sources[0x4d]	8185	1			T1	12		T2	13		T3	1
valid_sources[0x4e]	8272	1			T1	15		T2	2		T17	8
valid_sources[0x4f]	8756	1			T1	13		T2	5		T3	3
valid_sources[0x50]	8423	1			T1	14		T2	5		T4	2
valid_sources[0x51]	8079	1			T1	16		T2	9		T17	9
valid_sources[0x52]	9499	1			T1	15		T17	8		T14	2
valid_sources[0x53]	10447	1			T1	12		T2	8		T4	4
valid_sources[0x54]	7740	1			T1	13		T2	6		T3	1
valid_sources[0x55]	7982	1			T1	14		T2	5		T4	1
valid_sources[0x56]	8187	1			T1	15		T4	3		T17	9
valid_sources[0x57]	8833	1			T1	15		T2	2		T4	2
valid_sources[0x58]	8101	1			T1	14		T2	1		T17	9
valid_sources[0x59]	7675	1			T1	13		T2	3		T17	7
valid_sources[0x5a]	9420	1			T1	14		T2	8		T17	8
valid_sources[0x5b]	7823	1			T1	14		T2	10		T17	7
valid_sources[0x5c]	9262	1			T1	14		T2	1		T17	10
valid_sources[0x5d]	7765	1			T1	15		T2	5		T17	9
valid_sources[0x5e]	7521	1			T1	11		T2	3		T4	2
valid_sources[0x5f]	9340	1			T1	12		T2	4		T3	2
valid_sources[0x60]	7724	1			T1	13		T2	22		T17	9
valid_sources[0x61]	7673	1			T1	12		T2	3		T3	3
valid_sources[0x62]	8376	1			T1	16		T2	1		T17	9
valid_sources[0x63]	9457	1			T1	15		T2	2		T17	10
valid_sources[0x64]	8993	1			T1	15		T2	1		T17	8
valid_sources[0x65]	7906	1			T1	13		T2	2		T3	1
valid_sources[0x66]	7843	1			T1	13		T2	3		T17	5
valid_sources[0x67]	7876	1			T1	15		T2	4		T3	2
valid_sources[0x68]	7805	1			T1	13		T2	3		T3	1
valid_sources[0x69]	7282	1			T1	14		T2	5		T17	8
valid_sources[0x6a]	8116	1			T1	13		T2	7		T4	1
valid_sources[0x6b]	8765	1			T1	15		T2	4		T4	2
valid_sources[0x6c]	8742	1			T1	15		T2	1		T3	2
valid_sources[0x6d]	7258	1			T1	14		T2	6		T4	1
valid_sources[0x6e]	8598	1			T1	17		T3	2		T17	8
valid_sources[0x6f]	8579	1			T1	14		T2	1		T4	1
valid_sources[0x70]	8503	1			T1	13		T2	2		T17	9
valid_sources[0x71]	8105	1			T1	15		T2	10		T3	1
valid_sources[0x72]	7811	1			T1	13		T2	13		T3	4
valid_sources[0x73]	10337	1			T1	13		T2	3		T17	8
valid_sources[0x74]	8448	1			T1	14		T2	1		T17	9
valid_sources[0x75]	7795	1			T1	12		T2	2		T3	6
valid_sources[0x76]	8724	1			T1	14		T2	3		T4	1
valid_sources[0x77]	7524	1			T1	13		T2	4		T3	3
valid_sources[0x78]	8883	1			T1	14		T2	6		T17	9
valid_sources[0x79]	8312	1			T1	14		T2	2		T17	9
valid_sources[0x7a]	8013	1			T1	14		T17	9		T14	2
valid_sources[0x7b]	9573	1			T1	14		T3	1		T17	10
valid_sources[0x7c]	8628	1			T1	14		T2	4		T4	1
valid_sources[0x7d]	8217	1			T1	14		T2	2		T3	2
valid_sources[0x7e]	7924	1			T1	14		T2	5		T4	1
valid_sources[0x7f]	7581	1			T1	16		T2	1		T17	9
valid_sources[0x80]	8568	1			T1	13		T2	3		T17	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30518

1

T1

46

T2

11

T4

6

values[0x0]

all_enables

biggest_size

231826

1

T1

387

T2

127

T3

14

values[0x1]

all_enables

biggest_size

30438

1

T1

56

T2

14

T3

2