Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	329639822	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	329639822	0	0
T1	8326296	1484142	0	0
T2	8764616	1872276	0	0
T3	46424	753	0	0
T4	299712	12568	0	0
T14	30336656	749069	0	0
T15	163352	3108	0	0
T16	2455936	51135	0	0
T17	10694264	1597566	0	0
T18	31528	613	0	0
T19	258496	4624	0	0
T20	150176	4228	0	0
T21	0	178	0	0
T22	0	1266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	19428024	19427800	0	0
T2	8764616	8764504	0	0
T3	46424	41776	0	0
T4	299712	295736	0	0
T14	30336656	30333576	0	0
T15	163352	159264	0	0
T16	2455936	2450560	0	0
T17	10694264	10693872	0	0
T18	31528	29344	0	0
T19	258496	257600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	19428024	19427800	0	0
T2	8764616	8764504	0	0
T3	46424	41776	0	0
T4	299712	295736	0	0
T14	30336656	30333576	0	0
T15	163352	159264	0	0
T16	2455936	2450560	0	0
T17	10694264	10693872	0	0
T18	31528	29344	0	0
T19	258496	257600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	19428024	19427800	0	0
T2	8764616	8764504	0	0
T3	46424	41776	0	0
T4	299712	295736	0	0
T14	30336656	30333576	0	0
T15	163352	159264	0	0
T16	2455936	2450560	0	0
T17	10694264	10693872	0	0
T18	31528	29344	0	0
T19	258496	257600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	123248662	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	123248662	0	0
T1	346929	16500	0	0
T2	156511	742809	0	0
T3	829	294	0	0
T4	5352	4897	0	0
T14	541726	307542	0	0
T15	2917	1197	0	0
T16	43856	19342	0	0
T17	190969	10178	0	0
T18	563	238	0	0
T19	4616	1997	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	83256644	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	83256644	0	0
T1	346929	131922	0	0
T2	156511	372698	0	0
T3	829	153	0	0
T4	5352	2559	0	0
T14	541726	145741	0	0
T15	2917	851	0	0
T16	43856	16383	0	0
T17	190969	788606	0	0
T18	563	125	0	0
T19	4616	640	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1491377	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1491377	0	0
T1	346929	1396	0	0
T2	156511	16373	0	0
T3	829	6	0	0
T4	5352	97	0	0
T14	541726	7600	0	0
T15	2917	0	0	0
T16	43856	378	0	0
T17	190969	0	0	0
T18	563	6	0	0
T19	4616	50	0	0
T20	0	81	0	0
T21	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	2038712	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	2038712	0	0
T1	346929	114235	0	0
T2	156511	13778	0	0
T3	829	6	0	0
T4	5352	97	0	0
T14	541726	6659	0	0
T15	2917	0	0	0
T16	43856	392	0	0
T17	190969	0	0	0
T18	563	6	0	0
T19	4616	20	0	0
T20	0	81	0	0
T21	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1544936	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1544936	0	0
T1	346929	2261	0	0
T2	156511	16132	0	0
T3	829	4	0	0
T4	5352	109	0	0
T14	541726	5983	0	0
T15	2917	27	0	0
T16	43856	317	0	0
T17	190969	0	0	0
T18	563	3	0	0
T19	4616	28	0	0
T20	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3022616	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3022616	0	0
T1	346929	181147	0	0
T2	156511	14330	0	0
T3	829	4	0	0
T4	5352	109	0	0
T14	541726	4633	0	0
T15	2917	29	0	0
T16	43856	271	0	0
T17	190969	0	0	0
T18	563	3	0	0
T19	4616	8	0	0
T20	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1511405	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1511405	0	0
T2	156511	14988	0	0
T3	829	5	0	0
T4	5352	85	0	0
T14	541726	9873	0	0
T15	2917	8	0	0
T16	43856	373	0	0
T17	190969	1195	0	0
T18	563	8	0	0
T19	4616	15	0	0
T20	4693	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	4020508	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	4020508	0	0
T2	156511	14868	0	0
T3	829	5	0	0
T4	5352	85	0	0
T14	541726	8306	0	0
T15	2917	18	0	0
T16	43856	416	0	0
T17	190969	97921	0	0
T18	563	8	0	0
T19	4616	13	0	0
T20	4693	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1529723	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1529723	0	0
T2	156511	13867	0	0
T3	829	8	0	0
T4	5352	78	0	0
T14	541726	6811	0	0
T15	2917	11	0	0
T16	43856	313	0	0
T17	190969	0	0	0
T18	563	5	0	0
T19	4616	9	0	0
T20	4693	95	0	0
T21	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	2763200	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	2763200	0	0
T2	156511	16698	0	0
T3	829	8	0	0
T4	5352	78	0	0
T14	541726	6044	0	0
T15	2917	17	0	0
T16	43856	222	0	0
T17	190969	0	0	0
T18	563	5	0	0
T19	4616	4	0	0
T20	4693	95	0	0
T21	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1514253	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1514253	0	0
T2	156511	11465	0	0
T3	829	2	0	0
T4	5352	104	0	0
T14	541726	7151	0	0
T15	2917	9	0	0
T16	43856	353	0	0
T17	190969	1023	0	0
T18	563	2	0	0
T19	4616	46	0	0
T20	4693	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3289107	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3289107	0	0
T2	156511	10860	0	0
T3	829	2	0	0
T4	5352	104	0	0
T14	541726	6397	0	0
T15	2917	4	0	0
T16	43856	335	0	0
T17	190969	74929	0	0
T18	563	2	0	0
T19	4616	28	0	0
T20	4693	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1541757	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1541757	0	0
T2	156511	11545	0	0
T3	829	2	0	0
T4	5352	106	0	0
T14	541726	5217	0	0
T15	2917	84	0	0
T16	43856	290	0	0
T17	190969	0	0	0
T18	563	2	0	0
T19	4616	111	0	0
T20	4693	80	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3085639	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3085639	0	0
T2	156511	11972	0	0
T3	829	2	0	0
T4	5352	106	0	0
T14	541726	4299	0	0
T15	2917	84	0	0
T16	43856	277	0	0
T17	190969	0	0	0
T18	563	2	0	0
T19	4616	56	0	0
T20	4693	80	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1546055	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1546055	0	0
T2	156511	12946	0	0
T3	829	4	0	0
T4	5352	79	0	0
T14	541726	3711	0	0
T15	2917	35	0	0
T16	43856	216	0	0
T17	190969	0	0	0
T18	563	7	0	0
T19	4616	77	0	0
T20	4693	84	0	0
T21	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3366554	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3366554	0	0
T2	156511	13619	0	0
T3	829	4	0	0
T4	5352	79	0	0
T14	541726	3382	0	0
T15	2917	17	0	0
T16	43856	249	0	0
T17	190969	0	0	0
T18	563	7	0	0
T19	4616	45	0	0
T20	4693	84	0	0
T21	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1509152	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1509152	0	0
T2	156511	13079	0	0
T3	829	6	0	0
T4	5352	99	0	0
T14	541726	5880	0	0
T15	2917	29	0	0
T16	43856	145	0	0
T17	190969	0	0	0
T18	563	6	0	0
T19	4616	49	0	0
T20	4693	79	0	0
T21	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3048574	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3048574	0	0
T2	156511	14083	0	0
T3	829	6	0	0
T4	5352	99	0	0
T14	541726	5063	0	0
T15	2917	21	0	0
T16	43856	217	0	0
T17	190969	0	0	0
T18	563	6	0	0
T19	4616	40	0	0
T20	4693	79	0	0
T21	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1553281	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1553281	0	0
T2	156511	13611	0	0
T3	829	9	0	0
T4	5352	90	0	0
T14	541726	5478	0	0
T15	2917	45	0	0
T16	43856	234	0	0
T17	190969	0	0	0
T18	563	2	0	0
T19	4616	97	0	0
T20	4693	100	0	0
T21	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3073115	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3073115	0	0
T2	156511	15008	0	0
T3	829	9	0	0
T4	5352	90	0	0
T14	541726	4640	0	0
T15	2917	34	0	0
T16	43856	291	0	0
T17	190969	0	0	0
T18	563	2	0	0
T19	4616	14	0	0
T20	4693	100	0	0
T21	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1487651	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1487651	0	0
T2	156511	14230	0	0
T3	829	5	0	0
T4	5352	106	0	0
T14	541726	7313	0	0
T15	2917	10	0	0
T16	43856	291	0	0
T17	190969	0	0	0
T18	563	6	0	0
T19	4616	44	0	0
T20	4693	85	0	0
T21	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	2641948	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	2641948	0	0
T2	156511	13124	0	0
T3	829	5	0	0
T4	5352	106	0	0
T14	541726	6100	0	0
T15	2917	11	0	0
T16	43856	223	0	0
T17	190969	0	0	0
T18	563	6	0	0
T19	4616	15	0	0
T20	4693	85	0	0
T21	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1511306	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1511306	0	0
T2	156511	16612	0	0
T3	829	10	0	0
T4	5352	97	0	0
T14	541726	5164	0	0
T15	2917	15	0	0
T16	43856	277	0	0
T17	190969	1315	0	0
T18	563	3	0	0
T19	4616	38	0	0
T20	4693	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3218888	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3218888	0	0
T2	156511	12706	0	0
T3	829	10	0	0
T4	5352	97	0	0
T14	541726	4257	0	0
T15	2917	22	0	0
T16	43856	259	0	0
T17	190969	96144	0	0
T18	563	3	0	0
T19	4616	10	0	0
T20	4693	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1510103	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1510103	0	0
T2	156511	13028	0	0
T3	829	5	0	0
T4	5352	116	0	0
T14	541726	3525	0	0
T15	2917	22	0	0
T16	43856	256	0	0
T17	190969	0	0	0
T18	563	5	0	0
T19	4616	25	0	0
T20	4693	84	0	0
T21	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	2222786	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	2222786	0	0
T2	156511	16046	0	0
T3	829	5	0	0
T4	5352	116	0	0
T14	541726	3068	0	0
T15	2917	9	0	0
T16	43856	312	0	0
T17	190969	0	0	0
T18	563	5	0	0
T19	4616	32	0	0
T20	4693	84	0	0
T21	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1494925	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1494925	0	0
T1	346929	1252	0	0
T2	156511	15362	0	0
T3	829	8	0	0
T4	5352	106	0	0
T14	541726	3554	0	0
T15	2917	12	0	0
T16	43856	173	0	0
T17	190969	1036	0	0
T18	563	3	0	0
T19	4616	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3661366	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3661366	0	0
T1	346929	101241	0	0
T2	156511	14749	0	0
T3	829	8	0	0
T4	5352	106	0	0
T14	541726	3318	0	0
T15	2917	4	0	0
T16	43856	257	0	0
T17	190969	83178	0	0
T18	563	3	0	0
T19	4616	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1511477	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1511477	0	0
T1	346929	928	0	0
T2	156511	13727	0	0
T3	829	6	0	0
T4	5352	88	0	0
T14	541726	7562	0	0
T15	2917	19	0	0
T16	43856	307	0	0
T17	190969	0	0	0
T18	563	8	0	0
T19	4616	10	0	0
T20	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3301945	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3301945	0	0
T1	346929	73943	0	0
T2	156511	13736	0	0
T3	829	6	0	0
T4	5352	88	0	0
T14	541726	6146	0	0
T15	2917	32	0	0
T16	43856	299	0	0
T17	190969	0	0	0
T18	563	8	0	0
T19	4616	15	0	0
T20	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1530964	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1530964	0	0
T2	156511	14761	0	0
T3	829	6	0	0
T4	5352	114	0	0
T14	541726	6009	0	0
T15	2917	11	0	0
T16	43856	313	0	0
T17	190969	0	0	0
T18	563	5	0	0
T19	4616	28	0	0
T20	4693	64	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3265179	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3265179	0	0
T2	156511	10845	0	0
T3	829	6	0	0
T4	5352	114	0	0
T14	541726	5212	0	0
T15	2917	13	0	0
T16	43856	293	0	0
T17	190969	0	0	0
T18	563	5	0	0
T19	4616	19	0	0
T20	4693	64	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1531313	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1531313	0	0
T2	156511	16620	0	0
T3	829	2	0	0
T4	5352	89	0	0
T14	541726	8294	0	0
T15	2917	16	0	0
T16	43856	179	0	0
T17	190969	0	0	0
T18	563	3	0	0
T19	4616	119	0	0
T20	4693	102	0	0
T21	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3727165	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3727165	0	0
T2	156511	17388	0	0
T3	829	2	0	0
T4	5352	89	0	0
T14	541726	7003	0	0
T15	2917	7	0	0
T16	43856	187	0	0
T17	190969	0	0	0
T18	563	3	0	0
T19	4616	38	0	0
T20	4693	102	0	0
T21	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1504024	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1504024	0	0
T1	346929	1199	0	0
T2	156511	10794	0	0
T3	829	7	0	0
T4	5352	86	0	0
T14	541726	3481	0	0
T15	2917	7	0	0
T16	43856	215	0	0
T17	190969	0	0	0
T18	563	2	0	0
T19	4616	63	0	0
T20	0	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3050202	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3050202	0	0
T1	346929	94816	0	0
T2	156511	16149	0	0
T3	829	7	0	0
T4	5352	86	0	0
T14	541726	3167	0	0
T15	2917	6	0	0
T16	43856	231	0	0
T17	190969	0	0	0
T18	563	2	0	0
T19	4616	37	0	0
T20	0	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1530207	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1530207	0	0
T1	346929	1269	0	0
T2	156511	19560	0	0
T3	829	4	0	0
T4	5352	88	0	0
T14	541726	5124	0	0
T15	2917	74	0	0
T16	43856	269	0	0
T17	190969	0	0	0
T18	563	5	0	0
T19	4616	24	0	0
T20	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3098161	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3098161	0	0
T1	346929	102564	0	0
T2	156511	20393	0	0
T3	829	4	0	0
T4	5352	88	0	0
T14	541726	4217	0	0
T15	2917	58	0	0
T16	43856	280	0	0
T17	190969	0	0	0
T18	563	5	0	0
T19	4616	9	0	0
T20	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1552076	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1552076	0	0
T2	156511	11815	0	0
T3	829	4	0	0
T4	5352	87	0	0
T14	541726	4044	0	0
T15	2917	4	0	0
T16	43856	328	0	0
T17	190969	2000	0	0
T18	563	4	0	0
T19	4616	75	0	0
T20	4693	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3148075	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3148075	0	0
T2	156511	10479	0	0
T3	829	4	0	0
T4	5352	87	0	0
T14	541726	3389	0	0
T15	2917	6	0	0
T16	43856	285	0	0
T17	190969	165899	0	0
T18	563	4	0	0
T19	4616	40	0	0
T20	4693	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1513666	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1513666	0	0
T1	346929	937	0	0
T2	156511	13549	0	0
T3	829	7	0	0
T4	5352	89	0	0
T14	541726	8028	0	0
T15	2917	12	0	0
T16	43856	262	0	0
T17	190969	1168	0	0
T18	563	6	0	0
T19	4616	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3003420	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3003420	0	0
T1	346929	73134	0	0
T2	156511	9697	0	0
T3	829	7	0	0
T4	5352	89	0	0
T14	541726	6646	0	0
T15	2917	32	0	0
T16	43856	289	0	0
T17	190969	84358	0	0
T18	563	6	0	0
T19	4616	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1458953	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1458953	0	0
T2	156511	8781	0	0
T3	829	3	0	0
T4	5352	83	0	0
T14	541726	6245	0	0
T15	2917	5	0	0
T16	43856	254	0	0
T17	190969	1259	0	0
T18	563	6	0	0
T19	4616	83	0	0
T20	4693	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	2994915	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	2994915	0	0
T2	156511	9856	0	0
T3	829	3	0	0
T4	5352	83	0	0
T14	541726	5117	0	0
T15	2917	17	0	0
T16	43856	245	0	0
T17	190969	98729	0	0
T18	563	6	0	0
T19	4616	19	0	0
T20	4693	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1480220	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1480220	0	0
T2	156511	16946	0	0
T3	829	5	0	0
T4	5352	86	0	0
T14	541726	6644	0	0
T15	2917	1	0	0
T16	43856	328	0	0
T17	190969	0	0	0
T18	563	4	0	0
T19	4616	66	0	0
T20	4693	98	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	2295541	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	2295541	0	0
T2	156511	16197	0	0
T3	829	5	0	0
T4	5352	86	0	0
T14	541726	6042	0	0
T15	2917	6	0	0
T16	43856	371	0	0
T17	190969	0	0	0
T18	563	4	0	0
T19	4616	22	0	0
T20	4693	98	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1501951	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1501951	0	0
T1	346929	3480	0	0
T2	156511	20093	0	0
T3	829	5	0	0
T4	5352	107	0	0
T14	541726	7704	0	0
T15	2917	23	0	0
T16	43856	407	0	0
T17	190969	1181	0	0
T18	563	4	0	0
T19	4616	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	2737948	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	2737948	0	0
T1	346929	276779	0	0
T2	156511	15684	0	0
T3	829	5	0	0
T4	5352	107	0	0
T14	541726	6194	0	0
T15	2917	28	0	0
T16	43856	296	0	0
T17	190969	87447	0	0
T18	563	4	0	0
T19	4616	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1480949	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1480949	0	0
T1	346929	1328	0	0
T2	156511	14602	0	0
T3	829	7	0	0
T4	5352	105	0	0
T14	541726	3498	0	0
T15	2917	16	0	0
T16	43856	266	0	0
T17	190969	0	0	0
T18	563	5	0	0
T19	4616	61	0	0
T20	0	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3516638	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3516638	0	0
T1	346929	107728	0	0
T2	156511	12589	0	0
T3	829	7	0	0
T4	5352	105	0	0
T14	541726	3092	0	0
T15	2917	29	0	0
T16	43856	276	0	0
T17	190969	0	0	0
T18	563	5	0	0
T19	4616	21	0	0
T20	0	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1485655	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1485655	0	0
T1	346929	1115	0	0
T2	156511	12120	0	0
T3	829	9	0	0
T4	5352	94	0	0
T14	541726	4968	0	0
T15	2917	0	0	0
T16	43856	283	0	0
T17	190969	0	0	0
T18	563	4	0	0
T19	4616	37	0	0
T20	0	90	0	0
T21	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	3307360	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	3307360	0	0
T1	346929	94141	0	0
T2	156511	12371	0	0
T3	829	9	0	0
T4	5352	94	0	0
T14	541726	4372	0	0
T15	2917	0	0	0
T16	43856	240	0	0
T17	190969	0	0	0
T18	563	4	0	0
T19	4616	22	0	0
T20	0	90	0	0
T21	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1517324	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1517324	0	0
T1	346929	1334	0	0
T2	156511	13691	0	0
T3	829	6	0	0
T4	5352	88	0	0
T14	541726	3840	0	0
T15	2917	27	0	0
T16	43856	329	0	0
T17	190969	0	0	0
T18	563	8	0	0
T19	4616	50	0	0
T20	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	2549946	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	2549946	0	0
T1	346929	99493	0	0
T2	156511	10595	0	0
T3	829	6	0	0
T4	5352	88	0	0
T14	541726	3365	0	0
T15	2917	34	0	0
T16	43856	396	0	0
T17	190969	0	0	0
T18	563	8	0	0
T19	4616	20	0	0
T20	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	1495235	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	1495235	0	0
T2	156511	13774	0	0
T3	829	8	0	0
T4	5352	80	0	0
T14	541726	7281	0	0
T15	2917	0	0	0
T16	43856	350	0	0
T17	190969	0	0	0
T18	563	3	0	0
T19	4616	17	0	0
T20	4693	85	0	0
T21	0	8	0	0
T22	0	633	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	298400149	2845070	0	0
DepthKnown_A	298400149	298271249	0	0
RvalidKnown_A	298400149	298271249	0	0
WreadyKnown_A	298400149	298271249	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	2845070	0	0
T2	156511	14878	0	0
T3	829	8	0	0
T4	5352	80	0	0
T14	541726	5676	0	0
T15	2917	0	0	0
T16	43856	295	0	0
T17	190969	0	0	0
T18	563	3	0	0
T19	4616	22	0	0
T20	4693	85	0	0
T21	0	8	0	0
T22	0	633	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298400149	298271249	0	0
T1	346929	346925	0	0
T2	156511	156509	0	0
T3	829	746	0	0
T4	5352	5281	0	0
T14	541726	541671	0	0
T15	2917	2844	0	0
T16	43856	43760	0	0
T17	190969	190962	0	0
T18	563	524	0	0
T19	4616	4600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0