Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1632567	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256884

1

T1

16

T2

2

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	640192	1			T1	42		T2	23		T3	132
values[0x0]	607741	1			T1	44		T2	5		T3	14
values[0x1]	641518	1			T1	36		T2	24		T3	160

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1263199	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

626252

1

T1

37

T2

13

T3

94

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7435	1			T1	1		T13	19		T14	5
valid_sources[0x01]	7452	1			T1	3		T2	1		T3	2
valid_sources[0x02]	6909	1			T3	1		T14	9		T10	59
valid_sources[0x03]	7025	1			T3	1		T14	8		T10	20
valid_sources[0x04]	7080	1			T14	15		T10	15		T12	1
valid_sources[0x05]	7486	1			T3	4		T14	9		T10	45
valid_sources[0x06]	7734	1			T13	10		T14	21		T10	46
valid_sources[0x07]	7708	1			T3	2		T13	20		T14	5
valid_sources[0x08]	7476	1			T2	1		T13	36		T14	7
valid_sources[0x09]	6626	1			T14	11		T10	36		T12	1
valid_sources[0x0a]	7543	1			T2	1		T14	6		T10	45
valid_sources[0x0b]	8612	1			T3	3		T14	3		T10	24
valid_sources[0x0c]	9099	1			T3	1		T13	6		T14	17
valid_sources[0x0d]	6789	1			T2	1		T3	1		T14	15
valid_sources[0x0e]	7361	1			T14	7		T10	54		T12	1
valid_sources[0x0f]	7882	1			T14	8		T10	63		T15	7
valid_sources[0x10]	7101	1			T3	1		T13	6		T14	4
valid_sources[0x11]	6928	1			T1	4		T3	1		T14	5
valid_sources[0x12]	7556	1			T14	23		T10	55		T15	14
valid_sources[0x13]	7201	1			T13	20		T14	7		T10	70
valid_sources[0x14]	7009	1			T13	15		T14	8		T10	40
valid_sources[0x15]	8494	1			T3	1		T13	11		T14	7
valid_sources[0x16]	7459	1			T14	3		T10	25		T11	1
valid_sources[0x17]	7145	1			T14	8		T10	33		T11	2
valid_sources[0x18]	7808	1			T3	2		T14	13		T10	57
valid_sources[0x19]	7037	1			T3	4		T14	6		T10	23
valid_sources[0x1a]	7468	1			T14	6		T10	39		T12	2
valid_sources[0x1b]	7158	1			T13	11		T14	8		T10	49
valid_sources[0x1c]	7036	1			T13	11		T14	1		T10	102
valid_sources[0x1d]	6681	1			T14	6		T10	20		T11	1
valid_sources[0x1e]	6822	1			T10	29		T16	1		T19	24
valid_sources[0x1f]	7550	1			T2	1		T14	10		T10	52
valid_sources[0x20]	7978	1			T14	4		T10	34		T19	14
valid_sources[0x21]	8839	1			T13	14		T14	10		T10	66
valid_sources[0x22]	7296	1			T2	1		T14	14		T10	46
valid_sources[0x23]	6890	1			T14	8		T10	37		T12	5
valid_sources[0x24]	8153	1			T1	8		T2	1		T14	8
valid_sources[0x25]	6983	1			T3	1		T14	8		T10	38
valid_sources[0x26]	6941	1			T13	18		T14	3		T10	34
valid_sources[0x27]	7111	1			T3	5		T14	3		T10	45
valid_sources[0x28]	7562	1			T3	1		T14	6		T10	37
valid_sources[0x29]	6553	1			T3	4		T13	7		T14	3
valid_sources[0x2a]	8851	1			T3	1		T14	4		T10	52
valid_sources[0x2b]	7360	1			T2	1		T3	1		T13	15
valid_sources[0x2c]	6760	1			T3	1		T14	6		T10	29
valid_sources[0x2d]	8653	1			T3	1		T14	10		T10	59
valid_sources[0x2e]	7997	1			T14	6		T10	20		T11	3
valid_sources[0x2f]	7107	1			T2	1		T3	1		T13	20
valid_sources[0x30]	6976	1			T3	1		T14	3		T10	55
valid_sources[0x31]	7326	1			T1	4		T14	7		T10	22
valid_sources[0x32]	7375	1			T14	14		T10	41		T12	1
valid_sources[0x33]	6455	1			T14	2		T10	26		T19	6
valid_sources[0x34]	7507	1			T14	8		T10	47		T15	4
valid_sources[0x35]	7658	1			T3	3		T13	14		T14	12
valid_sources[0x36]	7321	1			T3	1		T14	12		T10	20
valid_sources[0x37]	7457	1			T2	1		T14	4		T10	24
valid_sources[0x38]	7948	1			T2	1		T14	6		T10	26
valid_sources[0x39]	7026	1			T13	16		T14	8		T10	23
valid_sources[0x3a]	7066	1			T2	1		T14	6		T10	18
valid_sources[0x3b]	8051	1			T14	18		T10	84		T15	3
valid_sources[0x3c]	7335	1			T3	1		T14	10		T10	38
valid_sources[0x3d]	6989	1			T14	11		T10	65		T12	4
valid_sources[0x3e]	7208	1			T3	2		T14	11		T10	36
valid_sources[0x3f]	8008	1			T3	2		T14	2		T10	32
valid_sources[0x40]	7423	1			T1	6		T14	17		T10	30
valid_sources[0x41]	8886	1			T2	2		T3	1		T10	40
valid_sources[0x42]	6425	1			T2	1		T3	5		T13	20
valid_sources[0x43]	8017	1			T3	1		T14	3		T10	46
valid_sources[0x44]	7024	1			T13	13		T14	7		T10	47
valid_sources[0x45]	7406	1			T14	8		T10	23		T11	6
valid_sources[0x46]	7397	1			T14	7		T10	10		T15	8
valid_sources[0x47]	7226	1			T2	1		T3	4		T14	18
valid_sources[0x48]	7436	1			T2	1		T14	7		T10	18
valid_sources[0x49]	8238	1			T3	3		T14	9		T10	49
valid_sources[0x4a]	7738	1			T3	2		T14	4		T10	35
valid_sources[0x4b]	7546	1			T3	2		T14	10		T10	38
valid_sources[0x4c]	7447	1			T3	2		T13	5		T14	1
valid_sources[0x4d]	7211	1			T1	3		T13	18		T14	6
valid_sources[0x4e]	6788	1			T1	1		T2	1		T3	8
valid_sources[0x4f]	7455	1			T14	7		T10	37		T15	8
valid_sources[0x50]	7328	1			T3	3		T14	2		T10	32
valid_sources[0x51]	7338	1			T3	1		T14	11		T10	22
valid_sources[0x52]	7460	1			T1	3		T3	10		T14	5
valid_sources[0x53]	6699	1			T1	5		T3	2		T14	3
valid_sources[0x54]	7335	1			T14	2		T10	49		T15	16
valid_sources[0x55]	8306	1			T3	13		T14	9		T10	40
valid_sources[0x56]	7314	1			T14	9		T10	34		T11	1
valid_sources[0x57]	7038	1			T3	1		T14	6		T10	45
valid_sources[0x58]	7397	1			T13	7		T14	3		T10	43
valid_sources[0x59]	7473	1			T1	3		T14	2		T10	33
valid_sources[0x5a]	7930	1			T3	1		T14	2		T10	12
valid_sources[0x5b]	7430	1			T3	2		T14	8		T10	19
valid_sources[0x5c]	8393	1			T3	5		T13	17		T14	7
valid_sources[0x5d]	6779	1			T1	5		T13	7		T14	5
valid_sources[0x5e]	7176	1			T1	3		T13	15		T14	11
valid_sources[0x5f]	8239	1			T3	1		T13	19		T14	10
valid_sources[0x60]	8555	1			T14	5		T10	39		T12	2
valid_sources[0x61]	7347	1			T2	1		T14	5		T10	54
valid_sources[0x62]	7264	1			T3	1		T13	12		T14	22
valid_sources[0x63]	7155	1			T1	1		T3	3		T13	19
valid_sources[0x64]	8223	1			T3	2		T14	5		T10	55
valid_sources[0x65]	7090	1			T14	1		T10	73		T15	17
valid_sources[0x66]	6708	1			T13	7		T14	3		T10	62
valid_sources[0x67]	7087	1			T13	6		T14	11		T10	50
valid_sources[0x68]	7318	1			T2	3		T14	4		T10	49
valid_sources[0x69]	6919	1			T1	3		T3	1		T14	5
valid_sources[0x6a]	6625	1			T2	2		T3	3		T14	8
valid_sources[0x6b]	8251	1			T3	1		T14	1		T10	24
valid_sources[0x6c]	7197	1			T3	4		T14	7		T10	37
valid_sources[0x6d]	7204	1			T3	2		T14	6		T10	52
valid_sources[0x6e]	8792	1			T3	1		T14	10		T10	24
valid_sources[0x6f]	7839	1			T1	2		T2	1		T3	1
valid_sources[0x70]	8135	1			T13	14		T14	11		T10	27
valid_sources[0x71]	7300	1			T13	16		T14	14		T10	24
valid_sources[0x72]	7255	1			T13	17		T14	1		T10	33
valid_sources[0x73]	7452	1			T13	15		T14	10		T10	28
valid_sources[0x74]	6863	1			T1	1		T14	9		T10	45
valid_sources[0x75]	6479	1			T13	14		T14	2		T10	41
valid_sources[0x76]	7087	1			T3	1		T13	12		T14	5
valid_sources[0x77]	8014	1			T14	15		T10	58		T12	2
valid_sources[0x78]	7203	1			T1	2		T14	4		T10	44
valid_sources[0x79]	8247	1			T1	4		T2	2		T14	17
valid_sources[0x7a]	7361	1			T14	7		T10	21		T12	4
valid_sources[0x7b]	8514	1			T3	1		T14	13		T10	41
valid_sources[0x7c]	6904	1			T3	1		T14	6		T10	9
valid_sources[0x7d]	7332	1			T3	3		T14	1		T10	26
valid_sources[0x7e]	7667	1			T1	6		T2	1		T3	2
valid_sources[0x7f]	8225	1			T13	7		T14	11		T10	44
valid_sources[0x80]	8510	1			T3	2		T14	22		T10	51

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27201

1

T1

2

T2

1

T3

10

values[0x0]

all_enables

biggest_size

202324

1

T1

12

T2

1

T3

8

values[0x1]

all_enables

biggest_size

27359

1

T1

2

T3

8

T13

10