Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	345359661	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345359661	0	0
T1	3291064	58302	0	0
T2	1878352	36215	0	0
T3	9702392	221637	0	0
T10	1139936	42808	0	0
T11	114912	3672	0	0
T12	11250456	248829	0	0
T13	156016	4414	0	0
T14	10750544	1966519	0	0
T15	185640	7864	0	0
T16	4515784	80548	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3291064	3288656	0	0
T2	1878352	1873648	0	0
T3	9702392	9697968	0	0
T10	1139936	1079288	0	0
T11	114912	113008	0	0
T12	11250456	11248944	0	0
T13	156016	150640	0	0
T14	10750544	10750152	0	0
T15	185640	184128	0	0
T16	4515784	4514216	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3291064	3288656	0	0
T2	1878352	1873648	0	0
T3	9702392	9697968	0	0
T10	1139936	1079288	0	0
T11	114912	113008	0	0
T12	11250456	11248944	0	0
T13	156016	150640	0	0
T14	10750544	10750152	0	0
T15	185640	184128	0	0
T16	4515784	4514216	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3291064	3288656	0	0
T2	1878352	1873648	0	0
T3	9702392	9697968	0	0
T10	1139936	1079288	0	0
T11	114912	113008	0	0
T12	11250456	11248944	0	0
T13	156016	150640	0	0
T14	10750544	10750152	0	0
T15	185640	184128	0	0
T16	4515784	4514216	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T10	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	127537908	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	127537908	0	0
T1	58769	55213	0	0
T2	33542	15924	0	0
T3	173257	83722	0	0
T10	20356	17327	0	0
T11	2052	1803	0	0
T12	200901	92801	0	0
T13	2786	1107	0	0
T14	191974	907328	0	0
T15	3315	3068	0	0
T16	80639	79069	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	87819602	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	87819602	0	0
T1	58769	1300	0	0
T2	33542	4954	0	0
T3	173257	41729	0	0
T10	20356	9643	0	0
T11	2052	921	0	0
T12	200901	50508	0	0
T13	2786	1107	0	0
T14	191974	219458	0	0
T15	3315	1600	0	0
T16	80639	393	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1598996	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1598996	0	0
T1	58769	16	0	0
T2	33542	351	0	0
T3	173257	5819	0	0
T10	20356	244	0	0
T11	2052	13	0	0
T12	200901	1111	0	0
T13	2786	45	0	0
T14	191974	24249	0	0
T15	3315	67	0	0
T16	80639	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	2664925	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	2664925	0	0
T1	58769	4	0	0
T2	33542	185	0	0
T3	173257	4006	0	0
T10	20356	243	0	0
T11	2052	13	0	0
T12	200901	981	0	0
T13	2786	45	0	0
T14	191974	7744	0	0
T15	3315	67	0	0
T16	80639	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1603712	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1603712	0	0
T1	58769	20	0	0
T2	33542	354	0	0
T3	173257	988	0	0
T10	20356	252	0	0
T11	2052	12	0	0
T12	200901	934	0	0
T13	2786	24	0	0
T14	191974	22815	0	0
T15	3315	57	0	0
T16	80639	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3721719	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3721719	0	0
T1	58769	4	0	0
T2	33542	198	0	0
T3	173257	854	0	0
T10	20356	252	0	0
T11	2052	12	0	0
T12	200901	880	0	0
T13	2786	24	0	0
T14	191974	7465	0	0
T15	3315	57	0	0
T16	80639	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1588091	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1588091	0	0
T1	58769	24	0	0
T2	33542	427	0	0
T3	173257	1256	0	0
T10	20356	266	0	0
T11	2052	21	0	0
T12	200901	1140	0	0
T13	2786	36	0	0
T14	191974	23323	0	0
T15	3315	72	0	0
T16	80639	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3086738	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3086738	0	0
T1	58769	7	0	0
T2	33542	196	0	0
T3	173257	787	0	0
T10	20356	266	0	0
T11	2052	21	0	0
T12	200901	978	0	0
T13	2786	36	0	0
T14	191974	7725	0	0
T15	3315	72	0	0
T16	80639	238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1571452	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1571452	0	0
T1	58769	11	0	0
T2	33542	399	0	0
T3	173257	826	0	0
T10	20356	264	0	0
T11	2052	20	0	0
T12	200901	1041	0	0
T13	2786	39	0	0
T14	191974	13835	0	0
T15	3315	62	0	0
T16	80639	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3849966	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3849966	0	0
T1	58769	1174	0	0
T2	33542	224	0	0
T3	173257	647	0	0
T10	20356	264	0	0
T11	2052	20	0	0
T12	200901	867	0	0
T13	2786	39	0	0
T14	191974	6241	0	0
T15	3315	62	0	0
T16	80639	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1644233	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1644233	0	0
T1	58769	14	0	0
T2	33542	359	0	0
T3	173257	1039	0	0
T10	20356	277	0	0
T11	2052	22	0	0
T12	200901	3936	0	0
T13	2786	44	0	0
T14	191974	26979	0	0
T15	3315	56	0	0
T16	80639	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3412476	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3412476	0	0
T1	58769	4	0	0
T2	33542	237	0	0
T3	173257	877	0	0
T10	20356	277	0	0
T11	2052	22	0	0
T12	200901	3616	0	0
T13	2786	44	0	0
T14	191974	7802	0	0
T15	3315	56	0	0
T16	80639	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1583202	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1583202	0	0
T1	58769	15	0	0
T2	33542	351	0	0
T3	173257	2958	0	0
T10	20356	281	0	0
T11	2052	13	0	0
T12	200901	1045	0	0
T13	2786	37	0	0
T14	191974	27108	0	0
T15	3315	61	0	0
T16	80639	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	2550139	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	2550139	0	0
T1	58769	6	0	0
T2	33542	120	0	0
T3	173257	2201	0	0
T10	20356	281	0	0
T11	2052	13	0	0
T12	200901	767	0	0
T13	2786	37	0	0
T14	191974	9985	0	0
T15	3315	61	0	0
T16	80639	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1549795	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1549795	0	0
T1	58769	27	0	0
T2	33542	422	0	0
T3	173257	4909	0	0
T10	20356	255	0	0
T11	2052	17	0	0
T12	200901	1027	0	0
T13	2786	39	0	0
T14	191974	27251	0	0
T15	3315	61	0	0
T16	80639	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3240706	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3240706	0	0
T1	58769	6	0	0
T2	33542	140	0	0
T3	173257	3640	0	0
T10	20356	255	0	0
T11	2052	17	0	0
T12	200901	853	0	0
T13	2786	39	0	0
T14	191974	12186	0	0
T15	3315	61	0	0
T16	80639	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1615579	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1615579	0	0
T1	58769	12	0	0
T2	33542	556	0	0
T3	173257	3425	0	0
T10	20356	280	0	0
T11	2052	21	0	0
T12	200901	3127	0	0
T13	2786	46	0	0
T14	191974	19578	0	0
T15	3315	66	0	0
T16	80639	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3240133	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3240133	0	0
T1	58769	5	0	0
T2	33542	270	0	0
T3	173257	2525	0	0
T10	20356	280	0	0
T11	2052	21	0	0
T12	200901	2563	0	0
T13	2786	46	0	0
T14	191974	7193	0	0
T15	3315	66	0	0
T16	80639	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1600811	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1600811	0	0
T1	58769	26	0	0
T2	33542	348	0	0
T3	173257	3259	0	0
T10	20356	275	0	0
T11	2052	14	0	0
T12	200901	1169	0	0
T13	2786	43	0	0
T14	191974	28264	0	0
T15	3315	63	0	0
T16	80639	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3571450	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3571450	0	0
T1	58769	5	0	0
T2	33542	178	0	0
T3	173257	2621	0	0
T10	20356	275	0	0
T11	2052	14	0	0
T12	200901	888	0	0
T13	2786	43	0	0
T14	191974	6466	0	0
T15	3315	63	0	0
T16	80639	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1638372	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1638372	0	0
T1	58769	9	0	0
T2	33542	322	0	0
T3	173257	2279	0	0
T10	20356	257	0	0
T11	2052	15	0	0
T12	200901	852	0	0
T13	2786	37	0	0
T14	191974	25240	0	0
T15	3315	53	0	0
T16	80639	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3103562	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3103562	0	0
T1	58769	9	0	0
T2	33542	160	0	0
T3	173257	1986	0	0
T10	20356	257	0	0
T11	2052	15	0	0
T12	200901	798	0	0
T13	2786	37	0	0
T14	191974	9988	0	0
T15	3315	53	0	0
T16	80639	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1607610	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1607610	0	0
T1	58769	12	0	0
T2	33542	306	0	0
T3	173257	2163	0	0
T10	20356	355	0	0
T11	2052	21	0	0
T12	200901	1073	0	0
T13	2786	39	0	0
T14	191974	23799	0	0
T15	3315	68	0	0
T16	80639	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3421678	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3421678	0	0
T1	58769	4	0	0
T2	33542	169	0	0
T3	173257	2157	0	0
T10	20356	354	0	0
T11	2052	21	0	0
T12	200901	780	0	0
T13	2786	39	0	0
T14	191974	8651	0	0
T15	3315	68	0	0
T16	80639	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1599663	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1599663	0	0
T1	58769	23	0	0
T2	33542	423	0	0
T3	173257	1073	0	0
T10	20356	259	0	0
T11	2052	20	0	0
T12	200901	1233	0	0
T13	2786	39	0	0
T14	191974	19613	0	0
T15	3315	65	0	0
T16	80639	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3043553	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3043553	0	0
T1	58769	6	0	0
T2	33542	172	0	0
T3	173257	866	0	0
T10	20356	259	0	0
T11	2052	20	0	0
T12	200901	983	0	0
T13	2786	39	0	0
T14	191974	6054	0	0
T15	3315	65	0	0
T16	80639	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1610482	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1610482	0	0
T1	58769	20	0	0
T2	33542	416	0	0
T3	173257	1175	0	0
T10	20356	253	0	0
T11	2052	12	0	0
T12	200901	2865	0	0
T13	2786	41	0	0
T14	191974	24208	0	0
T15	3315	48	0	0
T16	80639	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	2810463	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	2810463	0	0
T1	58769	5	0	0
T2	33542	144	0	0
T3	173257	859	0	0
T10	20356	253	0	0
T11	2052	12	0	0
T12	200901	2048	0	0
T13	2786	41	0	0
T14	191974	5316	0	0
T15	3315	48	0	0
T16	80639	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1590888	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1590888	0	0
T1	58769	19	0	0
T2	33542	314	0	0
T3	173257	917	0	0
T10	20356	223	0	0
T11	2052	12	0	0
T12	200901	4786	0	0
T13	2786	54	0	0
T14	191974	29380	0	0
T15	3315	51	0	0
T16	80639	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3652189	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3652189	0	0
T1	58769	2	0	0
T2	33542	108	0	0
T3	173257	761	0	0
T10	20356	223	0	0
T11	2052	12	0	0
T12	200901	3350	0	0
T13	2786	54	0	0
T14	191974	9439	0	0
T15	3315	51	0	0
T16	80639	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1670310	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1670310	0	0
T1	58769	30	0	0
T2	33542	470	0	0
T3	173257	3012	0	0
T10	20356	246	0	0
T11	2052	15	0	0
T12	200901	3121	0	0
T13	2786	41	0	0
T14	191974	23078	0	0
T15	3315	60	0	0
T16	80639	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3882492	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3882492	0	0
T1	58769	7	0	0
T2	33542	170	0	0
T3	173257	2235	0	0
T10	20356	246	0	0
T11	2052	15	0	0
T12	200901	2774	0	0
T13	2786	41	0	0
T14	191974	7980	0	0
T15	3315	60	0	0
T16	80639	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1562806	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1562806	0	0
T1	58769	17	0	0
T2	33542	401	0	0
T3	173257	981	0	0
T10	20356	289	0	0
T11	2052	20	0	0
T12	200901	1095	0	0
T13	2786	46	0	0
T14	191974	16342	0	0
T15	3315	43	0	0
T16	80639	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	2990589	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	2990589	0	0
T1	58769	3	0	0
T2	33542	119	0	0
T3	173257	847	0	0
T10	20356	289	0	0
T11	2052	20	0	0
T12	200901	844	0	0
T13	2786	46	0	0
T14	191974	7674	0	0
T15	3315	43	0	0
T16	80639	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1650678	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1650678	0	0
T1	58769	21	0	0
T2	33542	395	0	0
T3	173257	1094	0	0
T10	20356	275	0	0
T11	2052	16	0	0
T12	200901	1045	0	0
T13	2786	35	0	0
T14	191974	24352	0	0
T15	3315	56	0	0
T16	80639	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3537230	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3537230	0	0
T1	58769	7	0	0
T2	33542	181	0	0
T3	173257	837	0	0
T10	20356	275	0	0
T11	2052	16	0	0
T12	200901	790	0	0
T13	2786	35	0	0
T14	191974	9439	0	0
T15	3315	56	0	0
T16	80639	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1627396	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1627396	0	0
T1	58769	1	0	0
T2	33542	314	0	0
T3	173257	1224	0	0
T10	20356	261	0	0
T11	2052	18	0	0
T12	200901	1148	0	0
T13	2786	47	0	0
T14	191974	23119	0	0
T15	3315	61	0	0
T16	80639	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	2984028	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	2984028	0	0
T1	58769	1	0	0
T2	33542	155	0	0
T3	173257	992	0	0
T10	20356	261	0	0
T11	2052	18	0	0
T12	200901	994	0	0
T13	2786	47	0	0
T14	191974	7670	0	0
T15	3315	61	0	0
T16	80639	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1588602	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1588602	0	0
T1	58769	16	0	0
T2	33542	429	0	0
T3	173257	1204	0	0
T10	20356	521	0	0
T11	2052	16	0	0
T12	200901	4164	0	0
T13	2786	48	0	0
T14	191974	18214	0	0
T15	3315	51	0	0
T16	80639	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	4008056	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	4008056	0	0
T1	58769	3	0	0
T2	33542	153	0	0
T3	173257	910	0	0
T10	20356	521	0	0
T11	2052	16	0	0
T12	200901	3940	0	0
T13	2786	48	0	0
T14	191974	6547	0	0
T15	3315	51	0	0
T16	80639	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1597739	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1597739	0	0
T1	58769	20	0	0
T2	33542	323	0	0
T3	173257	1044	0	0
T10	20356	273	0	0
T11	2052	15	0	0
T12	200901	2513	0	0
T13	2786	42	0	0
T14	191974	18261	0	0
T15	3315	75	0	0
T16	80639	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	2908917	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	2908917	0	0
T1	58769	5	0	0
T2	33542	121	0	0
T3	173257	760	0	0
T10	20356	273	0	0
T11	2052	15	0	0
T12	200901	2189	0	0
T13	2786	42	0	0
T14	191974	5892	0	0
T15	3315	75	0	0
T16	80639	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1642589	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1642589	0	0
T1	58769	12	0	0
T2	33542	398	0	0
T3	173257	3351	0	0
T10	20356	556	0	0
T11	2052	23	0	0
T12	200901	992	0	0
T13	2786	47	0	0
T14	191974	29439	0	0
T15	3315	54	0	0
T16	80639	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	2897424	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	2897424	0	0
T1	58769	2	0	0
T2	33542	162	0	0
T3	173257	2425	0	0
T10	20356	556	0	0
T11	2052	23	0	0
T12	200901	802	0	0
T13	2786	47	0	0
T14	191974	10164	0	0
T15	3315	54	0	0
T16	80639	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1590129	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1590129	0	0
T1	58769	28	0	0
T2	33542	357	0	0
T3	173257	2777	0	0
T10	20356	268	0	0
T11	2052	21	0	0
T12	200901	3312	0	0
T13	2786	40	0	0
T14	191974	18540	0	0
T15	3315	52	0	0
T16	80639	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3280588	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3280588	0	0
T1	58769	6	0	0
T2	33542	243	0	0
T3	173257	2325	0	0
T10	20356	268	0	0
T11	2052	21	0	0
T12	200901	2486	0	0
T13	2786	40	0	0
T14	191974	7393	0	0
T15	3315	52	0	0
T16	80639	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1611622	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1611622	0	0
T1	58769	32	0	0
T2	33542	371	0	0
T3	173257	1009	0	0
T10	20356	275	0	0
T11	2052	27	0	0
T12	200901	3238	0	0
T13	2786	41	0	0
T14	191974	24905	0	0
T15	3315	62	0	0
T16	80639	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3090578	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3090578	0	0
T1	58769	11	0	0
T2	33542	213	0	0
T3	173257	782	0	0
T10	20356	275	0	0
T11	2052	27	0	0
T12	200901	2319	0	0
T13	2786	41	0	0
T14	191974	9315	0	0
T15	3315	62	0	0
T16	80639	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1594323	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1594323	0	0
T1	58769	12	0	0
T2	33542	423	0	0
T3	173257	3261	0	0
T10	20356	228	0	0
T11	2052	20	0	0
T12	200901	6672	0	0
T13	2786	50	0	0
T14	191974	24058	0	0
T15	3315	58	0	0
T16	80639	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3084918	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3084918	0	0
T1	58769	4	0	0
T2	33542	247	0	0
T3	173257	2274	0	0
T10	20356	228	0	0
T11	2052	20	0	0
T12	200901	5358	0	0
T13	2786	50	0	0
T14	191974	10669	0	0
T15	3315	58	0	0
T16	80639	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1617272	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1617272	0	0
T1	58769	35	0	0
T2	33542	376	0	0
T3	173257	1154	0	0
T10	20356	475	0	0
T11	2052	14	0	0
T12	200901	1147	0	0
T13	2786	43	0	0
T14	191974	24327	0	0
T15	3315	51	0	0
T16	80639	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3091657	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3091657	0	0
T1	58769	6	0	0
T2	33542	251	0	0
T3	173257	812	0	0
T10	20356	475	0	0
T11	2052	14	0	0
T12	200901	948	0	0
T13	2786	43	0	0
T14	191974	11496	0	0
T15	3315	51	0	0
T16	80639	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1531690	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1531690	0	0
T1	58769	2	0	0
T2	33542	321	0	0
T3	173257	1329	0	0
T10	20356	284	0	0
T11	2052	20	0	0
T12	200901	974	0	0
T13	2786	35	0	0
T14	191974	19986	0	0
T15	3315	62	0	0
T16	80639	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	3203846	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	3203846	0	0
T1	58769	1	0	0
T2	33542	182	0	0
T3	173257	991	0	0
T10	20356	284	0	0
T11	2052	20	0	0
T12	200901	835	0	0
T13	2786	35	0	0
T14	191974	6637	0	0
T15	3315	62	0	0
T16	80639	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	1592833	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	1592833	0	0
T1	58769	15	0	0
T2	33542	457	0	0
T3	173257	933	0	0
T10	20356	228	0	0
T11	2052	16	0	0
T12	200901	3451	0	0
T13	2786	22	0	0
T14	191974	20012	0	0
T15	3315	63	0	0
T16	80639	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315569007	2391256	0	0
DepthKnown_A	315569007	315443237	0	0
RvalidKnown_A	315569007	315443237	0	0
WreadyKnown_A	315569007	315443237	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	2391256	0	0
T1	58769	3	0	0
T2	33542	256	0	0
T3	173257	750	0	0
T10	20356	228	0	0
T11	2052	16	0	0
T12	200901	2678	0	0
T13	2786	22	0	0
T14	191974	6327	0	0
T15	3315	63	0	0
T16	80639	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569007	315443237	0	0
T1	58769	58726	0	0
T2	33542	33458	0	0
T3	173257	173178	0	0
T10	20356	19273	0	0
T11	2052	2018	0	0
T12	200901	200874	0	0
T13	2786	2690	0	0
T14	191974	191967	0	0
T15	3315	3288	0	0
T16	80639	80611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0