Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1649378	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

259765

1

T1

1742

T2

433

T3

328

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	645404	1			T1	4513		T2	1059		T3	826
values[0x0]	617221	1			T1	4567		T2	996		T3	765
values[0x1]	646518	1			T1	4500		T2	973		T3	822

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1278806	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

630337

1

T1

4350

T2

998

T3

784

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7228	1			T1	43		T2	21		T14	15
valid_sources[0x01]	7105	1			T1	32		T2	15		T12	6
valid_sources[0x02]	8402	1			T1	24		T2	8		T3	24
valid_sources[0x03]	7555	1			T1	91		T2	9		T3	47
valid_sources[0x04]	6454	1			T1	73		T2	7		T3	2
valid_sources[0x05]	7245	1			T1	47		T2	8		T12	5
valid_sources[0x06]	7477	1			T1	55		T2	3		T12	7
valid_sources[0x07]	7807	1			T1	64		T2	39		T12	2
valid_sources[0x08]	8267	1			T1	28		T2	19		T3	53
valid_sources[0x09]	7970	1			T1	74		T2	7		T12	7
valid_sources[0x0a]	7079	1			T1	4		T2	7		T3	7
valid_sources[0x0b]	7688	1			T1	51		T2	16		T3	41
valid_sources[0x0c]	7495	1			T1	101		T2	13		T12	5
valid_sources[0x0d]	7306	1			T1	30		T2	15		T12	22
valid_sources[0x0e]	7419	1			T1	94		T2	3		T12	5
valid_sources[0x0f]	7000	1			T1	108		T2	6		T3	2
valid_sources[0x10]	7625	1			T1	54		T2	5		T12	5
valid_sources[0x11]	7157	1			T1	53		T2	4		T12	6
valid_sources[0x12]	6735	1			T1	60		T2	16		T12	2
valid_sources[0x13]	7142	1			T1	36		T2	4		T12	11
valid_sources[0x14]	7742	1			T1	71		T2	2		T3	53
valid_sources[0x15]	7904	1			T1	58		T2	8		T12	4
valid_sources[0x16]	7953	1			T1	54		T2	12		T12	2
valid_sources[0x17]	7378	1			T1	35		T2	9		T12	11
valid_sources[0x18]	7504	1			T1	49		T2	25		T3	24
valid_sources[0x19]	7156	1			T1	63		T2	31		T3	27
valid_sources[0x1a]	7685	1			T1	26		T2	7		T3	8
valid_sources[0x1b]	7661	1			T1	46		T2	12		T3	28
valid_sources[0x1c]	7542	1			T1	52		T2	15		T3	14
valid_sources[0x1d]	6928	1			T1	30		T2	5		T12	35
valid_sources[0x1e]	7376	1			T1	46		T2	5		T12	9
valid_sources[0x1f]	7369	1			T1	33		T2	7		T3	31
valid_sources[0x20]	8113	1			T1	16		T2	6		T12	43
valid_sources[0x21]	7566	1			T1	52		T2	16		T3	14
valid_sources[0x22]	7436	1			T1	40		T2	5		T3	50
valid_sources[0x23]	6589	1			T1	9		T2	4		T3	18
valid_sources[0x24]	8176	1			T1	60		T2	16		T3	8
valid_sources[0x25]	7315	1			T1	85		T2	12		T12	5
valid_sources[0x26]	6943	1			T1	87		T2	26		T12	8
valid_sources[0x27]	6996	1			T1	32		T2	10		T3	30
valid_sources[0x28]	8153	1			T1	25		T2	7		T12	7
valid_sources[0x29]	7435	1			T1	52		T2	10		T3	2
valid_sources[0x2a]	8771	1			T1	106		T2	7		T12	4
valid_sources[0x2b]	6859	1			T1	85		T2	11		T3	28
valid_sources[0x2c]	7572	1			T1	38		T2	5		T12	10
valid_sources[0x2d]	7751	1			T1	57		T2	6		T12	15
valid_sources[0x2e]	7221	1			T1	48		T2	7		T12	28
valid_sources[0x2f]	7486	1			T1	74		T2	25		T12	3
valid_sources[0x30]	7850	1			T1	44		T2	19		T12	1
valid_sources[0x31]	7812	1			T1	83		T2	11		T12	16
valid_sources[0x32]	7624	1			T1	112		T2	12		T12	8
valid_sources[0x33]	7352	1			T1	64		T2	4		T12	4
valid_sources[0x34]	7106	1			T1	48		T2	3		T12	9
valid_sources[0x35]	6882	1			T1	25		T2	8		T3	15
valid_sources[0x36]	7464	1			T1	111		T2	7		T3	31
valid_sources[0x37]	7342	1			T1	46		T2	1		T3	2
valid_sources[0x38]	8272	1			T1	44		T2	29		T12	5
valid_sources[0x39]	6806	1			T1	46		T2	6		T3	40
valid_sources[0x3a]	7946	1			T1	89		T2	6		T12	3
valid_sources[0x3b]	7645	1			T1	102		T2	19		T12	7
valid_sources[0x3c]	7582	1			T1	60		T2	6		T3	80
valid_sources[0x3d]	7141	1			T1	25		T2	35		T12	7
valid_sources[0x3e]	7526	1			T1	64		T2	12		T3	5
valid_sources[0x3f]	7883	1			T1	6		T2	7		T12	4
valid_sources[0x40]	7585	1			T1	27		T2	4		T3	12
valid_sources[0x41]	8654	1			T1	68		T2	3		T12	5
valid_sources[0x42]	7939	1			T1	45		T2	3		T12	12
valid_sources[0x43]	8669	1			T1	51		T2	9		T3	15
valid_sources[0x44]	7230	1			T1	42		T2	27		T3	13
valid_sources[0x45]	7652	1			T1	36		T2	5		T12	16
valid_sources[0x46]	7099	1			T1	45		T2	12		T12	19
valid_sources[0x47]	7151	1			T1	48		T2	6		T13	1
valid_sources[0x48]	6682	1			T1	46		T2	5		T3	27
valid_sources[0x49]	7221	1			T1	79		T2	24		T3	7
valid_sources[0x4a]	7174	1			T1	39		T2	18		T12	8
valid_sources[0x4b]	7759	1			T1	54		T2	11		T12	8
valid_sources[0x4c]	7429	1			T1	69		T2	20		T12	12
valid_sources[0x4d]	7294	1			T1	60		T2	14		T12	3
valid_sources[0x4e]	6917	1			T1	81		T2	13		T12	4
valid_sources[0x4f]	7502	1			T1	50		T2	18		T12	3
valid_sources[0x50]	7633	1			T1	38		T2	4		T12	42
valid_sources[0x51]	7215	1			T1	23		T2	4		T12	10
valid_sources[0x52]	7204	1			T1	93		T2	6		T3	34
valid_sources[0x53]	7060	1			T1	50		T2	5		T12	14
valid_sources[0x54]	7506	1			T1	34		T2	11		T12	3
valid_sources[0x55]	8220	1			T1	36		T2	6		T3	12
valid_sources[0x56]	8069	1			T1	78		T2	11		T12	25
valid_sources[0x57]	9140	1			T1	26		T2	31		T3	53
valid_sources[0x58]	7383	1			T1	29		T2	9		T12	24
valid_sources[0x59]	6905	1			T1	88		T2	12		T12	4
valid_sources[0x5a]	8104	1			T1	64		T2	14		T12	12
valid_sources[0x5b]	6947	1			T1	35		T2	5		T12	6
valid_sources[0x5c]	7300	1			T1	51		T2	13		T12	4
valid_sources[0x5d]	7051	1			T1	35		T2	6		T12	8
valid_sources[0x5e]	7590	1			T1	90		T2	28		T12	6
valid_sources[0x5f]	7831	1			T1	44		T2	32		T3	138
valid_sources[0x60]	8116	1			T1	102		T2	6		T12	11
valid_sources[0x61]	7667	1			T1	63		T2	20		T12	8
valid_sources[0x62]	7735	1			T1	55		T2	21		T12	4
valid_sources[0x63]	7255	1			T1	27		T2	8		T12	10
valid_sources[0x64]	7586	1			T1	19		T2	7		T13	1
valid_sources[0x65]	7699	1			T1	81		T2	8		T12	4
valid_sources[0x66]	6865	1			T1	36		T2	5		T12	6
valid_sources[0x67]	7562	1			T1	14		T2	8		T3	1
valid_sources[0x68]	7956	1			T1	64		T2	22		T12	2
valid_sources[0x69]	7820	1			T1	43		T2	4		T12	2
valid_sources[0x6a]	7179	1			T1	50		T2	49		T12	12
valid_sources[0x6b]	6760	1			T1	39		T2	13		T12	24
valid_sources[0x6c]	8036	1			T1	64		T2	5		T12	4
valid_sources[0x6d]	7473	1			T1	26		T2	6		T12	21
valid_sources[0x6e]	7551	1			T1	37		T2	5		T3	32
valid_sources[0x6f]	7481	1			T1	28		T2	34		T12	28
valid_sources[0x70]	6930	1			T1	18		T2	14		T12	2
valid_sources[0x71]	7910	1			T1	88		T2	5		T3	24
valid_sources[0x72]	6941	1			T1	43		T2	5		T12	4
valid_sources[0x73]	7353	1			T1	65		T2	9		T12	2
valid_sources[0x74]	7089	1			T1	21		T2	7		T12	10
valid_sources[0x75]	6862	1			T1	20		T2	18		T12	19
valid_sources[0x76]	7099	1			T1	20		T2	10		T12	17
valid_sources[0x77]	7686	1			T1	78		T2	11		T12	22
valid_sources[0x78]	7079	1			T1	72		T2	4		T12	4
valid_sources[0x79]	7878	1			T1	32		T2	9		T3	9
valid_sources[0x7a]	7073	1			T1	7		T2	7		T12	32
valid_sources[0x7b]	7925	1			T1	72		T2	8		T12	5
valid_sources[0x7c]	7104	1			T1	126		T2	5		T3	115
valid_sources[0x7d]	7449	1			T1	111		T2	10		T3	12
valid_sources[0x7e]	7088	1			T1	69		T2	2		T3	4
valid_sources[0x7f]	7283	1			T1	45		T2	27		T3	12
valid_sources[0x80]	7161	1			T1	51		T2	6		T14	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27528

1

T1

165

T2

45

T3

35

values[0x0]

all_enables

biggest_size

204565

1

T1

1418

T2

330

T3

269

values[0x1]

all_enables

biggest_size

27672

1

T1

159

T2

58

T3

24