Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	328177550	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328177550	0	0
T1	19934096	407860	0	0
T2	4584272	110018	0	0
T3	2449608	35598	0	0
T11	5766992	126612	0	0
T12	4304328	66717	0	0
T13	2534952	48027	0	0
T14	570528	21379	0	0
T15	2885960	51386	0	0
T16	6342784	157317	0	0
T17	4826304	136251	0	0
T18	0	168	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	19934096	19918640	0	0
T2	4584272	4561480	0	0
T3	2449608	2447760	0	0
T11	5766992	5766656	0	0
T12	4304328	4299568	0	0
T13	2534952	2531536	0	0
T14	570528	567672	0	0
T15	2885960	2882600	0	0
T16	6342784	6336344	0	0
T17	4826304	4823448	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	19934096	19918640	0	0
T2	4584272	4561480	0	0
T3	2449608	2447760	0	0
T11	5766992	5766656	0	0
T12	4304328	4299568	0	0
T13	2534952	2531536	0	0
T14	570528	567672	0	0
T15	2885960	2882600	0	0
T16	6342784	6336344	0	0
T17	4826304	4823448	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	19934096	19918640	0	0
T2	4584272	4561480	0	0
T3	2449608	2447760	0	0
T11	5766992	5766656	0	0
T12	4304328	4299568	0	0
T13	2534952	2531536	0	0
T14	570528	567672	0	0
T15	2885960	2882600	0	0
T16	6342784	6336344	0	0
T17	4826304	4823448	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	116486428	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	116486428	0	0
T1	355966	155143	0	0
T2	81862	44420	0	0
T3	43743	15946	0	0
T11	102982	100219	0	0
T12	76863	21115	0	0
T13	45267	22084	0	0
T14	10188	9819	0	0
T15	51535	49676	0	0
T16	113264	54679	0	0
T17	86184	35843	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	85457893	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	85457893	0	0
T1	355966	84001	0	0
T2	81862	25139	0	0
T3	43743	5585	0	0
T11	102982	8740	0	0
T12	76863	14551	0	0
T13	45267	5837	0	0
T14	10188	5038	0	0
T15	51535	634	0	0
T16	113264	34430	0	0
T17	86184	33726	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1522162	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1522162	0	0
T1	355966	2303	0	0
T2	81862	895	0	0
T3	43743	326	0	0
T11	102982	402	0	0
T12	76863	778	0	0
T13	45267	475	0	0
T14	10188	113	0	0
T15	51535	24	0	0
T16	113264	293	0	0
T17	86184	2326	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2887586	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2887586	0	0
T1	355966	2028	0	0
T2	81862	780	0	0
T3	43743	188	0	0
T11	102982	1241	0	0
T12	76863	548	0	0
T13	45267	185	0	0
T14	10188	113	0	0
T15	51535	4	0	0
T16	113264	225	0	0
T17	86184	2240	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1489636	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1489636	0	0
T1	355966	2281	0	0
T2	81862	747	0	0
T3	43743	373	0	0
T11	102982	299	0	0
T12	76863	644	0	0
T13	45267	509	0	0
T14	10188	120	0	0
T15	51535	12	0	0
T16	113264	240	0	0
T17	86184	2099	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3145082	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3145082	0	0
T1	355966	1775	0	0
T2	81862	784	0	0
T3	43743	212	0	0
T11	102982	66	0	0
T12	76863	520	0	0
T13	45267	217	0	0
T14	10188	120	0	0
T15	51535	3	0	0
T16	113264	159	0	0
T17	86184	2097	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1553053	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1553053	0	0
T1	355966	3999	0	0
T2	81862	691	0	0
T3	43743	432	0	0
T11	102982	325	0	0
T12	76863	680	0	0
T13	45267	432	0	0
T14	10188	138	0	0
T15	51535	30	0	0
T16	113264	266	0	0
T17	86184	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3128408	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3128408	0	0
T1	355966	3485	0	0
T2	81862	738	0	0
T3	43743	239	0	0
T11	102982	71	0	0
T12	76863	500	0	0
T13	45267	144	0	0
T14	10188	138	0	0
T15	51535	5	0	0
T16	113264	218	0	0
T17	86184	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1544619	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1544619	0	0
T1	355966	8554	0	0
T2	81862	676	0	0
T3	43743	349	0	0
T11	102982	233	0	0
T12	76863	625	0	0
T13	45267	570	0	0
T14	10188	110	0	0
T15	51535	3	0	0
T16	113264	203	0	0
T17	86184	1979	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2725245	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2725245	0	0
T1	355966	6597	0	0
T2	81862	742	0	0
T3	43743	179	0	0
T11	102982	56	0	0
T12	76863	560	0	0
T13	45267	207	0	0
T14	10188	110	0	0
T15	51535	2	0	0
T16	113264	141	0	0
T17	86184	1920	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1501984	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1501984	0	0
T1	355966	2211	0	0
T2	81862	537	0	0
T3	43743	439	0	0
T11	102982	393	0	0
T12	76863	584	0	0
T13	45267	614	0	0
T14	10188	127	0	0
T15	51535	21	0	0
T16	113264	221	0	0
T17	86184	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3141414	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3141414	0	0
T1	355966	1972	0	0
T2	81862	588	0	0
T3	43743	168	0	0
T11	102982	536	0	0
T12	76863	480	0	0
T13	45267	185	0	0
T14	10188	127	0	0
T15	51535	7	0	0
T16	113264	216	0	0
T17	86184	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1490238	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1490238	0	0
T1	355966	3922	0	0
T2	81862	764	0	0
T3	43743	416	0	0
T11	102982	340	0	0
T12	76863	687	0	0
T13	45267	591	0	0
T14	10188	139	0	0
T15	51535	18	0	0
T16	113264	242	0	0
T17	86184	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3141438	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3141438	0	0
T1	355966	3234	0	0
T2	81862	911	0	0
T3	43743	192	0	0
T11	102982	68	0	0
T12	76863	550	0	0
T13	45267	288	0	0
T14	10188	139	0	0
T15	51535	3	0	0
T16	113264	209	0	0
T17	86184	117	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1574749	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1574749	0	0
T1	355966	2318	0	0
T2	81862	647	0	0
T3	43743	362	0	0
T11	102982	241	0	0
T12	76863	649	0	0
T13	45267	584	0	0
T14	10188	123	0	0
T15	51535	23	0	0
T16	113264	3474	0	0
T17	86184	2346	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	4669906	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	4669906	0	0
T1	355966	2053	0	0
T2	81862	593	0	0
T3	43743	137	0	0
T11	102982	63	0	0
T12	76863	545	0	0
T13	45267	180	0	0
T14	10188	123	0	0
T15	51535	6	0	0
T16	113264	3176	0	0
T17	86184	2274	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1497392	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1497392	0	0
T1	355966	2268	0	0
T2	81862	670	0	0
T3	43743	404	0	0
T11	102982	360	0	0
T12	76863	679	0	0
T13	45267	415	0	0
T14	10188	113	0	0
T15	51535	20	0	0
T16	113264	180	0	0
T17	86184	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2701722	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2701722	0	0
T1	355966	1857	0	0
T2	81862	775	0	0
T3	43743	148	0	0
T11	102982	79	0	0
T12	76863	606	0	0
T13	45267	193	0	0
T14	10188	113	0	0
T15	51535	5	0	0
T16	113264	162	0	0
T17	86184	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1562642	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1562642	0	0
T1	355966	2207	0	0
T2	81862	649	0	0
T3	43743	421	0	0
T11	102982	267	0	0
T12	76863	565	0	0
T13	45267	484	0	0
T14	10188	109	0	0
T15	51535	30	0	0
T16	113264	1791	0	0
T17	86184	2354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3187767	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3187767	0	0
T1	355966	1931	0	0
T2	81862	648	0	0
T3	43743	153	0	0
T11	102982	70	0	0
T12	76863	515	0	0
T13	45267	241	0	0
T14	10188	109	0	0
T15	51535	6	0	0
T16	113264	1512	0	0
T17	86184	2246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1589706	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1589706	0	0
T1	355966	2098	0	0
T2	81862	710	0	0
T3	43743	339	0	0
T11	102982	294	0	0
T12	76863	518	0	0
T13	45267	627	0	0
T14	10188	140	0	0
T15	51535	2	0	0
T16	113264	177	0	0
T17	86184	1782	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3253572	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3253572	0	0
T1	355966	1530	0	0
T2	81862	765	0	0
T3	43743	160	0	0
T11	102982	240	0	0
T12	76863	485	0	0
T13	45267	239	0	0
T14	10188	140	0	0
T15	51535	2	0	0
T16	113264	119	0	0
T17	86184	1825	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1558943	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1558943	0	0
T1	355966	2273	0	0
T2	81862	751	0	0
T3	43743	387	0	0
T11	102982	398	0	0
T12	76863	582	0	0
T13	45267	497	0	0
T14	10188	129	0	0
T15	51535	32	0	0
T16	113264	1964	0	0
T17	86184	1172	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2527192	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2527192	0	0
T1	355966	1785	0	0
T2	81862	615	0	0
T3	43743	125	0	0
T11	102982	491	0	0
T12	76863	503	0	0
T13	45267	223	0	0
T14	10188	129	0	0
T15	51535	6	0	0
T16	113264	2098	0	0
T17	86184	1608	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1598506	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1598506	0	0
T1	355966	4351	0	0
T2	81862	683	0	0
T3	43743	362	0	0
T11	102982	194	0	0
T12	76863	783	0	0
T13	45267	500	0	0
T14	10188	128	0	0
T15	51535	19	0	0
T16	113264	2566	0	0
T17	86184	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2803057	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2803057	0	0
T1	355966	3503	0	0
T2	81862	636	0	0
T3	43743	173	0	0
T11	102982	44	0	0
T12	76863	578	0	0
T13	45267	232	0	0
T14	10188	128	0	0
T15	51535	6	0	0
T16	113264	1916	0	0
T17	86184	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1594108	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1594108	0	0
T1	355966	4878	0	0
T2	81862	783	0	0
T3	43743	279	0	0
T11	102982	361	0	0
T12	76863	826	0	0
T13	45267	541	0	0
T14	10188	119	0	0
T15	51535	19	0	0
T16	113264	2448	0	0
T17	86184	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3415857	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3415857	0	0
T1	355966	3442	0	0
T2	81862	699	0	0
T3	43743	128	0	0
T11	102982	906	0	0
T12	76863	575	0	0
T13	45267	185	0	0
T14	10188	119	0	0
T15	51535	4	0	0
T16	113264	2042	0	0
T17	86184	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1592876	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1592876	0	0
T1	355966	4405	0	0
T2	81862	838	0	0
T3	43743	313	0	0
T11	102982	387	0	0
T12	76863	726	0	0
T13	45267	618	0	0
T14	10188	100	0	0
T15	51535	16	0	0
T16	113264	255	0	0
T17	86184	2210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2906440	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2906440	0	0
T1	355966	3375	0	0
T2	81862	916	0	0
T3	43743	167	0	0
T11	102982	782	0	0
T12	76863	593	0	0
T13	45267	267	0	0
T14	10188	100	0	0
T15	51535	4	0	0
T16	113264	212	0	0
T17	86184	2171	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1514941	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1514941	0	0
T1	355966	2408	0	0
T2	81862	664	0	0
T3	43743	298	0	0
T11	102982	359	0	0
T12	76863	640	0	0
T13	45267	499	0	0
T14	10188	121	0	0
T15	51535	26	0	0
T16	113264	2022	0	0
T17	86184	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2904078	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2904078	0	0
T1	355966	2007	0	0
T2	81862	702	0	0
T3	43743	143	0	0
T11	102982	89	0	0
T12	76863	481	0	0
T13	45267	194	0	0
T14	10188	121	0	0
T15	51535	4	0	0
T16	113264	1609	0	0
T17	86184	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1610390	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1610390	0	0
T1	355966	3500	0	0
T2	81862	615	0	0
T3	43743	439	0	0
T11	102982	363	0	0
T12	76863	469	0	0
T13	45267	526	0	0
T14	10188	101	0	0
T15	51535	33	0	0
T16	113264	1952	0	0
T17	86184	1244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3146191	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3146191	0	0
T1	355966	3085	0	0
T2	81862	631	0	0
T3	43743	177	0	0
T11	102982	83	0	0
T12	76863	446	0	0
T13	45267	277	0	0
T14	10188	101	0	0
T15	51535	8	0	0
T16	113264	1695	0	0
T17	86184	1687	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1535025	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1535025	0	0
T1	355966	8288	0	0
T2	81862	647	0	0
T3	43743	247	0	0
T11	102982	436	0	0
T12	76863	593	0	0
T13	45267	572	0	0
T14	10188	120	0	0
T15	51535	7	0	0
T16	113264	1950	0	0
T17	86184	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2666826	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2666826	0	0
T1	355966	5962	0	0
T2	81862	642	0	0
T3	43743	138	0	0
T11	102982	1164	0	0
T12	76863	580	0	0
T13	45267	221	0	0
T14	10188	120	0	0
T15	51535	3	0	0
T16	113264	1373	0	0
T17	86184	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1497989	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1497989	0	0
T1	355966	2183	0	0
T2	81862	678	0	0
T3	43743	282	0	0
T11	102982	232	0	0
T12	76863	541	0	0
T13	45267	551	0	0
T14	10188	119	0	0
T15	51535	14	0	0
T16	113264	1853	0	0
T17	86184	4401	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3054714	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3054714	0	0
T1	355966	1956	0	0
T2	81862	672	0	0
T3	43743	182	0	0
T11	102982	349	0	0
T12	76863	434	0	0
T13	45267	215	0	0
T14	10188	119	0	0
T15	51535	3	0	0
T16	113264	1737	0	0
T17	86184	4197	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1527469	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1527469	0	0
T1	355966	2496	0	0
T2	81862	2160	0	0
T3	43743	283	0	0
T11	102982	355	0	0
T12	76863	562	0	0
T13	45267	515	0	0
T14	10188	132	0	0
T15	51535	8	0	0
T16	113264	2511	0	0
T17	86184	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3357745	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3357745	0	0
T1	355966	1972	0	0
T2	81862	2016	0	0
T3	43743	157	0	0
T11	102982	79	0	0
T12	76863	490	0	0
T13	45267	189	0	0
T14	10188	132	0	0
T15	51535	3	0	0
T16	113264	1899	0	0
T17	86184	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1524107	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1524107	0	0
T1	355966	4321	0	0
T2	81862	471	0	0
T3	43743	350	0	0
T11	102982	374	0	0
T12	76863	544	0	0
T13	45267	466	0	0
T14	10188	136	0	0
T15	51535	18	0	0
T16	113264	2389	0	0
T17	86184	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3560782	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3560782	0	0
T1	355966	3333	0	0
T2	81862	625	0	0
T3	43743	137	0	0
T11	102982	851	0	0
T12	76863	533	0	0
T13	45267	211	0	0
T14	10188	136	0	0
T15	51535	4	0	0
T16	113264	1747	0	0
T17	86184	121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1544099	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1544099	0	0
T1	355966	4017	0	0
T2	81862	850	0	0
T3	43743	319	0	0
T11	102982	299	0	0
T12	76863	572	0	0
T13	45267	449	0	0
T14	10188	107	0	0
T15	51535	13	0	0
T16	113264	1839	0	0
T17	86184	2231	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2803135	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2803135	0	0
T1	355966	3071	0	0
T2	81862	769	0	0
T3	43743	137	0	0
T11	102982	70	0	0
T12	76863	404	0	0
T13	45267	168	0	0
T14	10188	107	0	0
T15	51535	531	0	0
T16	113264	1544	0	0
T17	86184	2067	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1586848	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1586848	0	0
T1	355966	2071	0	0
T2	81862	749	0	0
T3	43743	327	0	0
T11	102982	377	0	0
T12	76863	532	0	0
T13	45267	554	0	0
T14	10188	112	0	0
T15	51535	22	0	0
T16	113264	2230	0	0
T17	86184	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3368417	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3368417	0	0
T1	355966	1631	0	0
T2	81862	622	0	0
T3	43743	96	0	0
T11	102982	172	0	0
T12	76863	478	0	0
T13	45267	205	0	0
T14	10188	112	0	0
T15	51535	5	0	0
T16	113264	1734	0	0
T17	86184	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1529662	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1529662	0	0
T1	355966	3656	0	0
T2	81862	673	0	0
T3	43743	406	0	0
T11	102982	357	0	0
T12	76863	692	0	0
T13	45267	401	0	0
T14	10188	127	0	0
T15	51535	1	0	0
T16	113264	1694	0	0
T17	86184	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3596478	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3596478	0	0
T1	355966	3054	0	0
T2	81862	766	0	0
T3	43743	115	0	0
T11	102982	82	0	0
T12	76863	490	0	0
T13	45267	221	0	0
T14	10188	127	0	0
T15	51535	1	0	0
T16	113264	1536	0	0
T17	86184	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1544368	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1544368	0	0
T1	355966	2072	0	0
T2	81862	800	0	0
T3	43743	320	0	0
T11	102982	314	0	0
T12	76863	620	0	0
T13	45267	645	0	0
T14	10188	122	0	0
T15	51535	11	0	0
T16	113264	2224	0	0
T17	86184	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3529047	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3529047	0	0
T1	355966	1580	0	0
T2	81862	792	0	0
T3	43743	154	0	0
T11	102982	83	0	0
T12	76863	529	0	0
T13	45267	230	0	0
T14	10188	122	0	0
T15	51535	3	0	0
T16	113264	1897	0	0
T17	86184	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1523271	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1523271	0	0
T1	355966	2578	0	0
T2	81862	632	0	0
T3	43743	422	0	0
T11	102982	330	0	0
T12	76863	626	0	0
T13	45267	603	0	0
T14	10188	135	0	0
T15	51535	14	0	0
T16	113264	153	0	0
T17	86184	1307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	3453113	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	3453113	0	0
T1	355966	1860	0	0
T2	81862	660	0	0
T3	43743	187	0	0
T11	102982	71	0	0
T12	76863	502	0	0
T13	45267	274	0	0
T14	10188	135	0	0
T15	51535	3	0	0
T16	113264	140	0	0
T17	86184	1532	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1577117	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1577117	0	0
T1	355966	6043	0	0
T2	81862	609	0	0
T3	43743	398	0	0
T11	102982	327	0	0
T12	76863	613	0	0
T13	45267	513	0	0
T14	10188	118	0	0
T15	51535	0	0	0
T16	113264	1891	0	0
T17	86184	4607	0	0
T18	0	111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2788790	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2788790	0	0
T1	355966	4585	0	0
T2	81862	702	0	0
T3	43743	185	0	0
T11	102982	64	0	0
T12	76863	444	0	0
T13	45267	210	0	0
T14	10188	118	0	0
T15	51535	0	0	0
T16	113264	1429	0	0
T17	86184	4895	0	0
T18	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	1535726	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	1535726	0	0
T1	355966	2395	0	0
T2	81862	501	0	0
T3	43743	380	0	0
T11	102982	296	0	0
T12	76863	743	0	0
T13	45267	519	0	0
T14	10188	103	0	0
T15	51535	7	0	0
T16	113264	260	0	0
T17	86184	1881	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305535876	2647601	0	0
DepthKnown_A	305535876	305409366	0	0
RvalidKnown_A	305535876	305409366	0	0
WreadyKnown_A	305535876	305409366	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	2647601	0	0
T1	355966	1957	0	0
T2	81862	580	0	0
T3	43743	217	0	0
T11	102982	870	0	0
T12	76863	609	0	0
T13	45267	235	0	0
T14	10188	103	0	0
T15	51535	2	0	0
T16	113264	175	0	0
T17	86184	1838	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305535876	305409366	0	0
T1	355966	355690	0	0
T2	81862	81455	0	0
T3	43743	43710	0	0
T11	102982	102976	0	0
T12	76863	76778	0	0
T13	45267	45206	0	0
T14	10188	10137	0	0
T15	51535	51475	0	0
T16	113264	113149	0	0
T17	86184	86133	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0