Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1669462	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262997

1

T1

1788

T2

9

T3

240

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	653605	1			T1	4394		T2	27		T3	600
values[0x0]	625011	1			T1	4242		T2	5		T3	593
values[0x1]	653843	1			T1	4393		T2	35		T3	573

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1294449	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

638010

1

T1

4293

T2

26

T3

591

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7304	1			T1	39		T3	13		T16	9
valid_sources[0x01]	6812	1			T1	140		T3	5		T16	3
valid_sources[0x02]	7524	1			T1	58		T3	7		T17	1
valid_sources[0x03]	8361	1			T1	23		T3	5		T16	15
valid_sources[0x04]	7253	1			T1	13		T3	12		T16	15
valid_sources[0x05]	7726	1			T1	112		T3	6		T16	11
valid_sources[0x06]	8046	1			T1	35		T2	1		T3	7
valid_sources[0x07]	7578	1			T1	67		T3	4		T16	5
valid_sources[0x08]	7383	1			T1	18		T3	2		T16	5
valid_sources[0x09]	7542	1			T1	7		T2	1		T3	4
valid_sources[0x0a]	7429	1			T1	27		T3	3		T16	3
valid_sources[0x0b]	7349	1			T1	37		T3	5		T17	1
valid_sources[0x0c]	6702	1			T1	42		T3	7		T17	1
valid_sources[0x0d]	8340	1			T1	54		T3	7		T16	7
valid_sources[0x0e]	7380	1			T1	10		T3	8		T16	4
valid_sources[0x0f]	7450	1			T1	97		T2	1		T3	5
valid_sources[0x10]	8368	1			T1	19		T3	7		T16	10
valid_sources[0x11]	7353	1			T1	11		T3	6		T16	12
valid_sources[0x12]	6832	1			T1	3		T2	1		T3	7
valid_sources[0x13]	7514	1			T1	44		T3	10		T17	1
valid_sources[0x14]	7615	1			T1	49		T2	2		T3	10
valid_sources[0x15]	6988	1			T1	9		T3	2		T16	8
valid_sources[0x16]	7923	1			T1	22		T3	11		T16	7
valid_sources[0x17]	7151	1			T1	18		T3	5		T16	14
valid_sources[0x18]	8999	1			T1	17		T3	7		T16	12
valid_sources[0x19]	7985	1			T1	38		T2	1		T3	2
valid_sources[0x1a]	7127	1			T1	14		T3	4		T16	7
valid_sources[0x1b]	7043	1			T1	8		T3	7		T16	9
valid_sources[0x1c]	7219	1			T1	44		T3	11		T16	7
valid_sources[0x1d]	7392	1			T1	39		T3	12		T16	9
valid_sources[0x1e]	7557	1			T1	13		T3	9		T16	11
valid_sources[0x1f]	7362	1			T1	19		T2	2		T3	4
valid_sources[0x20]	7135	1			T1	31		T3	5		T16	11
valid_sources[0x21]	7495	1			T1	64		T3	3		T16	4
valid_sources[0x22]	7909	1			T1	64		T3	6		T16	18
valid_sources[0x23]	7260	1			T1	14		T3	8		T16	4
valid_sources[0x24]	7848	1			T1	60		T3	11		T17	2
valid_sources[0x25]	7569	1			T1	83		T3	8		T16	12
valid_sources[0x26]	7566	1			T1	5		T3	3		T16	18
valid_sources[0x27]	7411	1			T1	79		T3	10		T16	9
valid_sources[0x28]	6918	1			T1	21		T3	5		T16	9
valid_sources[0x29]	7532	1			T1	27		T3	12		T16	7
valid_sources[0x2a]	8606	1			T1	19		T2	1		T3	6
valid_sources[0x2b]	7728	1			T1	6		T3	10		T17	3
valid_sources[0x2c]	8198	1			T1	10		T2	1		T3	8
valid_sources[0x2d]	7009	1			T1	85		T3	3		T16	1
valid_sources[0x2e]	8550	1			T1	65		T2	1		T3	8
valid_sources[0x2f]	7963	1			T1	70		T3	7		T16	10
valid_sources[0x30]	7013	1			T1	73		T3	8		T17	1
valid_sources[0x31]	7588	1			T1	51		T3	6		T16	11
valid_sources[0x32]	7731	1			T1	10		T3	9		T16	11
valid_sources[0x33]	7954	1			T1	14		T2	1		T3	6
valid_sources[0x34]	6784	1			T1	42		T3	8		T16	15
valid_sources[0x35]	7515	1			T1	10		T3	5		T16	7
valid_sources[0x36]	7469	1			T1	62		T3	3		T16	13
valid_sources[0x37]	7548	1			T1	15		T3	6		T16	9
valid_sources[0x38]	7051	1			T1	14		T3	8		T17	4
valid_sources[0x39]	8085	1			T1	25		T3	11		T17	3
valid_sources[0x3a]	6834	1			T1	51		T2	1		T3	3
valid_sources[0x3b]	7055	1			T1	124		T2	1		T3	6
valid_sources[0x3c]	7529	1			T1	36		T3	6		T16	11
valid_sources[0x3d]	7455	1			T1	41		T3	14		T16	12
valid_sources[0x3e]	8657	1			T1	512		T2	1		T3	7
valid_sources[0x3f]	7460	1			T1	75		T3	7		T16	18
valid_sources[0x40]	7119	1			T1	78		T3	1		T16	13
valid_sources[0x41]	6976	1			T1	17		T3	10		T16	6
valid_sources[0x42]	8607	1			T1	43		T3	7		T16	10
valid_sources[0x43]	7316	1			T1	19		T2	1		T3	6
valid_sources[0x44]	7296	1			T1	24		T3	4		T16	10
valid_sources[0x45]	7518	1			T1	413		T2	1		T3	8
valid_sources[0x46]	6945	1			T1	51		T2	2		T3	8
valid_sources[0x47]	7515	1			T1	110		T3	8		T16	8
valid_sources[0x48]	6874	1			T1	45		T3	9		T16	10
valid_sources[0x49]	7138	1			T1	41		T3	9		T16	9
valid_sources[0x4a]	7794	1			T1	80		T3	8		T16	10
valid_sources[0x4b]	7287	1			T1	103		T2	1		T3	9
valid_sources[0x4c]	8991	1			T1	14		T2	2		T3	9
valid_sources[0x4d]	7295	1			T1	28		T3	6		T16	5
valid_sources[0x4e]	7538	1			T1	33		T3	5		T16	12
valid_sources[0x4f]	7449	1			T1	17		T3	4		T16	7
valid_sources[0x50]	8148	1			T1	192		T3	6		T16	8
valid_sources[0x51]	7056	1			T1	44		T2	1		T3	4
valid_sources[0x52]	7047	1			T1	24		T3	10		T16	5
valid_sources[0x53]	7008	1			T1	29		T3	7		T16	9
valid_sources[0x54]	6919	1			T1	52		T3	3		T16	7
valid_sources[0x55]	7302	1			T1	75		T3	7		T16	8
valid_sources[0x56]	8034	1			T1	84		T3	7		T17	3
valid_sources[0x57]	8303	1			T1	47		T2	2		T3	8
valid_sources[0x58]	6854	1			T1	10		T2	1		T3	7
valid_sources[0x59]	7779	1			T1	18		T3	4		T17	2
valid_sources[0x5a]	8140	1			T1	88		T3	9		T16	9
valid_sources[0x5b]	7177	1			T1	37		T2	2		T3	6
valid_sources[0x5c]	7180	1			T1	23		T3	6		T16	12
valid_sources[0x5d]	6901	1			T1	100		T3	5		T16	14
valid_sources[0x5e]	7568	1			T1	19		T3	4		T16	10
valid_sources[0x5f]	7439	1			T1	48		T3	6		T16	11
valid_sources[0x60]	7000	1			T1	17		T3	9		T16	15
valid_sources[0x61]	9281	1			T1	16		T3	8		T16	7
valid_sources[0x62]	7640	1			T1	8		T3	14		T16	14
valid_sources[0x63]	7177	1			T1	82		T3	3		T16	13
valid_sources[0x64]	6915	1			T1	177		T3	9		T16	8
valid_sources[0x65]	8137	1			T1	252		T3	4		T16	5
valid_sources[0x66]	8228	1			T1	60		T3	8		T16	11
valid_sources[0x67]	7130	1			T1	12		T3	12		T16	9
valid_sources[0x68]	8080	1			T1	155		T3	7		T17	9
valid_sources[0x69]	7107	1			T1	35		T3	3		T16	3
valid_sources[0x6a]	7539	1			T1	71		T3	12		T16	8
valid_sources[0x6b]	7956	1			T1	12		T3	11		T16	10
valid_sources[0x6c]	8178	1			T1	70		T3	3		T17	1
valid_sources[0x6d]	7425	1			T1	35		T3	9		T16	14
valid_sources[0x6e]	7321	1			T1	67		T3	15		T17	2
valid_sources[0x6f]	6725	1			T1	10		T2	1		T3	7
valid_sources[0x70]	7201	1			T1	43		T3	5		T16	12
valid_sources[0x71]	7697	1			T1	62		T3	6		T16	13
valid_sources[0x72]	7147	1			T1	60		T3	4		T16	11
valid_sources[0x73]	7643	1			T1	112		T3	10		T16	8
valid_sources[0x74]	8823	1			T1	426		T3	4		T16	17
valid_sources[0x75]	6872	1			T1	26		T3	10		T16	9
valid_sources[0x76]	7984	1			T1	18		T2	1		T3	4
valid_sources[0x77]	7975	1			T1	35		T3	9		T16	11
valid_sources[0x78]	6955	1			T1	92		T3	9		T16	12
valid_sources[0x79]	7784	1			T1	4		T3	4		T17	1
valid_sources[0x7a]	7538	1			T1	42		T3	7		T17	1
valid_sources[0x7b]	8189	1			T1	55		T3	7		T16	5
valid_sources[0x7c]	7711	1			T1	27		T2	1		T3	9
valid_sources[0x7d]	7701	1			T1	21		T3	7		T16	9
valid_sources[0x7e]	7928	1			T1	64		T3	5		T16	7
valid_sources[0x7f]	7413	1			T1	52		T3	8		T16	14
valid_sources[0x80]	6945	1			T1	11		T3	10		T16	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27668

1

T1

189

T2

4

T3

21

values[0x0]

all_enables

biggest_size

207579

1

T1

1402

T2

3

T3

192

values[0x1]

all_enables

biggest_size

27750

1

T1

197

T2

2

T3

27