Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	357070916	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	357070916	0	0
T1	19021632	335617	0	0
T2	2113552	40664	0	0
T3	199024	7038	0	0
T15	21502656	506312	0	0
T16	12865664	2028895	0	0
T17	9077880	230754	0	0
T18	33488	523	0	0
T19	2314368	34747	0	0
T20	11416440	218221	0	0
T21	24864	690	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	19021632	18958632	0	0
T2	2113552	2112880	0	0
T3	199024	198520	0	0
T15	21502656	21494928	0	0
T16	12865664	12865608	0	0
T17	9077880	9074912	0	0
T18	33488	30016	0	0
T19	2314368	2313920	0	0
T20	11416440	11414536	0	0
T21	24864	23968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	19021632	18958632	0	0
T2	2113552	2112880	0	0
T3	199024	198520	0	0
T15	21502656	21494928	0	0
T16	12865664	12865608	0	0
T17	9077880	9074912	0	0
T18	33488	30016	0	0
T19	2314368	2313920	0	0
T20	11416440	11414536	0	0
T21	24864	23968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	19021632	18958632	0	0
T2	2113552	2112880	0	0
T3	199024	198520	0	0
T15	21502656	21494928	0	0
T16	12865664	12865608	0	0
T17	9077880	9074912	0	0
T18	33488	30016	0	0
T19	2314368	2313920	0	0
T20	11416440	11414536	0	0
T21	24864	23968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	132040013	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	132040013	0	0
T1	339672	132844	0	0
T2	37742	18222	0	0
T3	3554	3460	0	0
T15	383976	183006	0	0
T16	229744	225457	0	0
T17	162105	97049	0	0
T18	598	205	0	0
T19	41328	8752	0	0
T20	203865	100528	0	0
T21	444	267	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	92967938	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	92967938	0	0
T1	339672	54847	0	0
T2	37742	5229	0	0
T3	3554	1766	0	0
T15	383976	124405	0	0
T16	229744	896355	0	0
T17	162105	45415	0	0
T18	598	106	0	0
T19	41328	8661	0	0
T20	203865	25266	0	0
T21	444	141	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1500636	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1500636	0	0
T1	339672	6361	0	0
T2	37742	428	0	0
T3	3554	33	0	0
T15	383976	4013	0	0
T16	229744	488	0	0
T17	162105	1891	0	0
T18	598	5	0	0
T19	41328	406	0	0
T20	203865	1712	0	0
T21	444	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3710273	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3710273	0	0
T1	339672	4414	0	0
T2	37742	225	0	0
T3	3554	33	0	0
T15	383976	4067	0	0
T16	229744	41571	0	0
T17	162105	1928	0	0
T18	598	5	0	0
T19	41328	420	0	0
T20	203865	1350	0	0
T21	444	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1529092	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1529092	0	0
T1	339672	6061	0	0
T2	37742	410	0	0
T3	3554	29	0	0
T15	383976	4506	0	0
T16	229744	376	0	0
T17	162105	2705	0	0
T18	598	3	0	0
T19	41328	341	0	0
T20	203865	2316	0	0
T21	444	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3863516	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3863516	0	0
T1	339672	3137	0	0
T2	37742	187	0	0
T3	3554	29	0	0
T15	383976	5052	0	0
T16	229744	30399	0	0
T17	162105	1733	0	0
T18	598	3	0	0
T19	41328	344	0	0
T20	203865	934	0	0
T21	444	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1506241	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1506241	0	0
T1	339672	2311	0	0
T2	37742	426	0	0
T3	3554	36	0	0
T15	383976	3165	0	0
T16	229744	367	0	0
T17	162105	1517	0	0
T18	598	6	0	0
T19	41328	198	0	0
T20	203865	459	0	0
T21	444	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3069927	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3069927	0	0
T1	339672	1557	0	0
T2	37742	171	0	0
T3	3554	36	0	0
T15	383976	3729	0	0
T16	229744	31189	0	0
T17	162105	1108	0	0
T18	598	6	0	0
T19	41328	221	0	0
T20	203865	141	0	0
T21	444	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1500490	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1500490	0	0
T1	339672	2146	0	0
T2	37742	450	0	0
T3	3554	36	0	0
T15	383976	7607	0	0
T16	229744	446	0	0
T17	162105	1132	0	0
T18	598	3	0	0
T19	41328	313	0	0
T20	203865	242	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3260707	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3260707	0	0
T1	339672	1181	0	0
T2	37742	217	0	0
T3	3554	36	0	0
T15	383976	7158	0	0
T16	229744	36587	0	0
T17	162105	433	0	0
T18	598	3	0	0
T19	41328	352	0	0
T20	203865	2	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1508175	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1508175	0	0
T1	339672	2070	0	0
T2	37742	296	0	0
T3	3554	32	0	0
T15	383976	10487	0	0
T16	229744	521	0	0
T17	162105	1273	0	0
T18	598	5	0	0
T19	41328	260	0	0
T20	203865	1069	0	0
T21	444	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3115628	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3115628	0	0
T1	339672	1279	0	0
T2	37742	178	0	0
T3	3554	32	0	0
T15	383976	10572	0	0
T16	229744	39021	0	0
T17	162105	1255	0	0
T18	598	5	0	0
T19	41328	325	0	0
T20	203865	193	0	0
T21	444	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1510970	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1510970	0	0
T1	339672	2298	0	0
T2	37742	436	0	0
T3	3554	39	0	0
T15	383976	5636	0	0
T16	229744	401	0	0
T17	162105	2145	0	0
T18	598	7	0	0
T19	41328	267	0	0
T20	203865	1725	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3813571	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3813571	0	0
T1	339672	1424	0	0
T2	37742	193	0	0
T3	3554	39	0	0
T15	383976	5294	0	0
T16	229744	27905	0	0
T17	162105	1491	0	0
T18	598	7	0	0
T19	41328	357	0	0
T20	203865	932	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1453068	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1453068	0	0
T1	339672	2186	0	0
T2	37742	519	0	0
T3	3554	24	0	0
T15	383976	3144	0	0
T16	229744	387	0	0
T17	162105	2281	0	0
T18	598	2	0	0
T19	41328	292	0	0
T20	203865	3298	0	0
T21	444	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3406978	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3406978	0	0
T1	339672	1304	0	0
T2	37742	163	0	0
T3	3554	24	0	0
T15	383976	3040	0	0
T16	229744	28884	0	0
T17	162105	1941	0	0
T18	598	2	0	0
T19	41328	251	0	0
T20	203865	534	0	0
T21	444	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1519416	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1519416	0	0
T1	339672	6759	0	0
T2	37742	435	0	0
T3	3554	23	0	0
T15	383976	1538	0	0
T16	229744	363	0	0
T17	162105	1003	0	0
T18	598	5	0	0
T19	41328	347	0	0
T20	203865	2038	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3283462	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3283462	0	0
T1	339672	4495	0	0
T2	37742	292	0	0
T3	3554	23	0	0
T15	383976	1449	0	0
T16	229744	34156	0	0
T17	162105	409	0	0
T18	598	5	0	0
T19	41328	316	0	0
T20	203865	1724	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1493484	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1493484	0	0
T1	339672	2389	0	0
T2	37742	503	0	0
T3	3554	45	0	0
T15	383976	1655	0	0
T16	229744	429	0	0
T17	162105	1616	0	0
T18	598	3	0	0
T19	41328	410	0	0
T20	203865	4143	0	0
T21	444	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3143437	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3143437	0	0
T1	339672	1296	0	0
T2	37742	172	0	0
T3	3554	45	0	0
T15	383976	1705	0	0
T16	229744	35463	0	0
T17	162105	3236	0	0
T18	598	3	0	0
T19	41328	356	0	0
T20	203865	1315	0	0
T21	444	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1539021	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1539021	0	0
T1	339672	4120	0	0
T2	37742	513	0	0
T3	3554	30	0	0
T15	383976	3863	0	0
T16	229744	374	0	0
T17	162105	1431	0	0
T18	598	2	0	0
T19	41328	296	0	0
T20	203865	2715	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3662895	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3662895	0	0
T1	339672	2041	0	0
T2	37742	226	0	0
T3	3554	30	0	0
T15	383976	3635	0	0
T16	229744	29881	0	0
T17	162105	1659	0	0
T18	598	2	0	0
T19	41328	260	0	0
T20	203865	1155	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1479851	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1479851	0	0
T1	339672	1964	0	0
T2	37742	496	0	0
T3	3554	29	0	0
T15	383976	3336	0	0
T16	229744	370	0	0
T17	162105	979	0	0
T18	598	2	0	0
T19	41328	319	0	0
T20	203865	2196	0	0
T21	444	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3160279	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3160279	0	0
T1	339672	1246	0	0
T2	37742	217	0	0
T3	3554	29	0	0
T15	383976	3861	0	0
T16	229744	33212	0	0
T17	162105	1212	0	0
T18	598	2	0	0
T19	41328	334	0	0
T20	203865	361	0	0
T21	444	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1537627	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1537627	0	0
T1	339672	5587	0	0
T2	37742	498	0	0
T3	3554	34	0	0
T15	383976	1744	0	0
T16	229744	347	0	0
T17	162105	1285	0	0
T18	598	5	0	0
T19	41328	305	0	0
T20	203865	3649	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3356960	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3356960	0	0
T1	339672	2760	0	0
T2	37742	227	0	0
T3	3554	34	0	0
T15	383976	1590	0	0
T16	229744	29487	0	0
T17	162105	1973	0	0
T18	598	5	0	0
T19	41328	256	0	0
T20	203865	1192	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1478837	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1478837	0	0
T1	339672	6052	0	0
T2	37742	541	0	0
T3	3554	31	0	0
T15	383976	1743	0	0
T16	229744	384	0	0
T17	162105	1462	0	0
T18	598	5	0	0
T19	41328	346	0	0
T20	203865	1636	0	0
T21	444	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3295023	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3295023	0	0
T1	339672	4346	0	0
T2	37742	200	0	0
T3	3554	31	0	0
T15	383976	1577	0	0
T16	229744	34322	0	0
T17	162105	1750	0	0
T18	598	5	0	0
T19	41328	318	0	0
T20	203865	810	0	0
T21	444	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1439168	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1439168	0	0
T1	339672	2136	0	0
T2	37742	433	0	0
T3	3554	36	0	0
T15	383976	1713	0	0
T16	229744	360	0	0
T17	162105	2330	0	0
T18	598	3	0	0
T19	41328	362	0	0
T20	203865	3870	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3889484	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3889484	0	0
T1	339672	1159	0	0
T2	37742	183	0	0
T3	3554	36	0	0
T15	383976	1716	0	0
T16	229744	29753	0	0
T17	162105	2060	0	0
T18	598	3	0	0
T19	41328	309	0	0
T20	203865	2815	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1447639	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1447639	0	0
T1	339672	4334	0	0
T2	37742	507	0	0
T3	3554	24	0	0
T15	383976	1663	0	0
T16	229744	469	0	0
T17	162105	41	0	0
T18	598	1	0	0
T19	41328	470	0	0
T20	203865	2399	0	0
T21	444	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	4406108	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	4406108	0	0
T1	339672	2224	0	0
T2	37742	186	0	0
T3	3554	24	0	0
T15	383976	1630	0	0
T16	229744	37836	0	0
T17	162105	337	0	0
T18	598	1	0	0
T19	41328	455	0	0
T20	203865	275	0	0
T21	444	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1464626	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1464626	0	0
T1	339672	3253	0	0
T2	37742	405	0	0
T3	3554	30	0	0
T15	383976	1704	0	0
T16	229744	541	0	0
T17	162105	992	0	0
T18	598	3	0	0
T19	41328	258	0	0
T20	203865	4374	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3602176	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3602176	0	0
T1	339672	2348	0	0
T2	37742	232	0	0
T3	3554	30	0	0
T15	383976	1745	0	0
T16	229744	43266	0	0
T17	162105	1504	0	0
T18	598	3	0	0
T19	41328	225	0	0
T20	203865	109	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1504615	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1504615	0	0
T1	339672	5835	0	0
T2	37742	529	0	0
T3	3554	31	0	0
T15	383976	1605	0	0
T16	229744	497	0	0
T17	162105	1010	0	0
T18	598	8	0	0
T19	41328	392	0	0
T20	203865	2839	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3703883	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3703883	0	0
T1	339672	2973	0	0
T2	37742	161	0	0
T3	3554	31	0	0
T15	383976	1747	0	0
T16	229744	36310	0	0
T17	162105	1137	0	0
T18	598	8	0	0
T19	41328	294	0	0
T20	203865	823	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1505617	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1505617	0	0
T1	339672	2376	0	0
T2	37742	479	0	0
T3	3554	32	0	0
T15	383976	2001	0	0
T16	229744	385	0	0
T17	162105	1880	0	0
T18	598	3	0	0
T19	41328	269	0	0
T20	203865	4814	0	0
T21	444	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3833095	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3833095	0	0
T1	339672	1206	0	0
T2	37742	194	0	0
T3	3554	32	0	0
T15	383976	1820	0	0
T16	229744	32180	0	0
T17	162105	3499	0	0
T18	598	3	0	0
T19	41328	189	0	0
T20	203865	153	0	0
T21	444	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1490551	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1490551	0	0
T1	339672	4141	0	0
T2	37742	404	0	0
T3	3554	40	0	0
T15	383976	5284	0	0
T16	229744	374	0	0
T17	162105	2190	0	0
T18	598	5	0	0
T19	41328	264	0	0
T20	203865	1185	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	2643690	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	2643690	0	0
T1	339672	1938	0	0
T2	37742	292	0	0
T3	3554	40	0	0
T15	383976	5188	0	0
T16	229744	30146	0	0
T17	162105	1040	0	0
T18	598	5	0	0
T19	41328	297	0	0
T20	203865	1940	0	0
T21	444	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1488969	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1488969	0	0
T1	339672	2477	0	0
T2	37742	409	0	0
T3	3554	39	0	0
T15	383976	1698	0	0
T16	229744	409	0	0
T17	162105	2185	0	0
T18	598	4	0	0
T19	41328	309	0	0
T20	203865	2386	0	0
T21	444	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3457908	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3457908	0	0
T1	339672	1258	0	0
T2	37742	173	0	0
T3	3554	39	0	0
T15	383976	1754	0	0
T16	229744	34720	0	0
T17	162105	2834	0	0
T18	598	4	0	0
T19	41328	358	0	0
T20	203865	489	0	0
T21	444	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1483102	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1483102	0	0
T1	339672	2200	0	0
T2	37742	412	0	0
T3	3554	40	0	0
T15	383976	2131	0	0
T16	229744	422	0	0
T17	162105	2426	0	0
T18	598	3	0	0
T19	41328	342	0	0
T20	203865	2448	0	0
T21	444	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3131650	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3131650	0	0
T1	339672	1179	0	0
T2	37742	169	0	0
T3	3554	40	0	0
T15	383976	2056	0	0
T16	229744	36174	0	0
T17	162105	1547	0	0
T18	598	3	0	0
T19	41328	378	0	0
T20	203865	609	0	0
T21	444	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1455976	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1455976	0	0
T1	339672	2156	0	0
T2	37742	478	0	0
T3	3554	43	0	0
T15	383976	3606	0	0
T16	229744	420	0	0
T17	162105	354	0	0
T18	598	3	0	0
T19	41328	273	0	0
T20	203865	1543	0	0
T21	444	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3017741	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3017741	0	0
T1	339672	1075	0	0
T2	37742	215	0	0
T3	3554	43	0	0
T15	383976	4053	0	0
T16	229744	38341	0	0
T17	162105	2116	0	0
T18	598	3	0	0
T19	41328	279	0	0
T20	203865	781	0	0
T21	444	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1432183	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1432183	0	0
T1	339672	3516	0	0
T2	37742	341	0	0
T3	3554	25	0	0
T15	383976	3041	0	0
T16	229744	379	0	0
T17	162105	1410	0	0
T18	598	5	0	0
T19	41328	356	0	0
T20	203865	2269	0	0
T21	444	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	2680320	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	2680320	0	0
T1	339672	2102	0	0
T2	37742	70	0	0
T3	3554	25	0	0
T15	383976	3092	0	0
T16	229744	29623	0	0
T17	162105	1339	0	0
T18	598	5	0	0
T19	41328	414	0	0
T20	203865	914	0	0
T21	444	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1502740	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1502740	0	0
T1	339672	2565	0	0
T2	37742	439	0	0
T3	3554	33	0	0
T15	383976	5419	0	0
T16	229744	321	0	0
T17	162105	2427	0	0
T18	598	4	0	0
T19	41328	363	0	0
T20	203865	2194	0	0
T21	444	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3516412	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3516412	0	0
T1	339672	1318	0	0
T2	37742	145	0	0
T3	3554	33	0	0
T15	383976	5086	0	0
T16	229744	20715	0	0
T17	162105	2789	0	0
T18	598	4	0	0
T19	41328	296	0	0
T20	203865	517	0	0
T21	444	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1491599	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1491599	0	0
T1	339672	2463	0	0
T2	37742	504	0	0
T3	3554	44	0	0
T15	383976	1867	0	0
T16	229744	416	0	0
T17	162105	2305	0	0
T18	598	7	0	0
T19	41328	352	0	0
T20	203865	4007	0	0
T21	444	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3757453	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3757453	0	0
T1	339672	1490	0	0
T2	37742	212	0	0
T3	3554	44	0	0
T15	383976	1744	0	0
T16	229744	35417	0	0
T17	162105	1256	0	0
T18	598	7	0	0
T19	41328	403	0	0
T20	203865	2522	0	0
T21	444	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1437056	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1437056	0	0
T1	339672	2378	0	0
T2	37742	415	0	0
T3	3554	41	0	0
T15	383976	8330	0	0
T16	229744	364	0	0
T17	162105	110	0	0
T18	598	3	0	0
T19	41328	250	0	0
T20	203865	2325	0	0
T21	444	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	2780225	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	2780225	0	0
T1	339672	1375	0	0
T2	37742	157	0	0
T3	3554	41	0	0
T15	383976	7778	0	0
T16	229744	26516	0	0
T17	162105	715	0	0
T18	598	3	0	0
T19	41328	297	0	0
T20	203865	1297	0	0
T21	444	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	1477827	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	1477827	0	0
T1	339672	3774	0	0
T2	37742	278	0	0
T3	3554	27	0	0
T15	383976	7378	0	0
T16	229744	391	0	0
T17	162105	2495	0	0
T18	598	1	0	0
T19	41328	382	0	0
T20	203865	3310	0	0
T21	444	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317990482	3321588	0	0
DepthKnown_A	317990482	317866522	0	0
RvalidKnown_A	317990482	317866522	0	0
WreadyKnown_A	317990482	317866522	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	3321588	0	0
T1	339672	1893	0	0
T2	37742	172	0	0
T3	3554	27	0	0
T15	383976	6886	0	0
T16	229744	33008	0	0
T17	162105	3114	0	0
T18	598	1	0	0
T19	41328	288	0	0
T20	203865	1379	0	0
T21	444	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317990482	317866522	0	0
T1	339672	338547	0	0
T2	37742	37730	0	0
T3	3554	3545	0	0
T15	383976	383838	0	0
T16	229744	229743	0	0
T17	162105	162052	0	0
T18	598	536	0	0
T19	41328	41320	0	0
T20	203865	203831	0	0
T21	444	428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0