Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1858064	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

293449

1

T1

197

T2

309

T3

309

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	726999	1			T1	514		T2	683		T3	891
values[0x0]	696334	1			T1	508		T2	727		T3	816
values[0x1]	728180	1			T1	477		T2	725		T3	806

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1440192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

711321

1

T1

472

T2

752

T3

787

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8556	1			T1	7		T2	11		T3	8
valid_sources[0x01]	8277	1			T1	4		T2	14		T3	6
valid_sources[0x02]	8244	1			T1	4		T2	2		T3	10
valid_sources[0x03]	9051	1			T1	10		T2	7		T3	6
valid_sources[0x04]	7813	1			T1	4		T2	3		T3	11
valid_sources[0x05]	8073	1			T1	6		T2	13		T3	8
valid_sources[0x06]	9185	1			T1	5		T2	6		T3	9
valid_sources[0x07]	7885	1			T1	26		T2	11		T3	6
valid_sources[0x08]	8069	1			T1	4		T2	6		T3	5
valid_sources[0x09]	9023	1			T1	3		T2	4		T3	14
valid_sources[0x0a]	10196	1			T1	3		T2	10		T3	10
valid_sources[0x0b]	7745	1			T1	5		T2	1		T3	12
valid_sources[0x0c]	7787	1			T1	21		T2	15		T3	11
valid_sources[0x0d]	9332	1			T1	21		T2	5		T3	11
valid_sources[0x0e]	8139	1			T1	9		T2	6		T3	15
valid_sources[0x0f]	8252	1			T1	2		T2	7		T3	12
valid_sources[0x10]	9344	1			T1	4		T2	9		T3	12
valid_sources[0x11]	7830	1			T1	4		T2	3		T3	8
valid_sources[0x12]	8443	1			T1	9		T2	4		T3	9
valid_sources[0x13]	8328	1			T1	1		T2	9		T3	4
valid_sources[0x14]	9320	1			T1	8		T2	13		T3	6
valid_sources[0x15]	8124	1			T1	2		T2	9		T3	9
valid_sources[0x16]	8066	1			T1	5		T2	8		T3	11
valid_sources[0x17]	8226	1			T1	8		T2	12		T3	14
valid_sources[0x18]	9348	1			T1	3		T2	18		T3	16
valid_sources[0x19]	8346	1			T1	5		T2	1		T3	9
valid_sources[0x1a]	8103	1			T1	2		T2	12		T3	6
valid_sources[0x1b]	8751	1			T1	13		T2	11		T3	5
valid_sources[0x1c]	7751	1			T1	3		T2	5		T3	7
valid_sources[0x1d]	9756	1			T1	5		T2	8		T3	6
valid_sources[0x1e]	8215	1			T1	4		T2	6		T3	7
valid_sources[0x1f]	8621	1			T1	2		T2	7		T3	8
valid_sources[0x20]	8881	1			T1	4		T2	12		T3	9
valid_sources[0x21]	8891	1			T1	5		T2	2		T3	16
valid_sources[0x22]	7923	1			T1	4		T2	7		T3	8
valid_sources[0x23]	7887	1			T1	2		T2	7		T3	9
valid_sources[0x24]	9009	1			T1	8		T2	6		T3	9
valid_sources[0x25]	7900	1			T1	2		T2	4		T3	13
valid_sources[0x26]	8467	1			T1	6		T2	8		T3	15
valid_sources[0x27]	8165	1			T1	4		T2	11		T3	8
valid_sources[0x28]	8683	1			T1	4		T2	11		T3	8
valid_sources[0x29]	8169	1			T1	4		T2	2		T3	5
valid_sources[0x2a]	8377	1			T1	5		T2	10		T3	6
valid_sources[0x2b]	8476	1			T1	1		T2	9		T3	12
valid_sources[0x2c]	7696	1			T1	5		T2	9		T3	8
valid_sources[0x2d]	8744	1			T1	8		T2	12		T3	6
valid_sources[0x2e]	8207	1			T1	2		T2	3		T3	8
valid_sources[0x2f]	8342	1			T1	1		T2	7		T3	8
valid_sources[0x30]	8593	1			T1	4		T2	8		T3	3
valid_sources[0x31]	7768	1			T1	4		T2	10		T3	11
valid_sources[0x32]	7916	1			T1	13		T2	7		T3	11
valid_sources[0x33]	7957	1			T1	6		T2	11		T3	7
valid_sources[0x34]	9537	1			T1	5		T2	3		T3	8
valid_sources[0x35]	7974	1			T1	2		T2	9		T3	16
valid_sources[0x36]	8911	1			T1	1		T2	8		T3	6
valid_sources[0x37]	9176	1			T1	4		T2	7		T3	12
valid_sources[0x38]	9170	1			T1	10		T2	8		T3	5
valid_sources[0x39]	7990	1			T1	11		T2	11		T3	8
valid_sources[0x3a]	8007	1			T1	4		T2	6		T3	16
valid_sources[0x3b]	7879	1			T1	1		T2	8		T3	12
valid_sources[0x3c]	10055	1			T1	1		T2	9		T3	17
valid_sources[0x3d]	7842	1			T1	2		T2	8		T3	10
valid_sources[0x3e]	9200	1			T2	9		T3	5		T5	18
valid_sources[0x3f]	8286	1			T1	5		T2	19		T3	15
valid_sources[0x40]	8796	1			T1	2		T2	1		T3	12
valid_sources[0x41]	9247	1			T1	9		T2	22		T3	8
valid_sources[0x42]	7695	1			T1	4		T2	8		T3	7
valid_sources[0x43]	7927	1			T1	2		T2	4		T3	8
valid_sources[0x44]	7779	1			T1	3		T2	1		T3	5
valid_sources[0x45]	8828	1			T1	3		T2	10		T3	6
valid_sources[0x46]	7406	1			T1	9		T2	4		T3	13
valid_sources[0x47]	8884	1			T1	4		T2	4		T3	6
valid_sources[0x48]	8077	1			T1	4		T2	9		T3	9
valid_sources[0x49]	7771	1			T1	1		T2	5		T3	7
valid_sources[0x4a]	8431	1			T1	19		T2	8		T3	12
valid_sources[0x4b]	9169	1			T1	28		T2	4		T3	9
valid_sources[0x4c]	8256	1			T1	6		T2	19		T3	12
valid_sources[0x4d]	8867	1			T1	1		T2	22		T3	15
valid_sources[0x4e]	8807	1			T1	6		T2	6		T3	10
valid_sources[0x4f]	8432	1			T1	9		T2	13		T3	15
valid_sources[0x50]	8511	1			T1	7		T2	11		T3	10
valid_sources[0x51]	8145	1			T1	1		T2	6		T3	11
valid_sources[0x52]	8419	1			T1	9		T2	6		T3	9
valid_sources[0x53]	8293	1			T1	3		T2	11		T3	8
valid_sources[0x54]	7401	1			T1	3		T2	12		T3	14
valid_sources[0x55]	7778	1			T1	5		T2	13		T3	14
valid_sources[0x56]	8191	1			T2	7		T3	15		T5	19
valid_sources[0x57]	8598	1			T1	2		T2	7		T3	13
valid_sources[0x58]	8672	1			T1	2		T2	9		T3	11
valid_sources[0x59]	8086	1			T1	7		T2	10		T3	7
valid_sources[0x5a]	8651	1			T1	1		T2	11		T3	8
valid_sources[0x5b]	8680	1			T1	5		T2	3		T3	9
valid_sources[0x5c]	7944	1			T1	5		T2	10		T3	5
valid_sources[0x5d]	8154	1			T1	2		T2	3		T3	11
valid_sources[0x5e]	7388	1			T1	2		T2	5		T3	15
valid_sources[0x5f]	8178	1			T1	4		T2	5		T3	7
valid_sources[0x60]	8953	1			T1	3		T2	8		T3	10
valid_sources[0x61]	8056	1			T2	11		T3	12		T5	16
valid_sources[0x62]	8585	1			T1	4		T2	22		T3	12
valid_sources[0x63]	8724	1			T1	14		T2	2		T3	10
valid_sources[0x64]	7272	1			T1	4		T2	5		T3	10
valid_sources[0x65]	8537	1			T1	2		T2	3		T3	8
valid_sources[0x66]	7508	1			T1	6		T2	10		T3	13
valid_sources[0x67]	8425	1			T1	2		T2	6		T3	8
valid_sources[0x68]	8541	1			T1	8		T2	3		T3	15
valid_sources[0x69]	8865	1			T1	5		T2	13		T3	7
valid_sources[0x6a]	8878	1			T1	5		T2	4		T3	10
valid_sources[0x6b]	8054	1			T1	3		T2	11		T3	10
valid_sources[0x6c]	8716	1			T1	6		T2	10		T3	18
valid_sources[0x6d]	8714	1			T1	9		T2	6		T3	5
valid_sources[0x6e]	7683	1			T1	7		T2	7		T3	6
valid_sources[0x6f]	8771	1			T1	7		T2	10		T3	10
valid_sources[0x70]	8707	1			T1	3		T2	14		T3	12
valid_sources[0x71]	8230	1			T1	3		T2	10		T3	8
valid_sources[0x72]	8065	1			T1	3		T2	2		T3	14
valid_sources[0x73]	9173	1			T1	24		T2	15		T3	9
valid_sources[0x74]	8997	1			T1	6		T2	8		T3	10
valid_sources[0x75]	9318	1			T1	8		T2	5		T3	11
valid_sources[0x76]	9083	1			T1	6		T2	13		T3	12
valid_sources[0x77]	7822	1			T2	7		T3	7		T5	17
valid_sources[0x78]	8220	1			T1	12		T2	8		T3	13
valid_sources[0x79]	8651	1			T1	4		T2	10		T3	12
valid_sources[0x7a]	8283	1			T1	4		T2	3		T3	17
valid_sources[0x7b]	9184	1			T1	7		T2	9		T3	11
valid_sources[0x7c]	9021	1			T1	4		T2	6		T3	12
valid_sources[0x7d]	8365	1			T1	3		T2	10		T3	10
valid_sources[0x7e]	9199	1			T1	3		T2	9		T3	15
valid_sources[0x7f]	8106	1			T1	9		T2	11		T3	7
valid_sources[0x80]	9066	1			T1	5		T2	7		T3	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30755

1

T1

22

T2

31

T3

25

values[0x0]

all_enables

biggest_size

231811

1

T1

157

T2

245

T3

251

values[0x1]

all_enables

biggest_size

30883

1

T1

18

T2

33

T3

33