Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	352291850	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352291850	0	0
T1	2273936	38171	0	0
T2	251160	8507	0	0
T3	2554048	54142	0	0
T4	7507976	135675	0	0
T5	21757568	1826058	0	0
T6	852600	20164	0	0
T15	0	784	0	0
T16	51128	857	0	0
T17	11036592	2355004	0	0
T18	239680	7926	0	0
T19	21945616	1775695	0	0
T20	0	1448	0	0
T21	0	1094	0	0
T22	0	42343	0	0
T23	0	58814	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2273936	2198616	0	0
T2	251160	248864	0	0
T3	2554048	2553600	0	0
T4	7507976	7507472	0	0
T5	21757568	21757344	0	0
T6	852600	850640	0	0
T16	51128	46368	0	0
T17	11036592	11036424	0	0
T18	239680	237272	0	0
T19	21945616	21945504	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2273936	2198616	0	0
T2	251160	248864	0	0
T3	2554048	2553600	0	0
T4	7507976	7507472	0	0
T5	21757568	21757344	0	0
T6	852600	850640	0	0
T16	51128	46368	0	0
T17	11036592	11036424	0	0
T18	239680	237272	0	0
T19	21945616	21945504	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2273936	2198616	0	0
T2	251160	248864	0	0
T3	2554048	2553600	0	0
T4	7507976	7507472	0	0
T5	21757568	21757344	0	0
T6	852600	850640	0	0
T16	51128	46368	0	0
T17	11036592	11036424	0	0
T18	239680	237272	0	0
T19	21945616	21945504	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	125642684	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	125642684	0	0
T1	40606	16150	0	0
T2	4485	4180	0	0
T3	45608	16568	0	0
T4	134071	63578	0	0
T5	388528	22140	0	0
T6	15225	5563	0	0
T16	913	331	0	0
T17	197082	978543	0	0
T18	4280	1986	0	0
T19	391886	20726	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	94298192	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	94298192	0	0
T1	40606	5660	0	0
T2	4485	2135	0	0
T3	45608	10503	0	0
T4	134071	14959	0	0
T5	388528	162240	0	0
T6	15225	4520	0	0
T16	913	176	0	0
T17	197082	459174	0	0
T18	4280	1986	0	0
T19	391886	157829	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1432230	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1432230	0	0
T1	40606	259	0	0
T2	4485	48	0	0
T3	45608	0	0	0
T4	134071	417	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T16	913	3	0	0
T17	197082	16304	0	0
T18	4280	71	0	0
T19	391886	0	0	0
T20	0	36	0	0
T21	0	11	0	0
T22	0	1183	0	0
T23	0	28930	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3244364	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3244364	0	0
T1	40606	165	0	0
T2	4485	48	0	0
T3	45608	0	0	0
T4	134071	2	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T16	913	3	0	0
T17	197082	17415	0	0
T18	4280	71	0	0
T19	391886	0	0	0
T20	0	36	0	0
T21	0	3	0	0
T22	0	1443	0	0
T23	0	29884	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1459468	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1459468	0	0
T1	40606	225	0	0
T2	4485	41	0	0
T3	45608	0	0	0
T4	134071	1012	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	67	0	0
T16	913	8	0	0
T17	197082	20451	0	0
T18	4280	75	0	0
T19	391886	1270	0	0
T20	0	19	0	0
T21	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3958952	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3958952	0	0
T1	40606	82	0	0
T2	4485	41	0	0
T3	45608	0	0	0
T4	134071	455	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	56	0	0
T16	913	8	0	0
T17	197082	17488	0	0
T18	4280	75	0	0
T19	391886	102434	0	0
T20	0	19	0	0
T21	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1414583	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1414583	0	0
T1	40606	264	0	0
T2	4485	40	0	0
T3	45608	0	0	0
T4	134071	1896	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	10	0	0
T16	913	1	0	0
T17	197082	21010	0	0
T18	4280	67	0	0
T19	391886	3487	0	0
T20	0	20	0	0
T21	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3554059	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3554059	0	0
T1	40606	108	0	0
T2	4485	40	0	0
T3	45608	0	0	0
T4	134071	1124	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	6	0	0
T16	913	1	0	0
T17	197082	20483	0	0
T18	4280	67	0	0
T19	391886	275037	0	0
T20	0	20	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1460109	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1460109	0	0
T1	40606	1016	0	0
T2	4485	43	0	0
T3	45608	0	0	0
T4	134071	1668	0	0
T5	388528	1394	0	0
T6	15225	0	0	0
T16	913	10	0	0
T17	197082	17031	0	0
T18	4280	60	0	0
T19	391886	1340	0	0
T20	0	29	0	0
T21	0	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	4026017	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	4026017	0	0
T1	40606	541	0	0
T2	4485	43	0	0
T3	45608	0	0	0
T4	134071	1159	0	0
T5	388528	109534	0	0
T6	15225	0	0	0
T16	913	10	0	0
T17	197082	12920	0	0
T18	4280	60	0	0
T19	391886	112204	0	0
T20	0	29	0	0
T21	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1436004	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1436004	0	0
T1	40606	292	0	0
T2	4485	48	0	0
T3	45608	0	0	0
T4	134071	1847	0	0
T5	388528	1118	0	0
T6	15225	0	0	0
T16	913	4	0	0
T17	197082	17776	0	0
T18	4280	58	0	0
T19	391886	1373	0	0
T20	0	24	0	0
T21	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3664021	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3664021	0	0
T1	40606	180	0	0
T2	4485	48	0	0
T3	45608	0	0	0
T4	134071	736	0	0
T5	388528	86073	0	0
T6	15225	0	0	0
T16	913	4	0	0
T17	197082	15501	0	0
T18	4280	58	0	0
T19	391886	110534	0	0
T20	0	24	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1458550	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1458550	0	0
T1	40606	1201	0	0
T2	4485	44	0	0
T3	45608	3286	0	0
T4	134071	1277	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	36	0	0
T16	913	5	0	0
T17	197082	16504	0	0
T18	4280	72	0	0
T19	391886	0	0	0
T20	0	25	0	0
T21	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3412121	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3412121	0	0
T1	40606	508	0	0
T2	4485	44	0	0
T3	45608	2483	0	0
T4	134071	733	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	29	0	0
T16	913	5	0	0
T17	197082	15091	0	0
T18	4280	72	0	0
T19	391886	0	0	0
T20	0	25	0	0
T21	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1453342	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1453342	0	0
T1	40606	308	0	0
T2	4485	39	0	0
T3	45608	0	0	0
T4	134071	1743	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	13	0	0
T16	913	3	0	0
T17	197082	16700	0	0
T18	4280	78	0	0
T19	391886	0	0	0
T20	0	24	0	0
T21	0	37	0	0
T22	0	3354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3019793	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3019793	0	0
T1	40606	171	0	0
T2	4485	39	0	0
T3	45608	0	0	0
T4	134071	2086	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	16	0	0
T16	913	3	0	0
T17	197082	14491	0	0
T18	4280	78	0	0
T19	391886	0	0	0
T20	0	24	0	0
T21	0	7	0	0
T22	0	3755	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1437355	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1437355	0	0
T1	40606	240	0	0
T2	4485	30	0	0
T3	45608	0	0	0
T4	134071	3716	0	0
T5	388528	884	0	0
T6	15225	0	0	0
T16	913	7	0	0
T17	197082	19010	0	0
T18	4280	80	0	0
T19	391886	1003	0	0
T20	0	31	0	0
T21	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	2773086	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	2773086	0	0
T1	40606	130	0	0
T2	4485	30	0	0
T3	45608	0	0	0
T4	134071	1298	0	0
T5	388528	72685	0	0
T6	15225	0	0	0
T16	913	7	0	0
T17	197082	17123	0	0
T18	4280	80	0	0
T19	391886	73580	0	0
T20	0	31	0	0
T21	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1441504	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1441504	0	0
T1	40606	2048	0	0
T2	4485	36	0	0
T3	45608	0	0	0
T4	134071	1824	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T16	913	13	0	0
T17	197082	17100	0	0
T18	4280	75	0	0
T19	391886	1132	0	0
T20	0	21	0	0
T21	0	30	0	0
T22	0	4767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3584734	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3584734	0	0
T1	40606	1107	0	0
T2	4485	36	0	0
T3	45608	0	0	0
T4	134071	75	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T16	913	13	0	0
T17	197082	15679	0	0
T18	4280	75	0	0
T19	391886	90042	0	0
T20	0	21	0	0
T21	0	211	0	0
T22	0	5367	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1442554	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1442554	0	0
T1	40606	206	0	0
T2	4485	48	0	0
T3	45608	0	0	0
T4	134071	163	0	0
T5	388528	1393	0	0
T6	15225	0	0	0
T15	0	52	0	0
T16	913	11	0	0
T17	197082	16435	0	0
T18	4280	84	0	0
T19	391886	0	0	0
T20	0	24	0	0
T21	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3245332	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3245332	0	0
T1	40606	118	0	0
T2	4485	48	0	0
T3	45608	0	0	0
T4	134071	0	0	0
T5	388528	109288	0	0
T6	15225	0	0	0
T15	0	55	0	0
T16	913	11	0	0
T17	197082	12206	0	0
T18	4280	84	0	0
T19	391886	0	0	0
T20	0	24	0	0
T21	0	6	0	0
T22	0	2981	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1436899	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1436899	0	0
T1	40606	280	0	0
T2	4485	52	0	0
T3	45608	1604	0	0
T4	134071	306	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	6	0	0
T16	913	5	0	0
T17	197082	17299	0	0
T18	4280	89	0	0
T19	391886	0	0	0
T20	0	36	0	0
T21	0	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3048090	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3048090	0	0
T1	40606	129	0	0
T2	4485	52	0	0
T3	45608	1114	0	0
T4	134071	2	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	5	0	0
T16	913	5	0	0
T17	197082	15444	0	0
T18	4280	89	0	0
T19	391886	0	0	0
T20	0	36	0	0
T21	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1453217	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1453217	0	0
T1	40606	236	0	0
T2	4485	46	0	0
T3	45608	1923	0	0
T4	134071	559	0	0
T5	388528	1222	0	0
T6	15225	0	0	0
T16	913	9	0	0
T17	197082	17144	0	0
T18	4280	83	0	0
T19	391886	1060	0	0
T20	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3618872	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3618872	0	0
T1	40606	159	0	0
T2	4485	46	0	0
T3	45608	944	0	0
T4	134071	327	0	0
T5	388528	89906	0	0
T6	15225	0	0	0
T16	913	9	0	0
T17	197082	19299	0	0
T18	4280	83	0	0
T19	391886	88444	0	0
T20	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1491559	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1491559	0	0
T1	40606	256	0	0
T2	4485	36	0	0
T3	45608	0	0	0
T4	134071	904	0	0
T5	388528	2047	0	0
T6	15225	0	0	0
T15	0	10	0	0
T16	913	5	0	0
T17	197082	18021	0	0
T18	4280	87	0	0
T19	391886	0	0	0
T20	0	32	0	0
T21	0	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3770159	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3770159	0	0
T1	40606	147	0	0
T2	4485	36	0	0
T3	45608	0	0	0
T4	134071	130	0	0
T5	388528	161205	0	0
T6	15225	0	0	0
T15	0	15	0	0
T16	913	5	0	0
T17	197082	21022	0	0
T18	4280	87	0	0
T19	391886	0	0	0
T20	0	32	0	0
T21	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1440244	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1440244	0	0
T1	40606	166	0	0
T2	4485	40	0	0
T3	45608	0	0	0
T4	134071	1303	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	20	0	0
T16	913	6	0	0
T17	197082	11622	0	0
T18	4280	84	0	0
T19	391886	0	0	0
T20	0	31	0	0
T21	0	11	0	0
T22	0	5166	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3430661	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3430661	0	0
T1	40606	69	0	0
T2	4485	40	0	0
T3	45608	0	0	0
T4	134071	386	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	37	0	0
T16	913	6	0	0
T17	197082	14457	0	0
T18	4280	84	0	0
T19	391886	0	0	0
T20	0	31	0	0
T21	0	3	0	0
T22	0	5500	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1472669	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1472669	0	0
T1	40606	267	0	0
T2	4485	39	0	0
T3	45608	0	0	0
T4	134071	4373	0	0
T5	388528	1308	0	0
T6	15225	0	0	0
T16	913	14	0	0
T17	197082	15508	0	0
T18	4280	65	0	0
T19	391886	1059	0	0
T20	0	34	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3542623	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3542623	0	0
T1	40606	142	0	0
T2	4485	39	0	0
T3	45608	0	0	0
T4	134071	296	0	0
T5	388528	91354	0	0
T6	15225	0	0	0
T16	913	14	0	0
T17	197082	14676	0	0
T18	4280	65	0	0
T19	391886	99640	0	0
T20	0	34	0	0
T21	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1463219	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1463219	0	0
T1	40606	417	0	0
T2	4485	33	0	0
T3	45608	0	0	0
T4	134071	1326	0	0
T5	388528	0	0	0
T6	15225	1440	0	0
T16	913	5	0	0
T17	197082	17982	0	0
T18	4280	71	0	0
T19	391886	2075	0	0
T20	0	29	0	0
T21	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3649382	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3649382	0	0
T1	40606	192	0	0
T2	4485	33	0	0
T3	45608	0	0	0
T4	134071	617	0	0
T5	388528	0	0	0
T6	15225	1448	0	0
T16	913	5	0	0
T17	197082	18285	0	0
T18	4280	71	0	0
T19	391886	154245	0	0
T20	0	29	0	0
T21	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1457771	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1457771	0	0
T1	40606	221	0	0
T2	4485	23	0	0
T3	45608	0	0	0
T4	134071	939	0	0
T5	388528	0	0	0
T6	15225	2367	0	0
T16	913	8	0	0
T17	197082	17432	0	0
T18	4280	61	0	0
T19	391886	1139	0	0
T20	0	23	0	0
T21	0	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3357003	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3357003	0	0
T1	40606	95	0	0
T2	4485	23	0	0
T3	45608	0	0	0
T4	134071	67	0	0
T5	388528	0	0	0
T6	15225	1620	0	0
T16	913	8	0	0
T17	197082	19316	0	0
T18	4280	61	0	0
T19	391886	89225	0	0
T20	0	23	0	0
T21	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1442042	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1442042	0	0
T1	40606	278	0	0
T2	4485	47	0	0
T3	45608	0	0	0
T4	134071	1373	0	0
T5	388528	1999	0	0
T6	15225	0	0	0
T16	913	3	0	0
T17	197082	14196	0	0
T18	4280	74	0	0
T19	391886	0	0	0
T20	0	20	0	0
T21	0	34	0	0
T22	0	4192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3546809	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3546809	0	0
T1	40606	132	0	0
T2	4485	47	0	0
T3	45608	0	0	0
T4	134071	582	0	0
T5	388528	157704	0	0
T6	15225	0	0	0
T16	913	3	0	0
T17	197082	15142	0	0
T18	4280	74	0	0
T19	391886	0	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	0	4635	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1446581	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1446581	0	0
T1	40606	245	0	0
T2	4485	29	0	0
T3	45608	0	0	0
T4	134071	2237	0	0
T5	388528	2273	0	0
T6	15225	0	0	0
T15	0	47	0	0
T16	913	5	0	0
T17	197082	16330	0	0
T18	4280	69	0	0
T19	391886	0	0	0
T20	0	19	0	0
T21	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	2942474	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	2942474	0	0
T1	40606	104	0	0
T2	4485	29	0	0
T3	45608	0	0	0
T4	134071	705	0	0
T5	388528	191096	0	0
T6	15225	0	0	0
T15	0	69	0	0
T16	913	5	0	0
T17	197082	16420	0	0
T18	4280	69	0	0
T19	391886	0	0	0
T20	0	19	0	0
T21	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1462742	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1462742	0	0
T1	40606	240	0	0
T2	4485	39	0	0
T3	45608	1549	0	0
T4	134071	3216	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	12	0	0
T16	913	7	0	0
T17	197082	12690	0	0
T18	4280	61	0	0
T19	391886	0	0	0
T20	0	29	0	0
T21	0	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	4042914	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	4042914	0	0
T1	40606	111	0	0
T2	4485	39	0	0
T3	45608	1156	0	0
T4	134071	977	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	18	0	0
T16	913	7	0	0
T17	197082	11369	0	0
T18	4280	61	0	0
T19	391886	0	0	0
T20	0	29	0	0
T21	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1423242	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1423242	0	0
T1	40606	482	0	0
T2	4485	49	0	0
T3	45608	1191	0	0
T4	134071	2356	0	0
T5	388528	3524	0	0
T6	15225	0	0	0
T16	913	2	0	0
T17	197082	17526	0	0
T18	4280	72	0	0
T19	391886	0	0	0
T20	0	31	0	0
T21	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3616507	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3616507	0	0
T1	40606	241	0	0
T2	4485	49	0	0
T3	45608	1066	0	0
T4	134071	550	0	0
T5	388528	278805	0	0
T6	15225	0	0	0
T16	913	2	0	0
T17	197082	19048	0	0
T18	4280	72	0	0
T19	391886	0	0	0
T20	0	31	0	0
T21	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1416923	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1416923	0	0
T1	40606	265	0	0
T2	4485	41	0	0
T3	45608	0	0	0
T4	134071	1152	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	26	0	0
T16	913	3	0	0
T17	197082	11903	0	0
T18	4280	65	0	0
T19	391886	2519	0	0
T20	0	16	0	0
T21	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3283179	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3283179	0	0
T1	40606	135	0	0
T2	4485	41	0	0
T3	45608	0	0	0
T4	134071	585	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	30	0	0
T16	913	3	0	0
T17	197082	19490	0	0
T18	4280	65	0	0
T19	391886	202171	0	0
T20	0	16	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1414768	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1414768	0	0
T1	40606	281	0	0
T2	4485	46	0	0
T3	45608	2228	0	0
T4	134071	1166	0	0
T5	388528	2254	0	0
T6	15225	0	0	0
T16	913	7	0	0
T17	197082	19208	0	0
T18	4280	60	0	0
T19	391886	0	0	0
T20	0	34	0	0
T21	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3856227	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3856227	0	0
T1	40606	154	0	0
T2	4485	46	0	0
T3	45608	1109	0	0
T4	134071	748	0	0
T5	388528	174840	0	0
T6	15225	0	0	0
T16	913	7	0	0
T17	197082	20636	0	0
T18	4280	60	0	0
T19	391886	0	0	0
T20	0	34	0	0
T21	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1415750	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1415750	0	0
T1	40606	297	0	0
T2	4485	39	0	0
T3	45608	0	0	0
T4	134071	1795	0	0
T5	388528	1294	0	0
T6	15225	1755	0	0
T16	913	9	0	0
T17	197082	15256	0	0
T18	4280	78	0	0
T19	391886	0	0	0
T20	0	20	0	0
T21	0	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3526676	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3526676	0	0
T1	40606	184	0	0
T2	4485	39	0	0
T3	45608	0	0	0
T4	134071	613	0	0
T5	388528	98478	0	0
T6	15225	1451	0	0
T16	913	9	0	0
T17	197082	15864	0	0
T18	4280	78	0	0
T19	391886	0	0	0
T20	0	20	0	0
T21	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1437967	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1437967	0	0
T1	40606	267	0	0
T2	4485	39	0	0
T3	45608	0	0	0
T4	134071	1379	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	57	0	0
T16	913	6	0	0
T17	197082	17754	0	0
T18	4280	77	0	0
T19	391886	1173	0	0
T20	0	36	0	0
T21	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3616388	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3616388	0	0
T1	40606	127	0	0
T2	4485	39	0	0
T3	45608	0	0	0
T4	134071	222	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	63	0	0
T16	913	6	0	0
T17	197082	18920	0	0
T18	4280	77	0	0
T19	391886	92574	0	0
T20	0	36	0	0
T21	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1421350	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1421350	0	0
T1	40606	292	0	0
T2	4485	39	0	0
T3	45608	1063	0	0
T4	134071	457	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	16	0	0
T16	913	6	0	0
T17	197082	21159	0	0
T18	4280	74	0	0
T19	391886	0	0	0
T20	0	25	0	0
T21	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	3523070	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	3523070	0	0
T1	40606	139	0	0
T2	4485	39	0	0
T3	45608	900	0	0
T4	134071	303	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T15	0	13	0	0
T16	913	6	0	0
T17	197082	21572	0	0
T18	4280	74	0	0
T19	391886	0	0	0
T20	0	25	0	0
T21	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	1454292	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	1454292	0	0
T1	40606	306	0	0
T2	4485	42	0	0
T3	45608	3724	0	0
T4	134071	1775	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T16	913	10	0	0
T17	197082	19460	0	0
T18	4280	87	0	0
T19	391886	1162	0	0
T20	0	27	0	0
T21	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320335143	2510527	0	0
DepthKnown_A	320335143	320213021	0	0
RvalidKnown_A	320335143	320213021	0	0
WreadyKnown_A	320335143	320213021	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	2510527	0	0
T1	40606	136	0	0
T2	4485	42	0	0
T3	45608	1731	0	0
T4	134071	181	0	0
T5	388528	0	0	0
T6	15225	0	0	0
T16	913	10	0	0
T17	197082	19119	0	0
T18	4280	87	0	0
T19	391886	87218	0	0
T20	0	27	0	0
T21	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320335143	320213021	0	0
T1	40606	39261	0	0
T2	4485	4444	0	0
T3	45608	45600	0	0
T4	134071	134062	0	0
T5	388528	388524	0	0
T6	15225	15190	0	0
T16	913	828	0	0
T17	197082	197079	0	0
T18	4280	4237	0	0
T19	391886	391884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0