Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2001262	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

315126

1

T1

297

T2

317

T3

79

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	781405	1			T1	795		T2	786		T3	291
values[0x0]	753112	1			T1	773		T2	802		T3	53
values[0x1]	781871	1			T1	762		T2	815		T3	305

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1552969	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

763419

1

T1

728

T2

766

T3

246

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9382	1			T1	9		T2	6		T3	2
valid_sources[0x01]	8930	1			T2	8		T3	4		T4	7
valid_sources[0x02]	8990	1			T1	2		T2	20		T3	1
valid_sources[0x03]	8522	1			T1	3		T3	3		T4	11
valid_sources[0x04]	9448	1			T1	5		T2	3		T3	5
valid_sources[0x05]	8594	1			T2	7		T4	1		T14	18
valid_sources[0x06]	8709	1			T1	9		T2	5		T3	5
valid_sources[0x07]	8289	1			T1	9		T2	3		T4	8
valid_sources[0x08]	9188	1			T2	9		T3	2		T4	6
valid_sources[0x09]	9601	1			T1	14		T2	16		T3	3
valid_sources[0x0a]	9085	1			T1	5		T2	6		T3	3
valid_sources[0x0b]	9182	1			T1	6		T2	7		T3	4
valid_sources[0x0c]	9187	1			T1	13		T2	9		T3	4
valid_sources[0x0d]	8348	1			T2	3		T3	8		T4	9
valid_sources[0x0e]	9424	1			T1	16		T2	11		T3	3
valid_sources[0x0f]	8709	1			T2	6		T3	4		T13	1
valid_sources[0x10]	9224	1			T1	19		T2	10		T3	3
valid_sources[0x11]	8938	1			T2	9		T3	3		T4	22
valid_sources[0x12]	8556	1			T2	4		T3	3		T4	10
valid_sources[0x13]	8764	1			T1	4		T2	6		T4	3
valid_sources[0x14]	9077	1			T2	11		T3	4		T4	17
valid_sources[0x15]	9189	1			T1	6		T2	9		T3	4
valid_sources[0x16]	10358	1			T2	9		T3	2		T13	2
valid_sources[0x17]	8717	1			T1	13		T2	4		T3	1
valid_sources[0x18]	8804	1			T1	9		T2	10		T4	8
valid_sources[0x19]	8689	1			T1	15		T2	15		T3	1
valid_sources[0x1a]	9535	1			T1	34		T2	11		T3	4
valid_sources[0x1b]	8673	1			T1	10		T2	8		T3	4
valid_sources[0x1c]	9025	1			T2	7		T4	5		T13	2
valid_sources[0x1d]	9271	1			T1	3		T2	12		T3	2
valid_sources[0x1e]	9651	1			T1	33		T2	8		T3	1
valid_sources[0x1f]	9118	1			T2	7		T3	1		T13	1
valid_sources[0x20]	8496	1			T1	22		T2	6		T3	8
valid_sources[0x21]	8932	1			T2	9		T3	3		T4	8
valid_sources[0x22]	8473	1			T2	9		T3	2		T13	1
valid_sources[0x23]	8954	1			T1	4		T2	11		T3	1
valid_sources[0x24]	9310	1			T1	5		T2	8		T3	4
valid_sources[0x25]	9318	1			T1	11		T2	8		T3	2
valid_sources[0x26]	9493	1			T1	6		T2	9		T3	3
valid_sources[0x27]	8631	1			T2	7		T3	3		T4	2
valid_sources[0x28]	8095	1			T1	3		T2	9		T4	8
valid_sources[0x29]	9074	1			T2	8		T4	15		T14	14
valid_sources[0x2a]	9652	1			T2	10		T3	2		T4	3
valid_sources[0x2b]	9116	1			T1	80		T2	12		T3	1
valid_sources[0x2c]	9950	1			T1	7		T2	15		T3	2
valid_sources[0x2d]	9584	1			T1	27		T2	10		T4	3
valid_sources[0x2e]	10306	1			T1	8		T2	10		T3	1
valid_sources[0x2f]	9446	1			T2	8		T4	8		T14	17
valid_sources[0x30]	9110	1			T1	34		T2	6		T3	1
valid_sources[0x31]	8308	1			T2	14		T3	3		T4	6
valid_sources[0x32]	8745	1			T2	15		T3	1		T4	23
valid_sources[0x33]	9095	1			T2	7		T4	8		T13	1
valid_sources[0x34]	8671	1			T1	35		T2	9		T3	3
valid_sources[0x35]	8892	1			T1	13		T2	5		T3	1
valid_sources[0x36]	8648	1			T1	18		T2	7		T3	2
valid_sources[0x37]	8538	1			T2	7		T4	3		T14	17
valid_sources[0x38]	9619	1			T1	18		T2	6		T3	7
valid_sources[0x39]	8749	1			T2	11		T3	4		T4	6
valid_sources[0x3a]	9478	1			T2	11		T3	4		T4	4
valid_sources[0x3b]	8205	1			T2	6		T3	2		T4	7
valid_sources[0x3c]	9249	1			T2	14		T3	1		T4	3
valid_sources[0x3d]	9264	1			T2	5		T4	1		T13	1
valid_sources[0x3e]	9689	1			T1	16		T2	11		T3	2
valid_sources[0x3f]	10032	1			T1	2		T2	9		T3	2
valid_sources[0x40]	8589	1			T1	8		T2	12		T3	8
valid_sources[0x41]	8618	1			T2	16		T3	1		T13	1
valid_sources[0x42]	8606	1			T1	13		T2	14		T3	2
valid_sources[0x43]	9708	1			T2	5		T3	1		T4	3
valid_sources[0x44]	9834	1			T1	25		T2	9		T3	4
valid_sources[0x45]	9562	1			T1	51		T2	9		T3	3
valid_sources[0x46]	8637	1			T2	7		T3	2		T4	1
valid_sources[0x47]	8869	1			T1	32		T2	21		T3	1
valid_sources[0x48]	9520	1			T1	18		T2	10		T3	5
valid_sources[0x49]	9394	1			T1	40		T2	15		T4	2
valid_sources[0x4a]	9320	1			T1	13		T2	11		T3	5
valid_sources[0x4b]	8842	1			T1	8		T2	12		T3	2
valid_sources[0x4c]	8951	1			T2	9		T4	1		T14	18
valid_sources[0x4d]	8993	1			T1	7		T2	10		T3	7
valid_sources[0x4e]	8186	1			T2	19		T3	2		T14	19
valid_sources[0x4f]	9160	1			T2	14		T3	2		T4	5
valid_sources[0x50]	8344	1			T1	76		T2	11		T4	1
valid_sources[0x51]	9245	1			T2	13		T3	4		T4	11
valid_sources[0x52]	8957	1			T1	8		T2	7		T3	1
valid_sources[0x53]	8604	1			T2	16		T3	2		T13	1
valid_sources[0x54]	9477	1			T2	9		T3	3		T4	4
valid_sources[0x55]	9454	1			T1	6		T2	5		T3	2
valid_sources[0x56]	9214	1			T2	12		T3	1		T4	13
valid_sources[0x57]	9202	1			T1	4		T2	16		T3	4
valid_sources[0x58]	8874	1			T2	8		T3	4		T4	5
valid_sources[0x59]	9368	1			T2	6		T3	4		T4	7
valid_sources[0x5a]	9283	1			T1	73		T2	12		T3	6
valid_sources[0x5b]	8515	1			T1	10		T2	4		T3	4
valid_sources[0x5c]	9763	1			T2	5		T4	19		T14	20
valid_sources[0x5d]	9428	1			T1	7		T2	8		T4	6
valid_sources[0x5e]	9147	1			T1	6		T2	6		T3	2
valid_sources[0x5f]	9141	1			T1	80		T2	7		T3	1
valid_sources[0x60]	9395	1			T2	9		T3	3		T4	1
valid_sources[0x61]	8626	1			T1	18		T2	8		T3	5
valid_sources[0x62]	9076	1			T1	12		T2	11		T3	4
valid_sources[0x63]	9670	1			T2	13		T3	2		T4	9
valid_sources[0x64]	8395	1			T2	6		T3	2		T14	18
valid_sources[0x65]	8907	1			T1	41		T2	13		T3	4
valid_sources[0x66]	8858	1			T2	7		T3	2		T13	2
valid_sources[0x67]	9026	1			T2	8		T3	1		T4	11
valid_sources[0x68]	8305	1			T1	3		T2	11		T4	12
valid_sources[0x69]	8844	1			T1	2		T2	11		T3	2
valid_sources[0x6a]	9241	1			T2	20		T3	2		T4	13
valid_sources[0x6b]	9151	1			T2	10		T3	2		T4	7
valid_sources[0x6c]	9076	1			T1	51		T2	9		T3	3
valid_sources[0x6d]	9183	1			T1	8		T2	14		T3	2
valid_sources[0x6e]	8467	1			T1	8		T2	15		T3	1
valid_sources[0x6f]	8694	1			T1	8		T2	11		T3	4
valid_sources[0x70]	8504	1			T1	4		T2	1		T3	3
valid_sources[0x71]	8965	1			T2	5		T4	2		T14	18
valid_sources[0x72]	8942	1			T1	20		T2	12		T3	1
valid_sources[0x73]	9069	1			T1	20		T2	6		T3	1
valid_sources[0x74]	8666	1			T1	2		T2	11		T3	8
valid_sources[0x75]	8016	1			T1	7		T2	7		T3	1
valid_sources[0x76]	8882	1			T2	10		T3	8		T4	11
valid_sources[0x77]	9348	1			T2	13		T3	2		T4	17
valid_sources[0x78]	8760	1			T2	7		T4	2		T14	16
valid_sources[0x79]	9706	1			T2	13		T3	6		T4	7
valid_sources[0x7a]	10170	1			T1	41		T2	18		T3	2
valid_sources[0x7b]	8909	1			T2	4		T3	4		T4	2
valid_sources[0x7c]	8435	1			T1	10		T2	9		T3	3
valid_sources[0x7d]	9620	1			T1	22		T2	14		T3	3
valid_sources[0x7e]	9798	1			T2	8		T4	9		T14	20
valid_sources[0x7f]	8298	1			T1	32		T2	12		T3	4
valid_sources[0x80]	9320	1			T1	3		T2	18		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

33066

1

T1

25

T2

25

T3

25

values[0x0]

all_enables

biggest_size

249001

1

T1

238

T2

261

T3

28

values[0x1]

all_enables

biggest_size

33059

1

T1

34

T2

31

T3

26