Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	369207456	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	369207456	0	0
T1	6603632	144573	0	0
T2	282800	11793	0	0
T3	17299072	334173	0	0
T4	1563576	38250	0	0
T9	0	14073	0	0
T11	0	242448	0	0
T13	238168	4788	0	0
T14	22523704	1867464	0	0
T15	8765512	273440	0	0
T16	236544	4748	0	0
T17	26376	1160	0	0
T18	165536	3927	0	0
T19	0	43719	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6603632	6603576	0	0
T2	282800	280336	0	0
T3	17299072	17296048	0	0
T4	1563576	1562344	0	0
T13	238168	237104	0	0
T14	22523704	22523424	0	0
T15	8765512	8765008	0	0
T16	236544	235872	0	0
T17	26376	24752	0	0
T18	165536	163408	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6603632	6603576	0	0
T2	282800	280336	0	0
T3	17299072	17296048	0	0
T4	1563576	1562344	0	0
T13	238168	237104	0	0
T14	22523704	22523424	0	0
T15	8765512	8765008	0	0
T16	236544	235872	0	0
T17	26376	24752	0	0
T18	165536	163408	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6603632	6603576	0	0
T2	282800	280336	0	0
T3	17299072	17296048	0	0
T4	1563576	1562344	0	0
T13	238168	237104	0	0
T14	22523704	22523424	0	0
T15	8765512	8765008	0	0
T16	236544	235872	0	0
T17	26376	24752	0	0
T18	165536	163408	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	132140638	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	132140638	0	0
T1	117922	115141	0	0
T2	5050	4586	0	0
T3	308912	134456	0	0
T4	27921	10171	0	0
T13	4253	2180	0	0
T14	402209	21486	0	0
T15	156527	153517	0	0
T16	4224	2115	0	0
T17	471	290	0	0
T18	2956	1580	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	97476399	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	97476399	0	0
T1	117922	9794	0	0
T2	5050	2403	0	0
T3	308912	52544	0	0
T4	27921	8969	0	0
T13	4253	591	0	0
T14	402209	165863	0	0
T15	156527	59586	0	0
T16	4224	642	0	0
T17	471	290	0	0
T18	2956	790	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1650980	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1650980	0	0
T1	117922	337	0	0
T2	5050	99	0	0
T3	308912	4177	0	0
T4	27921	0	0	0
T9	0	251	0	0
T11	0	10438	0	0
T13	4253	59	0	0
T14	402209	0	0	0
T15	156527	45	0	0
T16	4224	83	0	0
T17	471	0	0	0
T18	2956	11	0	0
T19	0	2189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3490785	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3490785	0	0
T1	117922	352	0	0
T2	5050	99	0	0
T3	308912	1808	0	0
T4	27921	0	0	0
T9	0	297	0	0
T11	0	5050	0	0
T13	4253	16	0	0
T14	402209	0	0	0
T15	156527	2917	0	0
T16	4224	49	0	0
T17	471	0	0	0
T18	2956	29	0	0
T19	0	1241	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1585642	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1585642	0	0
T1	117922	415	0	0
T2	5050	85	0	0
T3	308912	1579	0	0
T4	27921	0	0	0
T9	0	357	0	0
T11	0	4948	0	0
T13	4253	61	0	0
T14	402209	0	0	0
T15	156527	27	0	0
T16	4224	45	0	0
T17	471	0	0	0
T18	2956	15	0	0
T19	0	1264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3432217	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3432217	0	0
T1	117922	686	0	0
T2	5050	85	0	0
T3	308912	896	0	0
T4	27921	0	0	0
T9	0	303	0	0
T11	0	2854	0	0
T13	4253	21	0	0
T14	402209	0	0	0
T15	156527	1621	0	0
T16	4224	32	0	0
T17	471	0	0	0
T18	2956	9	0	0
T19	0	969	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1634855	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1634855	0	0
T1	117922	331	0	0
T2	5050	91	0	0
T3	308912	4073	0	0
T4	27921	3191	0	0
T9	0	295	0	0
T11	0	10155	0	0
T13	4253	16	0	0
T14	402209	0	0	0
T15	156527	20	0	0
T16	4224	39	0	0
T17	471	0	0	0
T18	2956	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3641664	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3641664	0	0
T1	117922	1197	0	0
T2	5050	91	0	0
T3	308912	2910	0	0
T4	27921	3105	0	0
T9	0	229	0	0
T11	0	4726	0	0
T13	4253	13	0	0
T14	402209	0	0	0
T15	156527	1527	0	0
T16	4224	14	0	0
T17	471	0	0	0
T18	2956	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1641845	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1641845	0	0
T1	117922	302	0	0
T2	5050	95	0	0
T3	308912	3896	0	0
T4	27921	0	0	0
T9	0	235	0	0
T11	0	6221	0	0
T13	4253	7	0	0
T14	402209	0	0	0
T15	156527	56	0	0
T16	4224	47	0	0
T17	471	290	0	0
T18	2956	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3219433	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3219433	0	0
T1	117922	254	0	0
T2	5050	95	0	0
T3	308912	1774	0	0
T4	27921	0	0	0
T9	0	219	0	0
T11	0	2578	0	0
T13	4253	3	0	0
T14	402209	0	0	0
T15	156527	3629	0	0
T16	4224	16	0	0
T17	471	290	0	0
T18	2956	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1586841	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1586841	0	0
T1	117922	422	0	0
T2	5050	81	0	0
T3	308912	3615	0	0
T4	27921	0	0	0
T9	0	310	0	0
T11	0	6404	0	0
T13	4253	56	0	0
T14	402209	1141	0	0
T15	156527	27	0	0
T16	4224	66	0	0
T17	471	0	0	0
T18	2956	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3667041	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3667041	0	0
T1	117922	402	0	0
T2	5050	81	0	0
T3	308912	1850	0	0
T4	27921	0	0	0
T9	0	224	0	0
T11	0	2604	0	0
T13	4253	18	0	0
T14	402209	91024	0	0
T15	156527	1482	0	0
T16	4224	40	0	0
T17	471	0	0	0
T18	2956	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1539942	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1539942	0	0
T1	117922	394	0	0
T2	5050	85	0	0
T3	308912	1853	0	0
T4	27921	2178	0	0
T9	0	330	0	0
T11	0	14739	0	0
T13	4253	71	0	0
T14	402209	0	0	0
T15	156527	21	0	0
T16	4224	33	0	0
T17	471	0	0	0
T18	2956	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3662233	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3662233	0	0
T1	117922	87	0	0
T2	5050	85	0	0
T3	308912	888	0	0
T4	27921	1510	0	0
T9	0	239	0	0
T11	0	6990	0	0
T13	4253	38	0	0
T14	402209	0	0	0
T15	156527	1597	0	0
T16	4224	53	0	0
T17	471	0	0	0
T18	2956	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1600213	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1600213	0	0
T1	117922	354	0	0
T2	5050	84	0	0
T3	308912	5104	0	0
T4	27921	1770	0	0
T9	0	262	0	0
T11	0	5019	0	0
T13	4253	55	0	0
T14	402209	0	0	0
T15	156527	29	0	0
T16	4224	32	0	0
T17	471	0	0	0
T18	2956	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3794647	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3794647	0	0
T1	117922	92	0	0
T2	5050	84	0	0
T3	308912	2163	0	0
T4	27921	1309	0	0
T9	0	221	0	0
T11	0	2898	0	0
T13	4253	12	0	0
T14	402209	0	0	0
T15	156527	2566	0	0
T16	4224	18	0	0
T17	471	0	0	0
T18	2956	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1585560	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1585560	0	0
T1	117922	286	0	0
T2	5050	92	0	0
T3	308912	3816	0	0
T4	27921	0	0	0
T9	0	229	0	0
T11	0	5654	0	0
T13	4253	34	0	0
T14	402209	996	0	0
T15	156527	19	0	0
T16	4224	54	0	0
T17	471	0	0	0
T18	2956	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3691636	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3691636	0	0
T1	117922	1015	0	0
T2	5050	92	0	0
T3	308912	1969	0	0
T4	27921	0	0	0
T9	0	231	0	0
T11	0	3302	0	0
T13	4253	13	0	0
T14	402209	77816	0	0
T15	156527	2047	0	0
T16	4224	27	0	0
T17	471	0	0	0
T18	2956	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1600635	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1600635	0	0
T1	117922	434	0	0
T2	5050	87	0	0
T3	308912	3474	0	0
T4	27921	0	0	0
T9	0	348	0	0
T11	0	7283	0	0
T13	4253	33	0	0
T14	402209	0	0	0
T15	156527	29	0	0
T16	4224	68	0	0
T17	471	0	0	0
T18	2956	26	0	0
T19	0	3308	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3323058	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3323058	0	0
T1	117922	95	0	0
T2	5050	87	0	0
T3	308912	1466	0	0
T4	27921	0	0	0
T9	0	341	0	0
T11	0	3138	0	0
T13	4253	18	0	0
T14	402209	0	0	0
T15	156527	2233	0	0
T16	4224	35	0	0
T17	471	0	0	0
T18	2956	48	0	0
T19	0	2629	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1593423	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1593423	0	0
T1	117922	334	0	0
T2	5050	88	0	0
T3	308912	1715	0	0
T4	27921	0	0	0
T9	0	217	0	0
T11	0	2515	0	0
T13	4253	2	0	0
T14	402209	2263	0	0
T15	156527	20	0	0
T16	4224	34	0	0
T17	471	0	0	0
T18	2956	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3218286	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3218286	0	0
T1	117922	81	0	0
T2	5050	88	0	0
T3	308912	721	0	0
T4	27921	0	0	0
T9	0	229	0	0
T11	0	1085	0	0
T13	4253	4	0	0
T14	402209	169937	0	0
T15	156527	1102	0	0
T16	4224	32	0	0
T17	471	0	0	0
T18	2956	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1664717	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1664717	0	0
T1	117922	385	0	0
T2	5050	94	0	0
T3	308912	1807	0	0
T4	27921	0	0	0
T9	0	290	0	0
T11	0	2539	0	0
T13	4253	150	0	0
T14	402209	0	0	0
T15	156527	28	0	0
T16	4224	45	0	0
T17	471	0	0	0
T18	2956	11	0	0
T19	0	1264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	4636555	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	4636555	0	0
T1	117922	97	0	0
T2	5050	94	0	0
T3	308912	948	0	0
T4	27921	0	0	0
T9	0	285	0	0
T11	0	1187	0	0
T13	4253	36	0	0
T14	402209	0	0	0
T15	156527	889	0	0
T16	4224	11	0	0
T17	471	0	0	0
T18	2956	51	0	0
T19	0	3493	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1578309	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1578309	0	0
T1	117922	386	0	0
T2	5050	98	0	0
T3	308912	3234	0	0
T4	27921	0	0	0
T9	0	255	0	0
T11	0	8573	0	0
T13	4253	39	0	0
T14	402209	3708	0	0
T15	156527	7	0	0
T16	4224	52	0	0
T17	471	0	0	0
T18	2956	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	4207920	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	4207920	0	0
T1	117922	1218	0	0
T2	5050	98	0	0
T3	308912	1540	0	0
T4	27921	0	0	0
T9	0	249	0	0
T11	0	3849	0	0
T13	4253	24	0	0
T14	402209	268667	0	0
T15	156527	1299	0	0
T16	4224	15	0	0
T17	471	0	0	0
T18	2956	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1627280	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1627280	0	0
T1	117922	326	0	0
T2	5050	92	0	0
T3	308912	1734	0	0
T4	27921	1644	0	0
T9	0	393	0	0
T13	4253	75	0	0
T14	402209	2075	0	0
T15	156527	42	0	0
T16	4224	25	0	0
T17	471	0	0	0
T18	2956	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3570496	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3570496	0	0
T1	117922	363	0	0
T2	5050	92	0	0
T3	308912	880	0	0
T4	27921	1669	0	0
T9	0	305	0	0
T13	4253	46	0	0
T14	402209	153789	0	0
T15	156527	2089	0	0
T16	4224	8	0	0
T17	471	0	0	0
T18	2956	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1570693	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1570693	0	0
T1	117922	356	0	0
T2	5050	69	0	0
T3	308912	1933	0	0
T4	27921	0	0	0
T9	0	287	0	0
T11	0	4350	0	0
T13	4253	35	0	0
T14	402209	0	0	0
T15	156527	43	0	0
T16	4224	90	0	0
T17	471	0	0	0
T18	2956	10	0	0
T19	0	4398	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	2702033	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	2702033	0	0
T1	117922	1149	0	0
T2	5050	69	0	0
T3	308912	781	0	0
T4	27921	0	0	0
T9	0	203	0	0
T11	0	1739	0	0
T13	4253	29	0	0
T14	402209	0	0	0
T15	156527	3451	0	0
T16	4224	23	0	0
T17	471	0	0	0
T18	2956	19	0	0
T19	0	4154	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1614335	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1614335	0	0
T1	117922	307	0	0
T2	5050	92	0	0
T3	308912	3708	0	0
T4	27921	0	0	0
T9	0	288	0	0
T11	0	6205	0	0
T13	4253	25	0	0
T14	402209	0	0	0
T15	156527	24	0	0
T16	4224	37	0	0
T17	471	0	0	0
T18	2956	44	0	0
T19	0	2685	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3383288	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3383288	0	0
T1	117922	73	0	0
T2	5050	92	0	0
T3	308912	2281	0	0
T4	27921	0	0	0
T9	0	293	0	0
T11	0	2822	0	0
T13	4253	15	0	0
T14	402209	0	0	0
T15	156527	2769	0	0
T16	4224	12	0	0
T17	471	0	0	0
T18	2956	69	0	0
T19	0	3386	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1577001	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1577001	0	0
T1	117922	367	0	0
T2	5050	92	0	0
T3	308912	3269	0	0
T4	27921	0	0	0
T9	0	255	0	0
T11	0	8433	0	0
T13	4253	56	0	0
T14	402209	0	0	0
T15	156527	18	0	0
T16	4224	80	0	0
T17	471	0	0	0
T18	2956	49	0	0
T19	0	1770	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3204964	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3204964	0	0
T1	117922	97	0	0
T2	5050	92	0	0
T3	308912	2383	0	0
T4	27921	0	0	0
T9	0	184	0	0
T11	0	3864	0	0
T13	4253	12	0	0
T14	402209	0	0	0
T15	156527	2157	0	0
T16	4224	27	0	0
T17	471	0	0	0
T18	2956	14	0	0
T19	0	1253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1604821	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1604821	0	0
T1	117922	402	0	0
T2	5050	104	0	0
T3	308912	3748	0	0
T4	27921	1375	0	0
T9	0	290	0	0
T13	4253	68	0	0
T14	402209	1151	0	0
T15	156527	46	0	0
T16	4224	57	0	0
T17	471	0	0	0
T18	2956	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3597782	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3597782	0	0
T1	117922	88	0	0
T2	5050	104	0	0
T3	308912	1679	0	0
T4	27921	1359	0	0
T9	0	235	0	0
T13	4253	33	0	0
T14	402209	97363	0	0
T15	156527	4767	0	0
T16	4224	22	0	0
T17	471	0	0	0
T18	2956	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1657228	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1657228	0	0
T1	117922	408	0	0
T2	5050	88	0	0
T3	308912	3508	0	0
T4	27921	0	0	0
T9	0	264	0	0
T11	0	6950	0	0
T13	4253	37	0	0
T14	402209	996	0	0
T15	156527	25	0	0
T16	4224	31	0	0
T17	471	0	0	0
T18	2956	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3672116	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3672116	0	0
T1	117922	139	0	0
T2	5050	88	0	0
T3	308912	1652	0	0
T4	27921	0	0	0
T9	0	214	0	0
T11	0	2832	0	0
T13	4253	11	0	0
T14	402209	83067	0	0
T15	156527	1194	0	0
T16	4224	28	0	0
T17	471	0	0	0
T18	2956	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1604897	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1604897	0	0
T1	117922	355	0	0
T2	5050	90	0	0
T3	308912	4084	0	0
T4	27921	0	0	0
T9	0	218	0	0
T11	0	6815	0	0
T13	4253	45	0	0
T14	402209	0	0	0
T15	156527	11	0	0
T16	4224	59	0	0
T17	471	0	0	0
T18	2956	25	0	0
T19	0	1625	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3353565	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3353565	0	0
T1	117922	83	0	0
T2	5050	90	0	0
T3	308912	1948	0	0
T4	27921	0	0	0
T9	0	192	0	0
T11	0	3095	0	0
T13	4253	12	0	0
T14	402209	0	0	0
T15	156527	2167	0	0
T16	4224	16	0	0
T17	471	0	0	0
T18	2956	20	0	0
T19	0	967	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1591866	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1591866	0	0
T1	117922	312	0	0
T2	5050	96	0	0
T3	308912	2954	0	0
T4	27921	0	0	0
T9	0	274	0	0
T11	0	8190	0	0
T13	4253	78	0	0
T14	402209	1301	0	0
T15	156527	23	0	0
T16	4224	30	0	0
T17	471	0	0	0
T18	2956	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3100866	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3100866	0	0
T1	117922	93	0	0
T2	5050	96	0	0
T3	308912	1586	0	0
T4	27921	0	0	0
T9	0	238	0	0
T11	0	3556	0	0
T13	4253	36	0	0
T14	402209	111156	0	0
T15	156527	3659	0	0
T16	4224	20	0	0
T17	471	0	0	0
T18	2956	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1587545	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1587545	0	0
T1	117922	390	0	0
T2	5050	109	0	0
T3	308912	5754	0	0
T4	27921	0	0	0
T9	0	187	0	0
T11	0	4922	0	0
T13	4253	73	0	0
T14	402209	925	0	0
T15	156527	44	0	0
T16	4224	25	0	0
T17	471	0	0	0
T18	2956	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3731519	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3731519	0	0
T1	117922	262	0	0
T2	5050	109	0	0
T3	308912	3324	0	0
T4	27921	0	0	0
T9	0	226	0	0
T11	0	2127	0	0
T13	4253	34	0	0
T14	402209	71664	0	0
T15	156527	3977	0	0
T16	4224	13	0	0
T17	471	0	0	0
T18	2956	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1611503	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1611503	0	0
T1	117922	319	0	0
T2	5050	94	0	0
T3	308912	3556	0	0
T4	27921	0	0	0
T9	0	236	0	0
T11	0	6569	0	0
T13	4253	47	0	0
T14	402209	4297	0	0
T15	156527	13	0	0
T16	4224	20	0	0
T17	471	0	0	0
T18	2956	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	4231721	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	4231721	0	0
T1	117922	587	0	0
T2	5050	94	0	0
T3	308912	1782	0	0
T4	27921	0	0	0
T9	0	216	0	0
T11	0	2855	0	0
T13	4253	27	0	0
T14	402209	328896	0	0
T15	156527	2097	0	0
T16	4224	9	0	0
T17	471	0	0	0
T18	2956	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1577727	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1577727	0	0
T1	117922	383	0	0
T2	5050	92	0	0
T3	308912	9158	0	0
T4	27921	0	0	0
T9	0	273	0	0
T11	0	4210	0	0
T13	4253	34	0	0
T14	402209	0	0	0
T15	156527	23	0	0
T16	4224	64	0	0
T17	471	0	0	0
T18	2956	30	0	0
T19	0	155	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	2995156	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	2995156	0	0
T1	117922	929	0	0
T2	5050	92	0	0
T3	308912	5447	0	0
T4	27921	0	0	0
T9	0	246	0	0
T11	0	1775	0	0
T13	4253	9	0	0
T14	402209	0	0	0
T15	156527	2524	0	0
T16	4224	14	0	0
T17	471	0	0	0
T18	2956	18	0	0
T19	0	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1599211	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1599211	0	0
T1	117922	364	0	0
T2	5050	77	0	0
T3	308912	1642	0	0
T4	27921	0	0	0
T9	0	263	0	0
T11	0	4175	0	0
T13	4253	69	0	0
T14	402209	1333	0	0
T15	156527	35	0	0
T16	4224	85	0	0
T17	471	0	0	0
T18	2956	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3897342	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3897342	0	0
T1	117922	95	0	0
T2	5050	77	0	0
T3	308912	829	0	0
T4	27921	0	0	0
T9	0	278	0	0
T11	0	2129	0	0
T13	4253	9	0	0
T14	402209	105686	0	0
T15	156527	3008	0	0
T16	4224	44	0	0
T17	471	0	0	0
T18	2956	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1599133	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1599133	0	0
T1	117922	437	0	0
T2	5050	79	0	0
T3	308912	3939	0	0
T4	27921	0	0	0
T9	0	258	0	0
T11	0	2688	0	0
T13	4253	112	0	0
T14	402209	0	0	0
T15	156527	33	0	0
T16	4224	20	0	0
T17	471	0	0	0
T18	2956	26	0	0
T19	0	975	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3696377	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3696377	0	0
T1	117922	102	0	0
T2	5050	79	0	0
T3	308912	2609	0	0
T4	27921	0	0	0
T9	0	166	0	0
T11	0	1099	0	0
T13	4253	53	0	0
T14	402209	0	0	0
T15	156527	1350	0	0
T16	4224	9	0	0
T17	471	0	0	0
T18	2956	35	0	0
T19	0	1078	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1624620	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1624620	0	0
T1	117922	358	0	0
T2	5050	67	0	0
T3	308912	4945	0	0
T4	27921	0	0	0
T9	0	306	0	0
T11	0	12698	0	0
T13	4253	52	0	0
T14	402209	1298	0	0
T15	156527	7	0	0
T16	4224	44	0	0
T17	471	0	0	0
T18	2956	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3700841	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3700841	0	0
T1	117922	80	0	0
T2	5050	67	0	0
T3	308912	2561	0	0
T4	27921	0	0	0
T9	0	339	0	0
T11	0	6047	0	0
T13	4253	33	0	0
T14	402209	99566	0	0
T15	156527	249	0	0
T16	4224	32	0	0
T17	471	0	0	0
T18	2956	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	1605632	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	1605632	0	0
T1	117922	380	0	0
T2	5050	82	0	0
T3	308912	3548	0	0
T4	27921	0	0	0
T9	0	293	0	0
T11	0	5297	0	0
T13	4253	37	0	0
T14	402209	0	0	0
T15	156527	36	0	0
T16	4224	84	0	0
T17	471	0	0	0
T18	2956	29	0	0
T19	0	2261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	332180912	3450424	0	0
DepthKnown_A	332180912	332055827	0	0
RvalidKnown_A	332180912	332055827	0	0
WreadyKnown_A	332180912	332055827	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	3450424	0	0
T1	117922	78	0	0
T2	5050	82	0	0
T3	308912	2675	0	0
T4	27921	0	0	0
T9	0	207	0	0
T11	0	2257	0	0
T13	4253	16	0	0
T14	402209	0	0	0
T15	156527	1219	0	0
T16	4224	23	0	0
T17	471	0	0	0
T18	2956	22	0	0
T19	0	2531	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332180912	332055827	0	0
T1	117922	117921	0	0
T2	5050	5006	0	0
T3	308912	308858	0	0
T4	27921	27899	0	0
T13	4253	4234	0	0
T14	402209	402204	0	0
T15	156527	156518	0	0
T16	4224	4212	0	0
T17	471	442	0	0
T18	2956	2918	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0