Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1880144	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

297126

1

T1

8

T2

20

T3

104

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	735764	1			T1	40		T2	49		T3	227
values[0x0]	705520	1			T1	29		T2	38		T3	215
values[0x1]	735986	1			T1	32		T2	43		T3	236

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1458507	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

718763

1

T1

21

T2

44

T3

228

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8002	1			T1	1		T2	1		T3	1
valid_sources[0x01]	7965	1			T2	1		T3	4		T4	27
valid_sources[0x02]	8275	1			T1	1		T2	1		T4	13
valid_sources[0x03]	7536	1			T4	22		T22	3		T21	128
valid_sources[0x04]	7828	1			T1	1		T4	55		T21	96
valid_sources[0x05]	8110	1			T1	1		T4	38		T21	86
valid_sources[0x06]	9120	1			T4	42		T21	94		T18	9
valid_sources[0x07]	7995	1			T1	1		T4	29		T21	101
valid_sources[0x08]	8274	1			T2	1		T4	50		T22	1
valid_sources[0x09]	7831	1			T1	1		T4	37		T21	120
valid_sources[0x0a]	7814	1			T1	1		T2	2		T3	4
valid_sources[0x0b]	8661	1			T3	1		T4	39		T21	70
valid_sources[0x0c]	8059	1			T1	1		T4	26		T22	5
valid_sources[0x0d]	7870	1			T4	30		T21	103		T18	8
valid_sources[0x0e]	9078	1			T1	1		T4	23		T21	103
valid_sources[0x0f]	7901	1			T4	39		T22	2		T21	82
valid_sources[0x10]	8333	1			T4	9		T22	2		T21	84
valid_sources[0x11]	8275	1			T2	1		T4	37		T22	6
valid_sources[0x12]	9847	1			T3	5		T4	60		T22	5
valid_sources[0x13]	10076	1			T2	1		T4	32		T21	132
valid_sources[0x14]	9030	1			T3	10		T4	51		T21	127
valid_sources[0x15]	7923	1			T4	38		T21	163		T18	9
valid_sources[0x16]	9333	1			T2	2		T4	34		T22	3
valid_sources[0x17]	9086	1			T2	1		T4	59		T21	134
valid_sources[0x18]	7840	1			T3	7		T4	42		T22	1
valid_sources[0x19]	7358	1			T1	1		T4	39		T22	1
valid_sources[0x1a]	9245	1			T1	2		T3	5		T4	45
valid_sources[0x1b]	8229	1			T2	1		T3	16		T4	35
valid_sources[0x1c]	8679	1			T4	22		T21	75		T18	8
valid_sources[0x1d]	7397	1			T4	37		T21	118		T18	7
valid_sources[0x1e]	8248	1			T4	25		T21	114		T23	1
valid_sources[0x1f]	8201	1			T3	2		T4	25		T21	125
valid_sources[0x20]	8304	1			T4	34		T22	1		T21	71
valid_sources[0x21]	8448	1			T3	5		T4	45		T21	106
valid_sources[0x22]	9328	1			T4	24		T21	130		T18	8
valid_sources[0x23]	7327	1			T3	3		T4	45		T21	129
valid_sources[0x24]	8376	1			T1	1		T3	16		T4	27
valid_sources[0x25]	8376	1			T2	2		T4	81		T21	109
valid_sources[0x26]	7705	1			T1	4		T4	68		T22	1
valid_sources[0x27]	8871	1			T1	1		T2	1		T4	21
valid_sources[0x28]	9385	1			T2	2		T4	21		T22	2
valid_sources[0x29]	10186	1			T4	33		T22	1		T21	131
valid_sources[0x2a]	8539	1			T4	34		T21	95		T18	11
valid_sources[0x2b]	7655	1			T4	60		T21	106		T18	7
valid_sources[0x2c]	9644	1			T2	1		T4	33		T22	2
valid_sources[0x2d]	8164	1			T1	1		T4	81		T21	102
valid_sources[0x2e]	8463	1			T1	2		T3	5		T4	52
valid_sources[0x2f]	8573	1			T4	24		T21	89		T18	7
valid_sources[0x30]	8260	1			T4	17		T22	1		T21	113
valid_sources[0x31]	8565	1			T1	1		T2	1		T4	63
valid_sources[0x32]	8092	1			T4	32		T22	1		T21	100
valid_sources[0x33]	7857	1			T1	1		T3	2		T4	46
valid_sources[0x34]	7974	1			T1	1		T4	80		T22	1
valid_sources[0x35]	9241	1			T1	1		T2	1		T4	39
valid_sources[0x36]	7720	1			T4	60		T21	108		T23	2
valid_sources[0x37]	8787	1			T2	1		T4	49		T21	91
valid_sources[0x38]	8873	1			T4	28		T21	81		T18	9
valid_sources[0x39]	7684	1			T1	1		T4	27		T21	131
valid_sources[0x3a]	7482	1			T4	29		T21	108		T18	8
valid_sources[0x3b]	7822	1			T1	1		T2	2		T4	61
valid_sources[0x3c]	8455	1			T4	63		T21	107		T18	8
valid_sources[0x3d]	7934	1			T1	1		T4	29		T22	1
valid_sources[0x3e]	8967	1			T4	47		T22	1		T21	95
valid_sources[0x3f]	8524	1			T1	1		T2	2		T4	28
valid_sources[0x40]	9039	1			T1	1		T2	1		T4	79
valid_sources[0x41]	8664	1			T2	1		T4	20		T21	95
valid_sources[0x42]	7933	1			T1	1		T4	58		T22	1
valid_sources[0x43]	7603	1			T2	2		T3	23		T4	50
valid_sources[0x44]	7997	1			T4	33		T21	103		T18	8
valid_sources[0x45]	9265	1			T1	1		T4	25		T21	91
valid_sources[0x46]	8077	1			T4	41		T22	1		T21	110
valid_sources[0x47]	8166	1			T1	2		T2	1		T4	60
valid_sources[0x48]	7803	1			T1	2		T4	59		T22	1
valid_sources[0x49]	9170	1			T2	4		T4	19		T22	1
valid_sources[0x4a]	8116	1			T1	1		T4	67		T21	120
valid_sources[0x4b]	7723	1			T4	43		T21	102		T18	9
valid_sources[0x4c]	9697	1			T4	62		T21	86		T18	8
valid_sources[0x4d]	7113	1			T4	20		T21	95		T18	8
valid_sources[0x4e]	8540	1			T3	15		T4	47		T22	1
valid_sources[0x4f]	8000	1			T2	1		T4	49		T22	1
valid_sources[0x50]	7254	1			T4	26		T22	1		T21	74
valid_sources[0x51]	7495	1			T2	1		T3	4		T4	54
valid_sources[0x52]	7320	1			T4	54		T22	1		T21	82
valid_sources[0x53]	9271	1			T2	2		T4	77		T22	1
valid_sources[0x54]	8551	1			T2	4		T4	50		T21	114
valid_sources[0x55]	8173	1			T1	1		T2	1		T3	17
valid_sources[0x56]	7679	1			T1	1		T4	50		T21	116
valid_sources[0x57]	8160	1			T3	13		T4	26		T21	79
valid_sources[0x58]	8458	1			T1	1		T3	4		T4	45
valid_sources[0x59]	8475	1			T2	1		T4	20		T21	85
valid_sources[0x5a]	7693	1			T3	9		T4	55		T21	94
valid_sources[0x5b]	7484	1			T2	1		T3	77		T4	37
valid_sources[0x5c]	9782	1			T4	42		T21	131		T18	10
valid_sources[0x5d]	8114	1			T2	1		T4	41		T21	92
valid_sources[0x5e]	9496	1			T2	2		T4	59		T21	182
valid_sources[0x5f]	8964	1			T4	48		T21	133		T18	9
valid_sources[0x60]	7405	1			T3	18		T4	35		T21	84
valid_sources[0x61]	8509	1			T1	1		T4	72		T22	1
valid_sources[0x62]	8014	1			T1	1		T3	5		T4	33
valid_sources[0x63]	8534	1			T1	1		T2	1		T3	3
valid_sources[0x64]	9050	1			T4	35		T22	1		T21	98
valid_sources[0x65]	8127	1			T2	1		T4	19		T21	89
valid_sources[0x66]	12012	1			T2	1		T4	24		T21	91
valid_sources[0x67]	8529	1			T2	3		T4	51		T21	89
valid_sources[0x68]	9669	1			T3	18		T4	45		T21	130
valid_sources[0x69]	7260	1			T1	1		T4	39		T21	101
valid_sources[0x6a]	7506	1			T1	1		T3	8		T4	49
valid_sources[0x6b]	8393	1			T2	1		T4	38		T22	1
valid_sources[0x6c]	8131	1			T1	3		T4	66		T21	105
valid_sources[0x6d]	8892	1			T2	2		T4	39		T21	97
valid_sources[0x6e]	8446	1			T4	21		T21	114		T18	8
valid_sources[0x6f]	8362	1			T4	88		T21	102		T18	11
valid_sources[0x70]	9642	1			T4	49		T22	2		T21	94
valid_sources[0x71]	9149	1			T1	1		T4	45		T21	90
valid_sources[0x72]	9074	1			T4	66		T22	1		T21	96
valid_sources[0x73]	7643	1			T2	3		T3	20		T4	30
valid_sources[0x74]	9681	1			T1	2		T3	1		T4	54
valid_sources[0x75]	7842	1			T4	55		T21	88		T18	9
valid_sources[0x76]	9387	1			T1	2		T4	48		T22	1
valid_sources[0x77]	8956	1			T4	28		T21	108		T18	10
valid_sources[0x78]	8032	1			T1	3		T4	64		T21	95
valid_sources[0x79]	8158	1			T2	1		T4	47		T22	2
valid_sources[0x7a]	8178	1			T4	44		T22	1		T21	94
valid_sources[0x7b]	9367	1			T1	1		T4	33		T21	106
valid_sources[0x7c]	8408	1			T1	1		T3	10		T4	18
valid_sources[0x7d]	7216	1			T2	1		T4	19		T21	99
valid_sources[0x7e]	7286	1			T1	1		T2	1		T4	74
valid_sources[0x7f]	8468	1			T4	28		T22	2		T21	111
valid_sources[0x80]	8771	1			T1	1		T4	24		T21	98

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31106

1

T1

1

T2

6

T3

14

values[0x0]

all_enables

biggest_size

235057

1

T1

5

T2

14

T3

85

values[0x1]

all_enables

biggest_size

30963

1

T1

2

T3

5

T4

124