Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	348706447	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348706447	0	0
T1	5001750	167791	0	0
T2	24136	641	0	0
T3	833056	17019	0	0
T4	14454216	250093	0	0
T18	11389000	1544140	0	0
T21	2786392	125320	0	0
T22	5737312	95194	0	0
T23	1171408	17985	0	0
T24	13252624	1388124	0	0
T25	4356352	77950	0	0
T26	4928	779	0	0
T27	0	6643	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5187000	5186552	0	0
T2	24136	22568	0	0
T3	833056	832104	0	0
T4	14454216	14451136	0	0
T18	11389000	11388664	0	0
T21	2786392	2758168	0	0
T22	5737312	5731656	0	0
T23	1171408	1171072	0	0
T24	13252624	13252400	0	0
T25	4356352	4354672	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5187000	5186552	0	0
T2	24136	22568	0	0
T3	833056	832104	0	0
T4	14454216	14451136	0	0
T18	11389000	11388664	0	0
T21	2786392	2758168	0	0
T22	5737312	5731656	0	0
T23	1171408	1171072	0	0
T24	13252624	13252400	0	0
T25	4356352	4354672	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5187000	5186552	0	0
T2	24136	22568	0	0
T3	833056	832104	0	0
T4	14454216	14451136	0	0
T18	11389000	11388664	0	0
T21	2786392	2758168	0	0
T22	5737312	5731656	0	0
T23	1171408	1171072	0	0
T24	13252624	13252400	0	0
T25	4356352	4354672	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T18	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0
T23	56	56	0	0
T24	56	56	0	0
T25	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	135155383	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	135155383	0	0
T1	92625	91281	0	0
T2	431	251	0	0
T3	14876	6235	0	0
T4	258111	92955	0	0
T18	203375	9822	0	0
T21	49757	48707	0	0
T22	102452	32151	0	0
T23	20918	8011	0	0
T24	236654	101411	0	0
T25	77792	75848	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	87027763	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	87027763	0	0
T1	92625	38019	0	0
T2	431	130	0	0
T3	14876	5815	0	0
T4	258111	44040	0	0
T18	203375	762248	0	0
T21	49757	27214	0	0
T22	102452	18552	0	0
T23	20918	2968	0	0
T24	236654	283305	0	0
T25	77792	735	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1530007	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1530007	0	0
T1	92625	7	0	0
T2	431	8	0	0
T3	14876	112	0	0
T4	258111	1977	0	0
T18	203375	1246	0	0
T21	49757	969	0	0
T22	102452	1217	0	0
T23	20918	151	0	0
T24	236654	34871	0	0
T25	77792	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3375732	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3375732	0	0
T1	92625	693	0	0
T2	431	8	0	0
T3	14876	120	0	0
T4	258111	1144	0	0
T18	203375	91941	0	0
T21	49757	969	0	0
T22	102452	813	0	0
T23	20918	68	0	0
T24	236654	12470	0	0
T25	77792	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1469292	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1469292	0	0
T1	92625	30	0	0
T2	431	7	0	0
T3	14876	96	0	0
T4	258111	4107	0	0
T18	203375	0	0	0
T21	49757	1018	0	0
T22	102452	1002	0	0
T23	20918	192	0	0
T24	236654	28751	0	0
T25	77792	24	0	0
T26	0	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3089078	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3089078	0	0
T1	92625	2926	0	0
T2	431	7	0	0
T3	14876	104	0	0
T4	258111	2091	0	0
T18	203375	0	0	0
T21	49757	1018	0	0
T22	102452	870	0	0
T23	20918	65	0	0
T24	236654	8959	0	0
T25	77792	7	0	0
T26	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1502551	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1502551	0	0
T1	92625	7	0	0
T2	431	4	0	0
T3	14876	142	0	0
T4	258111	3724	0	0
T18	203375	1028	0	0
T21	49757	1267	0	0
T22	102452	869	0	0
T23	20918	140	0	0
T24	236654	28296	0	0
T25	77792	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	4217302	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	4217302	0	0
T1	92625	645	0	0
T2	431	4	0	0
T3	14876	116	0	0
T4	258111	2180	0	0
T18	203375	86016	0	0
T21	49757	1267	0	0
T22	102452	632	0	0
T23	20918	39	0	0
T24	236654	9912	0	0
T25	77792	604	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1520609	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1520609	0	0
T1	92625	4	0	0
T2	431	11	0	0
T3	14876	125	0	0
T4	258111	5246	0	0
T18	203375	2472	0	0
T21	49757	1320	0	0
T22	102452	1076	0	0
T23	20918	127	0	0
T24	236654	33282	0	0
T25	77792	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3604296	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3604296	0	0
T1	92625	612	0	0
T2	431	11	0	0
T3	14876	123	0	0
T4	258111	3687	0	0
T18	203375	189294	0	0
T21	49757	1320	0	0
T22	102452	683	0	0
T23	20918	75	0	0
T24	236654	10855	0	0
T25	77792	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1496895	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1496895	0	0
T1	92625	25	0	0
T2	431	2	0	0
T3	14876	78	0	0
T4	258111	2194	0	0
T18	203375	0	0	0
T21	49757	793	0	0
T22	102452	986	0	0
T23	20918	315	0	0
T24	236654	21862	0	0
T25	77792	23	0	0
T26	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2605623	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2605623	0	0
T1	92625	1060	0	0
T2	431	2	0	0
T3	14876	87	0	0
T4	258111	1477	0	0
T18	203375	0	0	0
T21	49757	793	0	0
T22	102452	753	0	0
T23	20918	139	0	0
T24	236654	9344	0	0
T25	77792	5	0	0
T26	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1524511	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1524511	0	0
T1	92625	30	0	0
T2	431	2	0	0
T3	14876	67	0	0
T4	258111	2501	0	0
T18	203375	0	0	0
T21	49757	1098	0	0
T22	102452	876	0	0
T23	20918	131	0	0
T24	236654	28937	0	0
T25	77792	28	0	0
T26	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3286590	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3286590	0	0
T1	92625	2837	0	0
T2	431	2	0	0
T3	14876	65	0	0
T4	258111	1412	0	0
T18	203375	0	0	0
T21	49757	1098	0	0
T22	102452	548	0	0
T23	20918	107	0	0
T24	236654	13236	0	0
T25	77792	5	0	0
T26	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1510150	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1510150	0	0
T1	92625	19	0	0
T2	431	5	0	0
T3	14876	72	0	0
T4	258111	1862	0	0
T18	203375	0	0	0
T21	49757	1364	0	0
T22	102452	902	0	0
T23	20918	169	0	0
T24	236654	27532	0	0
T25	77792	15	0	0
T26	0	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3085069	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3085069	0	0
T1	92625	744	0	0
T2	431	5	0	0
T3	14876	70	0	0
T4	258111	1252	0	0
T18	203375	0	0	0
T21	49757	1364	0	0
T22	102452	603	0	0
T23	20918	103	0	0
T24	236654	8283	0	0
T25	77792	4	0	0
T26	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1528874	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1528874	0	0
T1	92625	28	0	0
T2	431	6	0	0
T3	14876	99	0	0
T4	258111	2127	0	0
T18	203375	0	0	0
T21	49757	764	0	0
T22	102452	856	0	0
T23	20918	140	0	0
T24	236654	27855	0	0
T25	77792	44	0	0
T26	0	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3435990	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3435990	0	0
T1	92625	1703	0	0
T2	431	6	0	0
T3	14876	68	0	0
T4	258111	1160	0	0
T18	203375	0	0	0
T21	49757	764	0	0
T22	102452	589	0	0
T23	20918	80	0	0
T24	236654	13285	0	0
T25	77792	7	0	0
T26	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1517381	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1517381	0	0
T1	92625	16	0	0
T2	431	2	0	0
T3	14876	126	0	0
T4	258111	2003	0	0
T18	203375	0	0	0
T21	49757	815	0	0
T22	102452	807	0	0
T23	20918	177	0	0
T24	236654	27374	0	0
T25	77792	45	0	0
T26	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3625745	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3625745	0	0
T1	92625	425	0	0
T2	431	2	0	0
T3	14876	128	0	0
T4	258111	1186	0	0
T18	203375	0	0	0
T21	49757	815	0	0
T22	102452	568	0	0
T23	20918	78	0	0
T24	236654	9895	0	0
T25	77792	11	0	0
T26	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1532836	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1532836	0	0
T1	92625	16	0	0
T2	431	2	0	0
T3	14876	106	0	0
T4	258111	1964	0	0
T18	203375	0	0	0
T21	49757	800	0	0
T22	102452	944	0	0
T23	20918	129	0	0
T24	236654	22073	0	0
T25	77792	20	0	0
T26	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3474256	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3474256	0	0
T1	92625	1948	0	0
T2	431	2	0	0
T3	14876	98	0	0
T4	258111	1148	0	0
T18	203375	0	0	0
T21	49757	800	0	0
T22	102452	625	0	0
T23	20918	38	0	0
T24	236654	11249	0	0
T25	77792	5	0	0
T26	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1499434	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1499434	0	0
T1	92625	18	0	0
T2	431	4	0	0
T3	14876	195	0	0
T4	258111	3284	0	0
T18	203375	0	0	0
T21	49757	822	0	0
T22	102452	806	0	0
T23	20918	159	0	0
T24	236654	24934	0	0
T25	77792	10	0	0
T26	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2769929	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2769929	0	0
T1	92625	1563	0	0
T2	431	4	0	0
T3	14876	117	0	0
T4	258111	2456	0	0
T18	203375	0	0	0
T21	49757	822	0	0
T22	102452	631	0	0
T23	20918	112	0	0
T24	236654	9592	0	0
T25	77792	2	0	0
T26	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1493952	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1493952	0	0
T1	92625	15	0	0
T2	431	5	0	0
T3	14876	117	0	0
T4	258111	2131	0	0
T18	203375	1136	0	0
T21	49757	513	0	0
T22	102452	989	0	0
T23	20918	215	0	0
T24	236654	22011	0	0
T25	77792	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2925956	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2925956	0	0
T1	92625	1419	0	0
T2	431	5	0	0
T3	14876	86	0	0
T4	258111	1329	0	0
T18	203375	91104	0	0
T21	49757	513	0	0
T22	102452	686	0	0
T23	20918	79	0	0
T24	236654	7749	0	0
T25	77792	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1477335	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1477335	0	0
T1	92625	46	0	0
T2	431	4	0	0
T3	14876	40	0	0
T4	258111	1948	0	0
T18	203375	0	0	0
T21	49757	986	0	0
T22	102452	981	0	0
T23	20918	142	0	0
T24	236654	22491	0	0
T25	77792	16	0	0
T27	0	1551	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2748791	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2748791	0	0
T1	92625	3756	0	0
T2	431	4	0	0
T3	14876	63	0	0
T4	258111	1367	0	0
T18	203375	0	0	0
T21	49757	986	0	0
T22	102452	638	0	0
T23	20918	103	0	0
T24	236654	8401	0	0
T25	77792	4	0	0
T27	0	1889	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1487243	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1487243	0	0
T1	92625	7	0	0
T2	431	6	0	0
T3	14876	124	0	0
T4	258111	2046	0	0
T18	203375	0	0	0
T21	49757	509	0	0
T22	102452	882	0	0
T23	20918	153	0	0
T24	236654	32461	0	0
T25	77792	46	0	0
T26	0	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3057117	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3057117	0	0
T1	92625	282	0	0
T2	431	6	0	0
T3	14876	104	0	0
T4	258111	1232	0	0
T18	203375	0	0	0
T21	49757	509	0	0
T22	102452	696	0	0
T23	20918	68	0	0
T24	236654	11004	0	0
T25	77792	9	0	0
T26	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1598096	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1598096	0	0
T1	92625	17	0	0
T2	431	5	0	0
T3	14876	120	0	0
T4	258111	2202	0	0
T18	203375	0	0	0
T21	49757	1167	0	0
T22	102452	848	0	0
T23	20918	96	0	0
T24	236654	33886	0	0
T25	77792	25	0	0
T26	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3219562	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3219562	0	0
T1	92625	1395	0	0
T2	431	5	0	0
T3	14876	67	0	0
T4	258111	1144	0	0
T18	203375	0	0	0
T21	49757	1167	0	0
T22	102452	518	0	0
T23	20918	79	0	0
T24	236654	12170	0	0
T25	77792	4	0	0
T26	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1538048	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1538048	0	0
T1	92625	6	0	0
T2	431	5	0	0
T3	14876	74	0	0
T4	258111	2097	0	0
T18	203375	1332	0	0
T21	49757	722	0	0
T22	102452	1121	0	0
T23	20918	170	0	0
T24	236654	29181	0	0
T25	77792	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3841575	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3841575	0	0
T1	92625	231	0	0
T2	431	5	0	0
T3	14876	43	0	0
T4	258111	1261	0	0
T18	203375	102939	0	0
T21	49757	722	0	0
T22	102452	722	0	0
T23	20918	67	0	0
T24	236654	14332	0	0
T25	77792	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1472799	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1472799	0	0
T1	92625	9	0	0
T2	431	3	0	0
T3	14876	43	0	0
T4	258111	4103	0	0
T18	203375	0	0	0
T21	49757	540	0	0
T22	102452	883	0	0
T23	20918	189	0	0
T24	236654	19187	0	0
T25	77792	8	0	0
T26	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2951839	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2951839	0	0
T1	92625	1146	0	0
T2	431	3	0	0
T3	14876	58	0	0
T4	258111	2176	0	0
T18	203375	0	0	0
T21	49757	540	0	0
T22	102452	663	0	0
T23	20918	141	0	0
T24	236654	8993	0	0
T25	77792	3	0	0
T26	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1471877	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1471877	0	0
T1	92625	16	0	0
T2	431	6	0	0
T3	14876	95	0	0
T4	258111	1957	0	0
T18	203375	0	0	0
T21	49757	589	0	0
T22	102452	1027	0	0
T23	20918	127	0	0
T24	236654	26387	0	0
T25	77792	16	0	0
T26	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3788912	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3788912	0	0
T1	92625	1588	0	0
T2	431	6	0	0
T3	14876	133	0	0
T4	258111	1121	0	0
T18	203375	0	0	0
T21	49757	588	0	0
T22	102452	750	0	0
T23	20918	55	0	0
T24	236654	13751	0	0
T25	77792	3	0	0
T26	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1474934	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1474934	0	0
T2	431	7	0	0
T3	14876	133	0	0
T4	258111	2056	0	0
T18	203375	0	0	0
T21	49757	1093	0	0
T22	102452	957	0	0
T23	20918	251	0	0
T24	236654	18751	0	0
T25	77792	31	0	0
T26	2464	13	0	0
T27	0	1536	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2936104	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2936104	0	0
T2	431	7	0	0
T3	14876	118	0	0
T4	258111	1410	0	0
T18	203375	0	0	0
T21	49757	1093	0	0
T22	102452	707	0	0
T23	20918	114	0	0
T24	236654	9798	0	0
T25	77792	7	0	0
T26	2464	17	0	0
T27	0	1667	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1517102	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1517102	0	0
T1	92625	14	0	0
T2	431	7	0	0
T3	14876	97	0	0
T4	258111	2149	0	0
T18	203375	0	0	0
T21	49757	1148	0	0
T22	102452	863	0	0
T23	20918	182	0	0
T24	236654	25683	0	0
T25	77792	7	0	0
T26	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2784097	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2784097	0	0
T1	92625	859	0	0
T2	431	7	0	0
T3	14876	95	0	0
T4	258111	1381	0	0
T18	203375	0	0	0
T21	49757	1148	0	0
T22	102452	760	0	0
T23	20918	135	0	0
T24	236654	9384	0	0
T25	77792	2	0	0
T26	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1515042	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1515042	0	0
T1	92625	13	0	0
T2	431	6	0	0
T3	14876	55	0	0
T4	258111	4126	0	0
T18	203375	0	0	0
T21	49757	768	0	0
T22	102452	768	0	0
T23	20918	226	0	0
T24	236654	25936	0	0
T25	77792	41	0	0
T26	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3262638	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3262638	0	0
T1	92625	856	0	0
T2	431	6	0	0
T3	14876	57	0	0
T4	258111	2306	0	0
T18	203375	0	0	0
T21	49757	768	0	0
T22	102452	551	0	0
T23	20918	129	0	0
T24	236654	10078	0	0
T25	77792	8	0	0
T26	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1465799	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1465799	0	0
T1	92625	26	0	0
T2	431	4	0	0
T3	14876	76	0	0
T4	258111	2182	0	0
T18	203375	0	0	0
T21	49757	1073	0	0
T22	102452	1020	0	0
T23	20918	124	0	0
T24	236654	24697	0	0
T25	77792	36	0	0
T26	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3006903	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3006903	0	0
T1	92625	2669	0	0
T2	431	4	0	0
T3	14876	93	0	0
T4	258111	1388	0	0
T18	203375	0	0	0
T21	49757	1073	0	0
T22	102452	795	0	0
T23	20918	36	0	0
T24	236654	10325	0	0
T25	77792	11	0	0
T26	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1471172	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1471172	0	0
T1	92625	27	0	0
T2	431	2	0	0
T3	14876	114	0	0
T4	258111	2352	0	0
T18	203375	0	0	0
T21	49757	599	0	0
T22	102452	1122	0	0
T23	20918	202	0	0
T24	236654	30093	0	0
T25	77792	29	0	0
T26	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	3684482	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	3684482	0	0
T1	92625	2180	0	0
T2	431	2	0	0
T3	14876	118	0	0
T4	258111	1330	0	0
T18	203375	0	0	0
T21	49757	599	0	0
T22	102452	786	0	0
T23	20918	80	0	0
T24	236654	12495	0	0
T25	77792	7	0	0
T26	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1432832	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1432832	0	0
T1	92625	32	0	0
T2	431	2	0	0
T3	14876	81	0	0
T4	258111	1966	0	0
T18	203375	0	0	0
T21	49757	1073	0	0
T22	102452	920	0	0
T23	20918	178	0	0
T24	236654	26139	0	0
T25	77792	5	0	0
T26	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2754915	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2754915	0	0
T1	92625	2672	0	0
T2	431	2	0	0
T3	14876	63	0	0
T4	258111	1279	0	0
T18	203375	0	0	0
T21	49757	1073	0	0
T22	102452	711	0	0
T23	20918	84	0	0
T24	236654	11873	0	0
T25	77792	2	0	0
T26	0	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1474630	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1474630	0	0
T1	92625	18	0	0
T2	431	2	0	0
T3	14876	66	0	0
T4	258111	1814	0	0
T18	203375	0	0	0
T21	49757	937	0	0
T22	102452	1074	0	0
T23	20918	154	0	0
T24	236654	20228	0	0
T25	77792	3	0	0
T26	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2830874	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2830874	0	0
T1	92625	979	0	0
T2	431	2	0	0
T3	14876	90	0	0
T4	258111	1129	0	0
T18	203375	0	0	0
T21	49757	937	0	0
T22	102452	871	0	0
T23	20918	95	0	0
T24	236654	5341	0	0
T25	77792	2	0	0
T26	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1488790	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1488790	0	0
T1	92625	12	0	0
T2	431	8	0	0
T3	14876	78	0	0
T4	258111	2510	0	0
T18	203375	2608	0	0
T21	49757	943	0	0
T22	102452	1157	0	0
T23	20918	211	0	0
T24	236654	28667	0	0
T25	77792	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2984754	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2984754	0	0
T1	92625	1817	0	0
T2	431	8	0	0
T3	14876	91	0	0
T4	258111	1447	0	0
T18	203375	200954	0	0
T21	49757	943	0	0
T22	102452	700	0	0
T23	20918	72	0	0
T24	236654	9667	0	0
T25	77792	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	1439423	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	1439423	0	0
T1	92625	14	0	0
T2	431	5	0	0
T3	14876	28	0	0
T4	258111	3902	0	0
T18	203375	0	0	0
T21	49757	1010	0	0
T22	102452	993	0	0
T23	20918	218	0	0
T24	236654	28538	0	0
T25	77792	20	0	0
T26	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311996085	2723558	0	0
DepthKnown_A	311996085	311867412	0	0
RvalidKnown_A	311996085	311867412	0	0
WreadyKnown_A	311996085	311867412	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	2723558	0	0
T1	92625	1014	0	0
T2	431	5	0	0
T3	14876	35	0	0
T4	258111	2075	0	0
T18	203375	0	0	0
T21	49757	1010	0	0
T22	102452	676	0	0
T23	20918	97	0	0
T24	236654	10864	0	0
T25	77792	4	0	0
T26	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311996085	311867412	0	0
T1	92625	92617	0	0
T2	431	403	0	0
T3	14876	14859	0	0
T4	258111	258056	0	0
T18	203375	203369	0	0
T21	49757	49253	0	0
T22	102452	102351	0	0
T23	20918	20912	0	0
T24	236654	236650	0	0
T25	77792	77762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0