Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1656761	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

260898

1

T1

213

T2

17

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	648280	1			T1	505		T2	51		T3	32
values[0x0]	620019	1			T1	471		T2	53		T3	36
values[0x1]	649360	1			T1	475		T2	50		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1283443	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

634216

1

T1

509

T2

53

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8258	1			T1	7		T3	20		T15	2
valid_sources[0x01]	8753	1			T15	1		T16	4		T20	8
valid_sources[0x02]	7549	1			T1	50		T15	3		T18	1
valid_sources[0x03]	6979	1			T18	1		T17	1		T16	12
valid_sources[0x04]	7424	1			T1	4		T15	6		T18	3
valid_sources[0x05]	7461	1			T15	13		T16	8		T20	6
valid_sources[0x06]	8051	1			T15	2		T18	3		T16	9
valid_sources[0x07]	7325	1			T1	22		T18	3		T17	2
valid_sources[0x08]	7946	1			T15	1		T18	2		T17	1
valid_sources[0x09]	8106	1			T1	119		T15	1		T18	2
valid_sources[0x0a]	8410	1			T15	2		T18	3		T16	13
valid_sources[0x0b]	6780	1			T15	1		T13	1		T18	1
valid_sources[0x0c]	6979	1			T1	17		T15	9		T18	2
valid_sources[0x0d]	8435	1			T15	4		T18	1		T16	4
valid_sources[0x0e]	6594	1			T15	5		T18	2		T17	1
valid_sources[0x0f]	6921	1			T18	1		T16	11		T20	6
valid_sources[0x10]	6848	1			T15	3		T16	6		T20	7
valid_sources[0x11]	7771	1			T1	22		T15	5		T18	4
valid_sources[0x12]	7201	1			T1	10		T15	3		T17	2
valid_sources[0x13]	7415	1			T15	3		T17	1		T16	12
valid_sources[0x14]	7746	1			T15	1		T18	2		T17	1
valid_sources[0x15]	7543	1			T1	7		T15	5		T13	1
valid_sources[0x16]	6978	1			T1	14		T15	1		T18	3
valid_sources[0x17]	7156	1			T15	1		T18	3		T17	1
valid_sources[0x18]	7766	1			T15	2		T18	1		T14	1
valid_sources[0x19]	7051	1			T13	1		T18	5		T16	5
valid_sources[0x1a]	7881	1			T15	6		T13	1		T18	3
valid_sources[0x1b]	8338	1			T15	3		T13	1		T16	4
valid_sources[0x1c]	7003	1			T1	26		T15	1		T18	4
valid_sources[0x1d]	6637	1			T15	1		T13	2		T18	2
valid_sources[0x1e]	7103	1			T1	8		T15	5		T18	1
valid_sources[0x1f]	6954	1			T15	1		T18	3		T17	1
valid_sources[0x20]	7652	1			T1	13		T4	9		T15	3
valid_sources[0x21]	6919	1			T15	3		T18	3		T16	7
valid_sources[0x22]	9895	1			T13	1		T18	4		T16	14
valid_sources[0x23]	7371	1			T15	2		T18	3		T16	4
valid_sources[0x24]	6760	1			T18	1		T16	27		T20	7
valid_sources[0x25]	7867	1			T18	2		T17	1		T16	11
valid_sources[0x26]	6720	1			T1	1		T18	1		T17	2
valid_sources[0x27]	7942	1			T15	3		T18	3		T16	9
valid_sources[0x28]	7233	1			T1	8		T15	4		T18	1
valid_sources[0x29]	7923	1			T1	3		T3	18		T15	3
valid_sources[0x2a]	6884	1			T1	26		T18	2		T16	9
valid_sources[0x2b]	7415	1			T15	2		T13	1		T18	5
valid_sources[0x2c]	7523	1			T13	1		T18	4		T16	7
valid_sources[0x2d]	7348	1			T1	4		T15	2		T18	4
valid_sources[0x2e]	7646	1			T1	29		T15	4		T18	5
valid_sources[0x2f]	7715	1			T15	4		T18	2		T17	1
valid_sources[0x30]	6784	1			T1	3		T16	1		T20	6
valid_sources[0x31]	9120	1			T1	15		T15	2		T18	1
valid_sources[0x32]	7427	1			T4	20		T15	1		T18	4
valid_sources[0x33]	7454	1			T15	1		T18	1		T16	6
valid_sources[0x34]	8105	1			T15	4		T16	16		T20	6
valid_sources[0x35]	6563	1			T15	2		T18	1		T17	1
valid_sources[0x36]	8182	1			T18	6		T16	4		T20	8
valid_sources[0x37]	6916	1			T3	2		T15	2		T18	2
valid_sources[0x38]	7410	1			T1	7		T15	3		T18	1
valid_sources[0x39]	6664	1			T18	1		T16	9		T20	7
valid_sources[0x3a]	7672	1			T15	1		T18	5		T16	20
valid_sources[0x3b]	7500	1			T15	6		T13	1		T16	10
valid_sources[0x3c]	6832	1			T15	14		T17	1		T16	7
valid_sources[0x3d]	7167	1			T15	4		T18	1		T17	1
valid_sources[0x3e]	7088	1			T15	8		T18	1		T16	19
valid_sources[0x3f]	7388	1			T15	6		T18	3		T16	12
valid_sources[0x40]	6940	1			T1	58		T13	2		T16	14
valid_sources[0x41]	7406	1			T15	1		T18	3		T16	7
valid_sources[0x42]	7442	1			T1	1		T15	4		T18	2
valid_sources[0x43]	6959	1			T18	2		T20	7		T19	4
valid_sources[0x44]	6826	1			T1	4		T15	1		T13	1
valid_sources[0x45]	7437	1			T15	3		T18	2		T17	1
valid_sources[0x46]	7185	1			T15	1		T13	1		T18	1
valid_sources[0x47]	6508	1			T15	2		T18	2		T16	6
valid_sources[0x48]	7222	1			T15	3		T16	11		T20	7
valid_sources[0x49]	7273	1			T15	4		T18	3		T16	8
valid_sources[0x4a]	8120	1			T1	85		T15	3		T18	3
valid_sources[0x4b]	7115	1			T1	5		T15	4		T13	1
valid_sources[0x4c]	7049	1			T1	3		T15	9		T18	1
valid_sources[0x4d]	7239	1			T1	4		T15	7		T18	4
valid_sources[0x4e]	6800	1			T1	71		T2	77		T15	4
valid_sources[0x4f]	7110	1			T15	6		T18	6		T16	21
valid_sources[0x50]	7654	1			T15	2		T18	4		T16	19
valid_sources[0x51]	7654	1			T1	30		T15	3		T18	4
valid_sources[0x52]	7921	1			T15	8		T18	2		T16	8
valid_sources[0x53]	7165	1			T15	4		T18	3		T16	5
valid_sources[0x54]	7622	1			T15	5		T18	1		T16	3
valid_sources[0x55]	9912	1			T15	2		T18	2		T16	7
valid_sources[0x56]	7795	1			T13	1		T18	3		T17	1
valid_sources[0x57]	6976	1			T15	4		T18	1		T16	4
valid_sources[0x58]	6646	1			T15	1		T18	2		T16	11
valid_sources[0x59]	8253	1			T15	4		T18	1		T17	1
valid_sources[0x5a]	7826	1			T1	4		T4	10		T15	5
valid_sources[0x5b]	7025	1			T15	4		T18	4		T16	5
valid_sources[0x5c]	6700	1			T1	1		T15	3		T18	1
valid_sources[0x5d]	8374	1			T1	16		T18	1		T16	19
valid_sources[0x5e]	7420	1			T1	5		T15	2		T13	1
valid_sources[0x5f]	7083	1			T15	1		T18	5		T17	1
valid_sources[0x60]	6715	1			T1	81		T15	5		T18	1
valid_sources[0x61]	7708	1			T15	2		T16	9		T20	6
valid_sources[0x62]	7485	1			T1	37		T2	77		T15	4
valid_sources[0x63]	6907	1			T15	1		T13	1		T18	2
valid_sources[0x64]	7338	1			T16	2		T20	7		T19	14
valid_sources[0x65]	7506	1			T1	2		T18	3		T17	1
valid_sources[0x66]	7325	1			T15	2		T18	2		T16	7
valid_sources[0x67]	7708	1			T15	4		T13	1		T17	1
valid_sources[0x68]	7229	1			T18	3		T16	24		T20	7
valid_sources[0x69]	8111	1			T17	1		T16	8		T20	7
valid_sources[0x6a]	7189	1			T15	1		T18	1		T16	5
valid_sources[0x6b]	7313	1			T15	4		T16	5		T20	6
valid_sources[0x6c]	8515	1			T1	6		T15	3		T18	1
valid_sources[0x6d]	7827	1			T15	6		T18	2		T16	10
valid_sources[0x6e]	7052	1			T1	1		T15	3		T17	1
valid_sources[0x6f]	8147	1			T4	1		T18	2		T16	1
valid_sources[0x70]	6697	1			T15	2		T18	3		T17	1
valid_sources[0x71]	8009	1			T15	4		T18	3		T16	19
valid_sources[0x72]	9045	1			T15	3		T18	4		T17	1
valid_sources[0x73]	8497	1			T1	4		T4	31		T15	1
valid_sources[0x74]	6806	1			T1	7		T15	6		T18	3
valid_sources[0x75]	7373	1			T15	2		T18	2		T17	1
valid_sources[0x76]	7617	1			T15	3		T18	5		T17	1
valid_sources[0x77]	7655	1			T15	3		T18	5		T16	8
valid_sources[0x78]	6843	1			T15	1		T18	1		T16	8
valid_sources[0x79]	7870	1			T15	2		T18	2		T16	11
valid_sources[0x7a]	6765	1			T4	5		T15	4		T18	1
valid_sources[0x7b]	6964	1			T1	10		T15	5		T18	1
valid_sources[0x7c]	6790	1			T15	7		T18	3		T16	3
valid_sources[0x7d]	7981	1			T18	2		T16	16		T20	4
valid_sources[0x7e]	7628	1			T15	4		T18	2		T14	1
valid_sources[0x7f]	7955	1			T15	5		T18	4		T17	1
valid_sources[0x80]	7378	1			T1	24		T3	15		T15	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27399

1

T1

27

T2

1

T3

2

values[0x0]

all_enables

biggest_size

206101

1

T1

158

T2

14

T3

9

values[0x1]

all_enables

biggest_size

27398

1

T1

28

T2

2

T3

4