Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	340571021	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	340571021	0	0
T1	12014296	1404063	0	0
T2	35168	756	0	0
T3	183904	3891	0	0
T4	5777072	102750	0	0
T13	122416	4474	0	0
T14	386680	8383	0	0
T15	25433968	427762	0	0
T16	3139640	65977	0	0
T17	3661000	85218	0	0
T18	15499120	273460	0	0
T19	0	3498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12014296	12014184	0	0
T2	35168	32816	0	0
T3	183904	182504	0	0
T4	5777072	5776624	0	0
T13	122416	119504	0	0
T14	386680	367920	0	0
T15	25433968	25330480	0	0
T16	3139640	3136112	0	0
T17	3661000	3658312	0	0
T18	15499120	15498448	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12014296	12014184	0	0
T2	35168	32816	0	0
T3	183904	182504	0	0
T4	5777072	5776624	0	0
T13	122416	119504	0	0
T14	386680	367920	0	0
T15	25433968	25330480	0	0
T16	3139640	3136112	0	0
T17	3661000	3658312	0	0
T18	15499120	15498448	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12014296	12014184	0	0
T2	35168	32816	0	0
T3	183904	182504	0	0
T4	5777072	5776624	0	0
T13	122416	119504	0	0
T14	386680	367920	0	0
T15	25433968	25330480	0	0
T16	3139640	3136112	0	0
T17	3661000	3658312	0	0
T18	15499120	15498448	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	124851672	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	124851672	0	0
T1	214541	105245	0	0
T2	628	294	0	0
T3	3284	1553	0	0
T4	103162	101035	0	0
T13	2186	1732	0	0
T14	6905	3523	0	0
T15	454178	162379	0	0
T16	56065	24600	0	0
T17	65375	34245	0	0
T18	276770	266875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	89327117	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	89327117	0	0
T1	214541	382732	0	0
T2	628	154	0	0
T3	3284	737	0	0
T4	103162	451	0	0
T13	2186	914	0	0
T14	6905	1556	0	0
T15	454178	74500	0	0
T16	56065	21444	0	0
T17	65375	16916	0	0
T18	276770	2149	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1412245	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1412245	0	0
T1	214541	22888	0	0
T2	628	8	0	0
T3	3284	9	0	0
T4	103162	18	0	0
T13	2186	29	0	0
T14	6905	24	0	0
T15	454178	5418	0	0
T16	56065	253	0	0
T17	65375	648	0	0
T18	276770	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3648377	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3648377	0	0
T1	214541	18065	0	0
T2	628	8	0	0
T3	3284	36	0	0
T4	103162	5	0	0
T13	2186	29	0	0
T14	6905	2	0	0
T15	454178	3061	0	0
T16	56065	250	0	0
T17	65375	692	0	0
T18	276770	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1403080	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1403080	0	0
T1	214541	13334	0	0
T2	628	6	0	0
T3	3284	63	0	0
T4	103162	23	0	0
T13	2186	35	0	0
T14	6905	21	0	0
T15	454178	5632	0	0
T16	56065	313	0	0
T17	65375	440	0	0
T18	276770	120	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	2940210	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	2940210	0	0
T1	214541	7376	0	0
T2	628	6	0	0
T3	3284	36	0	0
T4	103162	7	0	0
T13	2186	35	0	0
T14	6905	32	0	0
T15	454178	4141	0	0
T16	56065	383	0	0
T17	65375	412	0	0
T18	276770	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1417334	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1417334	0	0
T1	214541	19844	0	0
T2	628	3	0	0
T3	3284	27	0	0
T4	103162	47	0	0
T13	2186	23	0	0
T14	6905	40	0	0
T15	454178	7125	0	0
T16	56065	334	0	0
T17	65375	713	0	0
T18	276770	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3004940	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3004940	0	0
T1	214541	16882	0	0
T2	628	3	0	0
T3	3284	24	0	0
T4	103162	10	0	0
T13	2186	23	0	0
T14	6905	18	0	0
T15	454178	3844	0	0
T16	56065	276	0	0
T17	65375	725	0	0
T18	276770	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1383705	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1383705	0	0
T1	214541	22063	0	0
T2	628	7	0	0
T3	3284	37	0	0
T4	103162	13	0	0
T13	2186	45	0	0
T14	6905	411	0	0
T15	454178	4442	0	0
T16	56065	603	0	0
T17	65375	613	0	0
T18	276770	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3293885	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3293885	0	0
T1	214541	14228	0	0
T2	628	7	0	0
T3	3284	23	0	0
T4	103162	244	0	0
T13	2186	45	0	0
T14	6905	445	0	0
T15	454178	3021	0	0
T16	56065	467	0	0
T17	65375	618	0	0
T18	276770	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1424193	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1424193	0	0
T1	214541	13125	0	0
T2	628	4	0	0
T3	3284	58	0	0
T4	103162	42	0	0
T13	2186	34	0	0
T14	6905	84	0	0
T15	454178	4396	0	0
T16	56065	336	0	0
T17	65375	627	0	0
T18	276770	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3239507	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3239507	0	0
T1	214541	12436	0	0
T2	628	4	0	0
T3	3284	89	0	0
T4	103162	9	0	0
T13	2186	34	0	0
T14	6905	74	0	0
T15	454178	2572	0	0
T16	56065	344	0	0
T17	65375	617	0	0
T18	276770	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1427761	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1427761	0	0
T1	214541	19325	0	0
T2	628	2	0	0
T3	3284	7	0	0
T4	103162	39	0	0
T13	2186	38	0	0
T14	6905	69	0	0
T15	454178	3378	0	0
T16	56065	422	0	0
T17	65375	571	0	0
T18	276770	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3770402	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3770402	0	0
T1	214541	13574	0	0
T2	628	2	0	0
T3	3284	26	0	0
T4	103162	10	0	0
T13	2186	38	0	0
T14	6905	30	0	0
T15	454178	2068	0	0
T16	56065	389	0	0
T17	65375	662	0	0
T18	276770	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1411585	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1411585	0	0
T1	214541	22840	0	0
T2	628	4	0	0
T3	3284	24	0	0
T4	103162	42	0	0
T13	2186	32	0	0
T14	6905	32	0	0
T15	454178	2854	0	0
T16	56065	424	0	0
T17	65375	584	0	0
T18	276770	119	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3494858	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3494858	0	0
T1	214541	16193	0	0
T2	628	4	0	0
T3	3284	41	0	0
T4	103162	12	0	0
T13	2186	32	0	0
T14	6905	29	0	0
T15	454178	1826	0	0
T16	56065	428	0	0
T17	65375	566	0	0
T18	276770	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1404809	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1404809	0	0
T1	214541	23471	0	0
T2	628	7	0	0
T3	3284	34	0	0
T4	103162	32	0	0
T13	2186	31	0	0
T14	6905	2	0	0
T15	454178	5378	0	0
T16	56065	240	0	0
T17	65375	712	0	0
T18	276770	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3537469	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3537469	0	0
T1	214541	18502	0	0
T2	628	7	0	0
T3	3284	28	0	0
T4	103162	7	0	0
T13	2186	31	0	0
T14	6905	1	0	0
T15	454178	3192	0	0
T16	56065	291	0	0
T17	65375	720	0	0
T18	276770	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1383618	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1383618	0	0
T1	214541	23395	0	0
T2	628	6	0	0
T3	3284	52	0	0
T4	103162	43	0	0
T13	2186	33	0	0
T14	6905	65	0	0
T15	454178	3206	0	0
T16	56065	474	0	0
T17	65375	641	0	0
T18	276770	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3673424	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3673424	0	0
T1	214541	16051	0	0
T2	628	6	0	0
T3	3284	41	0	0
T4	103162	7	0	0
T13	2186	33	0	0
T14	6905	29	0	0
T15	454178	2012	0	0
T16	56065	376	0	0
T17	65375	541	0	0
T18	276770	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1395702	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1395702	0	0
T1	214541	23377	0	0
T2	628	4	0	0
T3	3284	32	0	0
T4	103162	22	0	0
T13	2186	35	0	0
T14	6905	167	0	0
T15	454178	7148	0	0
T16	56065	318	0	0
T17	65375	744	0	0
T18	276770	119	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3242216	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3242216	0	0
T1	214541	13574	0	0
T2	628	4	0	0
T3	3284	31	0	0
T4	103162	12	0	0
T13	2186	35	0	0
T14	6905	95	0	0
T15	454178	4319	0	0
T16	56065	307	0	0
T17	65375	776	0	0
T18	276770	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1407395	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1407395	0	0
T1	214541	17969	0	0
T2	628	11	0	0
T3	3284	51	0	0
T4	103162	28	0	0
T13	2186	43	0	0
T14	6905	50	0	0
T15	454178	3179	0	0
T16	56065	403	0	0
T17	65375	541	0	0
T18	276770	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	4346268	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	4346268	0	0
T1	214541	15424	0	0
T2	628	11	0	0
T3	3284	37	0	0
T4	103162	7	0	0
T13	2186	43	0	0
T14	6905	47	0	0
T15	454178	2094	0	0
T16	56065	341	0	0
T17	65375	693	0	0
T18	276770	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1415137	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1415137	0	0
T1	214541	18751	0	0
T2	628	5	0	0
T3	3284	49	0	0
T4	103162	22	0	0
T13	2186	24	0	0
T14	6905	73	0	0
T15	454178	4344	0	0
T16	56065	411	0	0
T17	65375	627	0	0
T18	276770	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3506483	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3506483	0	0
T1	214541	16975	0	0
T2	628	5	0	0
T3	3284	46	0	0
T4	103162	8	0	0
T13	2186	24	0	0
T14	6905	59	0	0
T15	454178	3049	0	0
T16	56065	510	0	0
T17	65375	578	0	0
T18	276770	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1416728	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1416728	0	0
T1	214541	16085	0	0
T2	628	4	0	0
T3	3284	55	0	0
T4	103162	31	0	0
T13	2186	35	0	0
T14	6905	52	0	0
T15	454178	3133	0	0
T16	56065	512	0	0
T17	65375	671	0	0
T18	276770	103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3846186	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3846186	0	0
T1	214541	10429	0	0
T2	628	4	0	0
T3	3284	30	0	0
T4	103162	7	0	0
T13	2186	35	0	0
T14	6905	58	0	0
T15	454178	1736	0	0
T16	56065	452	0	0
T17	65375	651	0	0
T18	276770	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1415659	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1415659	0	0
T1	214541	17662	0	0
T2	628	8	0	0
T3	3284	44	0	0
T4	103162	34	0	0
T13	2186	43	0	0
T14	6905	63	0	0
T15	454178	4006	0	0
T16	56065	341	0	0
T17	65375	678	0	0
T18	276770	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	2981820	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	2981820	0	0
T1	214541	11528	0	0
T2	628	8	0	0
T3	3284	15	0	0
T4	103162	8	0	0
T13	2186	43	0	0
T14	6905	27	0	0
T15	454178	2442	0	0
T16	56065	284	0	0
T17	65375	651	0	0
T18	276770	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1387936	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1387936	0	0
T1	214541	22563	0	0
T2	628	3	0	0
T3	3284	0	0	0
T4	103162	16	0	0
T13	2186	32	0	0
T14	6905	63	0	0
T15	454178	5369	0	0
T16	56065	280	0	0
T17	65375	817	0	0
T18	276770	91	0	0
T19	0	1731	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	2729496	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	2729496	0	0
T1	214541	16045	0	0
T2	628	3	0	0
T3	3284	0	0	0
T4	103162	3	0	0
T13	2186	32	0	0
T14	6905	44	0	0
T15	454178	2874	0	0
T16	56065	285	0	0
T17	65375	765	0	0
T18	276770	23	0	0
T19	0	1767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1383526	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1383526	0	0
T1	214541	19936	0	0
T2	628	6	0	0
T3	3284	20	0	0
T4	103162	37	0	0
T13	2186	39	0	0
T14	6905	53	0	0
T15	454178	5934	0	0
T16	56065	307	0	0
T17	65375	686	0	0
T18	276770	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	2757307	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	2757307	0	0
T1	214541	15824	0	0
T2	628	6	0	0
T3	3284	23	0	0
T4	103162	7	0	0
T13	2186	39	0	0
T14	6905	48	0	0
T15	454178	3284	0	0
T16	56065	325	0	0
T17	65375	693	0	0
T18	276770	330	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1349738	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1349738	0	0
T1	214541	20010	0	0
T2	628	3	0	0
T3	3284	27	0	0
T4	103162	14	0	0
T13	2186	38	0	0
T14	6905	49	0	0
T15	454178	3156	0	0
T16	56065	262	0	0
T17	65375	658	0	0
T18	276770	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	2751937	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	2751937	0	0
T1	214541	12191	0	0
T2	628	3	0	0
T3	3284	27	0	0
T4	103162	5	0	0
T13	2186	38	0	0
T14	6905	59	0	0
T15	454178	2101	0	0
T16	56065	329	0	0
T17	65375	646	0	0
T18	276770	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1437567	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1437567	0	0
T1	214541	18934	0	0
T2	628	7	0	0
T3	3284	30	0	0
T4	103162	17	0	0
T13	2186	34	0	0
T14	6905	17	0	0
T15	454178	4579	0	0
T16	56065	476	0	0
T17	65375	561	0	0
T18	276770	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3128554	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3128554	0	0
T1	214541	12486	0	0
T2	628	7	0	0
T3	3284	29	0	0
T4	103162	6	0	0
T13	2186	34	0	0
T14	6905	24	0	0
T15	454178	2976	0	0
T16	56065	400	0	0
T17	65375	628	0	0
T18	276770	499	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1423282	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1423282	0	0
T1	214541	20577	0	0
T2	628	7	0	0
T3	3284	34	0	0
T4	103162	58	0	0
T13	2186	31	0	0
T14	6905	69	0	0
T15	454178	5319	0	0
T16	56065	371	0	0
T17	65375	571	0	0
T18	276770	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	2916816	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	2916816	0	0
T1	214541	15052	0	0
T2	628	7	0	0
T3	3284	18	0	0
T4	103162	12	0	0
T13	2186	31	0	0
T14	6905	67	0	0
T15	454178	2790	0	0
T16	56065	324	0	0
T17	65375	444	0	0
T18	276770	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1457669	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1457669	0	0
T1	214541	13971	0	0
T2	628	2	0	0
T3	3284	17	0	0
T4	103162	11	0	0
T13	2186	31	0	0
T14	6905	71	0	0
T15	454178	3326	0	0
T16	56065	508	0	0
T17	65375	605	0	0
T18	276770	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3143914	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3143914	0	0
T1	214541	8162	0	0
T2	628	2	0	0
T3	3284	20	0	0
T4	103162	3	0	0
T13	2186	31	0	0
T14	6905	33	0	0
T15	454178	2070	0	0
T16	56065	409	0	0
T17	65375	462	0	0
T18	276770	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1392432	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1392432	0	0
T1	214541	22642	0	0
T2	628	8	0	0
T3	3284	12	0	0
T4	103162	24	0	0
T13	2186	32	0	0
T14	6905	32	0	0
T15	454178	3120	0	0
T16	56065	413	0	0
T17	65375	532	0	0
T18	276770	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	2903924	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	2903924	0	0
T1	214541	17474	0	0
T2	628	8	0	0
T3	3284	8	0	0
T4	103162	5	0	0
T13	2186	32	0	0
T14	6905	43	0	0
T15	454178	1751	0	0
T16	56065	388	0	0
T17	65375	485	0	0
T18	276770	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1379714	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1379714	0	0
T1	214541	16533	0	0
T2	628	7	0	0
T3	3284	33	0	0
T4	103162	39	0	0
T13	2186	38	0	0
T14	6905	22	0	0
T15	454178	3566	0	0
T16	56065	421	0	0
T17	65375	601	0	0
T18	276770	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3260881	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3260881	0	0
T1	214541	10798	0	0
T2	628	7	0	0
T3	3284	14	0	0
T4	103162	6	0	0
T13	2186	38	0	0
T14	6905	11	0	0
T15	454178	2156	0	0
T16	56065	502	0	0
T17	65375	666	0	0
T18	276770	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1430832	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1430832	0	0
T1	214541	24908	0	0
T2	628	3	0	0
T3	3284	38	0	0
T4	103162	22	0	0
T13	2186	28	0	0
T14	6905	49	0	0
T15	454178	3347	0	0
T16	56065	431	0	0
T17	65375	663	0	0
T18	276770	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3215500	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3215500	0	0
T1	214541	12618	0	0
T2	628	3	0	0
T3	3284	27	0	0
T4	103162	6	0	0
T13	2186	28	0	0
T14	6905	63	0	0
T15	454178	2147	0	0
T16	56065	400	0	0
T17	65375	596	0	0
T18	276770	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1395467	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1395467	0	0
T1	214541	17285	0	0
T2	628	16	0	0
T3	3284	39	0	0
T4	103162	27	0	0
T13	2186	23	0	0
T14	6905	52	0	0
T15	454178	3758	0	0
T16	56065	254	0	0
T17	65375	550	0	0
T18	276770	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	2554864	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	2554864	0	0
T1	214541	14834	0	0
T2	628	16	0	0
T3	3284	15	0	0
T4	103162	6	0	0
T13	2186	23	0	0
T14	6905	52	0	0
T15	454178	2686	0	0
T16	56065	259	0	0
T17	65375	525	0	0
T18	276770	762	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1383750	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1383750	0	0
T1	214541	17179	0	0
T2	628	4	0	0
T3	3284	10	0	0
T4	103162	24	0	0
T13	2186	36	0	0
T14	6905	62	0	0
T15	454178	3457	0	0
T16	56065	380	0	0
T17	65375	641	0	0
T18	276770	109	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3469453	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3469453	0	0
T1	214541	13750	0	0
T2	628	4	0	0
T3	3284	4	0	0
T4	103162	7	0	0
T13	2186	36	0	0
T14	6905	52	0	0
T15	454178	2503	0	0
T16	56065	302	0	0
T17	65375	670	0	0
T18	276770	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1416571	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1416571	0	0
T1	214541	18544	0	0
T2	628	6	0	0
T3	3284	44	0	0
T4	103162	33	0	0
T13	2186	42	0	0
T14	6905	35	0	0
T15	454178	5816	0	0
T16	56065	412	0	0
T17	65375	763	0	0
T18	276770	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3197713	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3197713	0	0
T1	214541	17572	0	0
T2	628	6	0	0
T3	3284	48	0	0
T4	103162	19	0	0
T13	2186	42	0	0
T14	6905	46	0	0
T15	454178	4276	0	0
T16	56065	375	0	0
T17	65375	648	0	0
T18	276770	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	1414019	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	1414019	0	0
T1	214541	26474	0	0
T2	628	3	0	0
T3	3284	18	0	0
T4	103162	55	0	0
T13	2186	30	0	0
T14	6905	43	0	0
T15	454178	3492	0	0
T16	56065	331	0	0
T17	65375	700	0	0
T18	276770	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	310577823	3864374	0	0
DepthKnown_A	310577823	310454450	0	0
RvalidKnown_A	310577823	310454450	0	0
WreadyKnown_A	310577823	310454450	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	3864374	0	0
T1	214541	14358	0	0
T2	628	3	0	0
T3	3284	1	0	0
T4	103162	13	0	0
T13	2186	30	0	0
T14	6905	46	0	0
T15	454178	2014	0	0
T16	56065	307	0	0
T17	65375	769	0	0
T18	276770	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	310577823	310454450	0	0
T1	214541	214539	0	0
T2	628	586	0	0
T3	3284	3259	0	0
T4	103162	103154	0	0
T13	2186	2134	0	0
T14	6905	6570	0	0
T15	454178	452330	0	0
T16	56065	56002	0	0
T17	65375	65327	0	0
T18	276770	276758	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0