Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1558842	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

245900

1

T1

138

T2

223

T3

638

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	609431	1			T1	338		T2	578		T3	1514
values[0x0]	585237	1			T1	355		T2	540		T3	1541
values[0x1]	610074	1			T1	329		T2	547		T3	1517

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1208852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

595890

1

T1

341

T2

529

T3

1471

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7257	1			T1	4		T3	19		T5	4
valid_sources[0x01]	8821	1			T1	4		T3	20		T5	2
valid_sources[0x02]	6250	1			T1	4		T3	16		T5	3
valid_sources[0x03]	7207	1			T1	4		T3	18		T15	22
valid_sources[0x04]	7290	1			T1	4		T3	17		T4	29
valid_sources[0x05]	7186	1			T1	4		T3	19		T5	4
valid_sources[0x06]	6547	1			T1	5		T3	20		T4	20
valid_sources[0x07]	6872	1			T1	4		T3	19		T5	3
valid_sources[0x08]	6818	1			T1	4		T3	18		T5	7
valid_sources[0x09]	7335	1			T1	4		T3	15		T5	1
valid_sources[0x0a]	7125	1			T1	4		T3	16		T5	1
valid_sources[0x0b]	6386	1			T1	4		T3	17		T5	12
valid_sources[0x0c]	6936	1			T1	4		T3	20		T5	6
valid_sources[0x0d]	6855	1			T1	4		T3	18		T5	12
valid_sources[0x0e]	6657	1			T1	3		T3	21		T5	1
valid_sources[0x0f]	7084	1			T1	5		T3	19		T5	1
valid_sources[0x10]	7019	1			T1	4		T3	19		T5	2
valid_sources[0x11]	7431	1			T1	2		T3	18		T5	6
valid_sources[0x12]	6840	1			T1	4		T3	15		T4	26
valid_sources[0x13]	7289	1			T1	4		T3	20		T5	6
valid_sources[0x14]	6890	1			T1	4		T3	17		T5	2
valid_sources[0x15]	7903	1			T1	4		T3	22		T5	2
valid_sources[0x16]	7166	1			T1	4		T2	18		T3	18
valid_sources[0x17]	6684	1			T1	4		T3	19		T5	5
valid_sources[0x18]	7651	1			T1	5		T3	18		T5	3
valid_sources[0x19]	6630	1			T1	3		T3	16		T5	6
valid_sources[0x1a]	6871	1			T1	4		T3	16		T5	12
valid_sources[0x1b]	6898	1			T1	4		T3	18		T5	8
valid_sources[0x1c]	7172	1			T1	4		T3	18		T5	7
valid_sources[0x1d]	6800	1			T1	4		T3	17		T5	5
valid_sources[0x1e]	7051	1			T1	4		T3	18		T5	4
valid_sources[0x1f]	7092	1			T1	3		T3	18		T5	6
valid_sources[0x20]	6645	1			T1	5		T3	18		T5	10
valid_sources[0x21]	6167	1			T1	5		T3	18		T5	7
valid_sources[0x22]	6222	1			T1	4		T3	19		T5	4
valid_sources[0x23]	6561	1			T1	4		T2	14		T3	17
valid_sources[0x24]	6596	1			T1	4		T3	16		T5	2
valid_sources[0x25]	8013	1			T1	4		T3	17		T18	3
valid_sources[0x26]	7791	1			T1	4		T3	18		T5	19
valid_sources[0x27]	6565	1			T1	4		T3	17		T17	1
valid_sources[0x28]	6973	1			T1	3		T3	18		T5	8
valid_sources[0x29]	7164	1			T1	3		T3	21		T5	2
valid_sources[0x2a]	6464	1			T1	4		T3	19		T5	5
valid_sources[0x2b]	7620	1			T1	4		T2	151		T3	17
valid_sources[0x2c]	7277	1			T1	3		T3	18		T5	18
valid_sources[0x2d]	7089	1			T1	4		T3	17		T5	10
valid_sources[0x2e]	6837	1			T1	4		T3	16		T5	4
valid_sources[0x2f]	6238	1			T1	5		T3	20		T4	31
valid_sources[0x30]	7143	1			T1	4		T3	17		T5	8
valid_sources[0x31]	7633	1			T1	3		T3	22		T5	5
valid_sources[0x32]	6934	1			T1	4		T3	17		T5	1
valid_sources[0x33]	6517	1			T1	4		T3	16		T17	1
valid_sources[0x34]	7710	1			T1	4		T3	15		T5	4
valid_sources[0x35]	7084	1			T1	4		T3	18		T5	6
valid_sources[0x36]	7721	1			T1	5		T3	17		T5	11
valid_sources[0x37]	7267	1			T1	4		T3	17		T5	6
valid_sources[0x38]	6971	1			T1	4		T3	18		T18	1
valid_sources[0x39]	7755	1			T1	5		T2	51		T3	18
valid_sources[0x3a]	6442	1			T1	4		T3	17		T17	3
valid_sources[0x3b]	7303	1			T1	4		T3	18		T5	3
valid_sources[0x3c]	6624	1			T1	4		T3	19		T5	11
valid_sources[0x3d]	7238	1			T1	3		T3	20		T17	1
valid_sources[0x3e]	7464	1			T1	4		T3	16		T5	2
valid_sources[0x3f]	6914	1			T1	4		T3	21		T5	14
valid_sources[0x40]	6633	1			T1	5		T3	17		T5	5
valid_sources[0x41]	6518	1			T1	3		T3	18		T5	2
valid_sources[0x42]	7237	1			T1	3		T3	19		T5	1
valid_sources[0x43]	6788	1			T1	5		T3	19		T5	1
valid_sources[0x44]	6555	1			T1	4		T3	19		T5	9
valid_sources[0x45]	7302	1			T1	4		T3	17		T18	1
valid_sources[0x46]	7104	1			T1	3		T3	21		T5	1
valid_sources[0x47]	9222	1			T1	4		T3	19		T5	7
valid_sources[0x48]	6840	1			T1	4		T3	18		T5	15
valid_sources[0x49]	6900	1			T1	4		T3	19		T5	31
valid_sources[0x4a]	6234	1			T1	4		T3	17		T5	7
valid_sources[0x4b]	7583	1			T1	3		T3	18		T18	2
valid_sources[0x4c]	7611	1			T1	4		T2	577		T3	17
valid_sources[0x4d]	7335	1			T1	5		T3	17		T14	1
valid_sources[0x4e]	7149	1			T1	4		T3	17		T5	10
valid_sources[0x4f]	6785	1			T1	5		T3	17		T5	14
valid_sources[0x50]	7703	1			T1	5		T2	1		T3	19
valid_sources[0x51]	6326	1			T1	4		T3	19		T5	11
valid_sources[0x52]	6610	1			T1	4		T3	19		T15	20
valid_sources[0x53]	7648	1			T1	3		T3	17		T18	2
valid_sources[0x54]	8629	1			T1	3		T3	17		T5	4
valid_sources[0x55]	6549	1			T1	5		T3	17		T17	1
valid_sources[0x56]	9101	1			T1	4		T3	17		T5	3
valid_sources[0x57]	8587	1			T1	4		T3	19		T17	2
valid_sources[0x58]	6371	1			T1	4		T3	15		T5	1
valid_sources[0x59]	6661	1			T1	3		T3	15		T5	2
valid_sources[0x5a]	6982	1			T1	2		T3	17		T5	4
valid_sources[0x5b]	7089	1			T1	6		T3	17		T5	12
valid_sources[0x5c]	7282	1			T1	4		T3	20		T5	9
valid_sources[0x5d]	6860	1			T1	4		T3	13		T18	2
valid_sources[0x5e]	6798	1			T1	4		T3	17		T5	2
valid_sources[0x5f]	6649	1			T1	4		T3	17		T5	15
valid_sources[0x60]	6893	1			T1	4		T3	16		T5	2
valid_sources[0x61]	7553	1			T1	4		T3	19		T5	7
valid_sources[0x62]	7691	1			T1	4		T3	17		T5	7
valid_sources[0x63]	6322	1			T1	4		T3	17		T5	30
valid_sources[0x64]	6447	1			T1	4		T3	21		T5	9
valid_sources[0x65]	6437	1			T1	4		T3	16		T5	4
valid_sources[0x66]	6689	1			T1	4		T3	19		T5	2
valid_sources[0x67]	7532	1			T1	4		T3	18		T5	2
valid_sources[0x68]	7032	1			T1	4		T3	19		T5	3
valid_sources[0x69]	7076	1			T1	4		T3	18		T5	18
valid_sources[0x6a]	6682	1			T1	4		T3	21		T5	12
valid_sources[0x6b]	7281	1			T1	3		T3	18		T5	4
valid_sources[0x6c]	6677	1			T1	4		T3	17		T5	7
valid_sources[0x6d]	6919	1			T1	3		T2	94		T3	17
valid_sources[0x6e]	6655	1			T1	5		T3	18		T5	13
valid_sources[0x6f]	7045	1			T1	4		T3	18		T5	2
valid_sources[0x70]	8160	1			T1	4		T3	18		T5	9
valid_sources[0x71]	7347	1			T1	4		T3	19		T5	1
valid_sources[0x72]	6546	1			T1	3		T2	11		T3	18
valid_sources[0x73]	6055	1			T1	3		T3	20		T5	2
valid_sources[0x74]	7882	1			T1	4		T3	19		T5	16
valid_sources[0x75]	6501	1			T1	4		T3	18		T5	21
valid_sources[0x76]	7083	1			T1	5		T3	18		T5	10
valid_sources[0x77]	7955	1			T1	4		T3	18		T5	2
valid_sources[0x78]	7665	1			T1	5		T3	18		T5	6
valid_sources[0x79]	6270	1			T1	3		T3	21		T5	4
valid_sources[0x7a]	6526	1			T1	4		T3	15		T5	7
valid_sources[0x7b]	7315	1			T1	4		T3	16		T5	2
valid_sources[0x7c]	6750	1			T1	5		T3	16		T5	10
valid_sources[0x7d]	6442	1			T1	4		T3	19		T5	5
valid_sources[0x7e]	6860	1			T1	4		T3	16		T15	36
valid_sources[0x7f]	6212	1			T1	3		T3	17		T5	4
valid_sources[0x80]	6654	1			T1	5		T3	19		T15	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25836

1

T1

11

T2

23

T3

72

values[0x0]

all_enables

biggest_size

194201

1

T1

114

T2

177

T3

503

values[0x1]

all_enables

biggest_size

25863

1

T1

13

T2

23

T3

63