Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	333913516	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333913516	0	0
T1	8725560	738162	0	0
T2	204848	7401	0	0
T3	21758632	1799046	0	0
T4	38775016	692945	0	0
T5	163352	6303	0	0
T14	1582056	33129	0	0
T15	12281976	264973	0	0
T16	0	2862	0	0
T17	9248736	171988	0	0
T18	48384	908	0	0
T19	53842768	1010484	0	0
T20	18606540	168427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48863136	48860224	0	0
T2	204848	196672	0	0
T3	21758632	21758240	0	0
T4	38775016	38772440	0	0
T5	163352	160048	0	0
T14	1582056	1581104	0	0
T15	12281976	12260136	0	0
T17	9248736	9244760	0	0
T18	48384	45360	0	0
T19	53842768	53840136	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48863136	48860224	0	0
T2	204848	196672	0	0
T3	21758632	21758240	0	0
T4	38775016	38772440	0	0
T5	163352	160048	0	0
T14	1582056	1581104	0	0
T15	12281976	12260136	0	0
T17	9248736	9244760	0	0
T18	48384	45360	0	0
T19	53842768	53840136	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48863136	48860224	0	0
T2	204848	196672	0	0
T3	21758632	21758240	0	0
T4	38775016	38772440	0	0
T5	163352	160048	0	0
T14	1582056	1581104	0	0
T15	12281976	12260136	0	0
T17	9248736	9244760	0	0
T18	48384	45360	0	0
T19	53842768	53840136	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	126594548	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	126594548	0	0
T1	872556	4852	0	0
T2	3658	3278	0	0
T3	388547	20990	0	0
T4	692411	674559	0	0
T5	2917	2442	0	0
T14	28251	15138	0	0
T15	219321	106071	0	0
T17	165156	82251	0	0
T18	864	353	0	0
T19	961478	464880	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	83710461	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	83710461	0	0
T1	872556	364229	0	0
T2	3658	1665	0	0
T3	388547	159733	0	0
T4	692411	6268	0	0
T5	2917	1287	0	0
T14	28251	4227	0	0
T15	219321	62872	0	0
T17	165156	17765	0	0
T18	864	185	0	0
T19	961478	114599	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1497152	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1497152	0	0
T2	3658	44	0	0
T3	388547	1009	0	0
T4	692411	234	0	0
T5	2917	56	0	0
T14	28251	333	0	0
T15	219321	1623	0	0
T17	165156	850	0	0
T18	864	8	0	0
T19	961478	15876	0	0
T20	404490	4969	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2782477	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2782477	0	0
T2	3658	44	0	0
T3	388547	84769	0	0
T4	692411	1159	0	0
T5	2917	56	0	0
T14	28251	118	0	0
T15	219321	1600	0	0
T17	165156	82	0	0
T18	864	8	0	0
T19	961478	7875	0	0
T20	404490	1267	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1494309	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1494309	0	0
T2	3658	43	0	0
T3	388547	1238	0	0
T4	692411	209	0	0
T5	2917	58	0	0
T14	28251	274	0	0
T15	219321	1855	0	0
T17	165156	2101	0	0
T18	864	7	0	0
T19	961478	11029	0	0
T20	404490	4768	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3264496	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3264496	0	0
T2	3658	43	0	0
T3	388547	89169	0	0
T4	692411	47	0	0
T5	2917	58	0	0
T14	28251	116	0	0
T15	219321	1871	0	0
T17	165156	1202	0	0
T18	864	7	0	0
T19	961478	3922	0	0
T20	404490	1030	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1513863	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1513863	0	0
T2	3658	36	0	0
T3	388547	2129	0	0
T4	692411	194	0	0
T5	2917	38	0	0
T14	28251	338	0	0
T15	219321	1662	0	0
T17	165156	785	0	0
T18	864	4	0	0
T19	961478	14063	0	0
T20	404490	5291	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3357964	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3357964	0	0
T2	3658	36	0	0
T3	388547	158845	0	0
T4	692411	393	0	0
T5	2917	38	0	0
T14	28251	155	0	0
T15	219321	1734	0	0
T17	165156	60	0	0
T18	864	4	0	0
T19	961478	4943	0	0
T20	404490	3110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1518365	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1518365	0	0
T2	3658	47	0	0
T3	388547	0	0	0
T4	692411	228	0	0
T5	2917	51	0	0
T14	28251	349	0	0
T15	219321	1639	0	0
T16	0	140	0	0
T17	165156	2733	0	0
T18	864	7	0	0
T19	961478	10207	0	0
T20	404490	5789	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2900109	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2900109	0	0
T2	3658	47	0	0
T3	388547	0	0	0
T4	692411	58	0	0
T5	2917	51	0	0
T14	28251	158	0	0
T15	219321	1743	0	0
T16	0	46	0	0
T17	165156	729	0	0
T18	864	7	0	0
T19	961478	5007	0	0
T20	404490	2681	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1483129	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1483129	0	0
T2	3658	41	0	0
T3	388547	0	0	0
T4	692411	202	0	0
T5	2917	40	0	0
T14	28251	274	0	0
T15	219321	2061	0	0
T16	0	300	0	0
T17	165156	1852	0	0
T18	864	6	0	0
T19	961478	12059	0	0
T20	404490	4731	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3075566	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3075566	0	0
T2	3658	41	0	0
T3	388547	0	0	0
T4	692411	49	0	0
T5	2917	40	0	0
T14	28251	113	0	0
T15	219321	1876	0	0
T16	0	115	0	0
T17	165156	619	0	0
T18	864	6	0	0
T19	961478	4501	0	0
T20	404490	779	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1572053	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1572053	0	0
T2	3658	40	0	0
T3	388547	969	0	0
T4	692411	281	0	0
T5	2917	53	0	0
T14	28251	254	0	0
T15	219321	1633	0	0
T17	165156	1076	0	0
T18	864	6	0	0
T19	961478	13974	0	0
T20	404490	5086	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3093511	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3093511	0	0
T2	3658	40	0	0
T3	388547	74868	0	0
T4	692411	186	0	0
T5	2917	53	0	0
T14	28251	141	0	0
T15	219321	1799	0	0
T17	165156	599	0	0
T18	864	6	0	0
T19	961478	4644	0	0
T20	404490	1056	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1538114	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1538114	0	0
T2	3658	45	0	0
T3	388547	948	0	0
T4	692411	163	0	0
T5	2917	49	0	0
T14	28251	353	0	0
T15	219321	2188	0	0
T17	165156	1662	0	0
T18	864	7	0	0
T19	961478	13591	0	0
T20	404490	7451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3217064	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3217064	0	0
T2	3658	45	0	0
T3	388547	79734	0	0
T4	692411	35	0	0
T5	2917	49	0	0
T14	28251	160	0	0
T15	219321	2092	0	0
T17	165156	926	0	0
T18	864	7	0	0
T19	961478	4535	0	0
T20	404490	3054	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1488986	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1488986	0	0
T1	872556	1297	0	0
T2	3658	33	0	0
T3	388547	1077	0	0
T4	692411	235	0	0
T5	2917	54	0	0
T14	28251	421	0	0
T15	219321	1605	0	0
T17	165156	2029	0	0
T18	864	9	0	0
T19	961478	8359	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2789176	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2789176	0	0
T1	872556	98420	0	0
T2	3658	33	0	0
T3	388547	77081	0	0
T4	692411	57	0	0
T5	2917	54	0	0
T14	28251	226	0	0
T15	219321	1517	0	0
T17	165156	5	0	0
T18	864	9	0	0
T19	961478	2645	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1508565	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1508565	0	0
T2	3658	47	0	0
T3	388547	0	0	0
T4	692411	188	0	0
T5	2917	49	0	0
T14	28251	535	0	0
T15	219321	1965	0	0
T16	0	154	0	0
T17	165156	1032	0	0
T18	864	5	0	0
T19	961478	11619	0	0
T20	404490	6113	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2636843	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2636843	0	0
T2	3658	47	0	0
T3	388547	0	0	0
T4	692411	61	0	0
T5	2917	49	0	0
T14	28251	164	0	0
T15	219321	1981	0	0
T16	0	76	0	0
T17	165156	551	0	0
T18	864	5	0	0
T19	961478	6657	0	0
T20	404490	2543	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1529652	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1529652	0	0
T2	3658	51	0	0
T3	388547	1355	0	0
T4	692411	202	0	0
T5	2917	46	0	0
T14	28251	369	0	0
T15	219321	1816	0	0
T17	165156	1900	0	0
T18	864	8	0	0
T19	961478	11997	0	0
T20	404490	3993	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2526884	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2526884	0	0
T2	3658	51	0	0
T3	388547	108821	0	0
T4	692411	356	0	0
T5	2917	46	0	0
T14	28251	207	0	0
T15	219321	1753	0	0
T17	165156	546	0	0
T18	864	8	0	0
T19	961478	2181	0	0
T20	404490	2854	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1515234	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1515234	0	0
T2	3658	63	0	0
T3	388547	1420	0	0
T4	692411	230	0	0
T5	2917	37	0	0
T14	28251	442	0	0
T15	219321	1816	0	0
T17	165156	1631	0	0
T18	864	7	0	0
T19	961478	13568	0	0
T20	404490	5229	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3237206	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3237206	0	0
T2	3658	63	0	0
T3	388547	99547	0	0
T4	692411	699	0	0
T5	2917	37	0	0
T14	28251	212	0	0
T15	219321	1738	0	0
T17	165156	731	0	0
T18	864	7	0	0
T19	961478	4736	0	0
T20	404490	2452	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1510899	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1510899	0	0
T2	3658	48	0	0
T3	388547	0	0	0
T4	692411	227	0	0
T5	2917	51	0	0
T14	28251	365	0	0
T15	219321	1908	0	0
T16	0	186	0	0
T17	165156	2605	0	0
T18	864	6	0	0
T19	961478	10166	0	0
T20	404490	7627	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2695897	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2695897	0	0
T2	3658	48	0	0
T3	388547	0	0	0
T4	692411	67	0	0
T5	2917	51	0	0
T14	28251	148	0	0
T15	219321	1768	0	0
T16	0	122	0	0
T17	165156	754	0	0
T18	864	6	0	0
T19	961478	3110	0	0
T20	404490	2829	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1513934	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1513934	0	0
T2	3658	44	0	0
T3	388547	1303	0	0
T4	692411	268	0	0
T5	2917	50	0	0
T14	28251	301	0	0
T15	219321	1825	0	0
T17	165156	2862	0	0
T18	864	4	0	0
T19	961478	11163	0	0
T20	404490	8671	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3099461	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3099461	0	0
T2	3658	44	0	0
T3	388547	96849	0	0
T4	692411	1018	0	0
T5	2917	50	0	0
T14	28251	153	0	0
T15	219321	1769	0	0
T17	165156	1869	0	0
T18	864	4	0	0
T19	961478	4118	0	0
T20	404490	3545	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1496984	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1496984	0	0
T2	3658	57	0	0
T3	388547	0	0	0
T4	692411	204	0	0
T5	2917	43	0	0
T14	28251	299	0	0
T15	219321	1677	0	0
T16	0	258	0	0
T17	165156	1737	0	0
T18	864	10	0	0
T19	961478	8736	0	0
T20	404490	5665	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2878279	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2878279	0	0
T2	3658	57	0	0
T3	388547	0	0	0
T4	692411	50	0	0
T5	2917	43	0	0
T14	28251	90	0	0
T15	219321	1618	0	0
T16	0	132	0	0
T17	165156	76	0	0
T18	864	10	0	0
T19	961478	2991	0	0
T20	404490	3481	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1497792	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1497792	0	0
T2	3658	50	0	0
T3	388547	2195	0	0
T4	692411	205	0	0
T5	2917	47	0	0
T14	28251	372	0	0
T15	219321	2039	0	0
T17	165156	1821	0	0
T18	864	8	0	0
T19	961478	7767	0	0
T20	404490	4321	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3067903	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3067903	0	0
T2	3658	50	0	0
T3	388547	164691	0	0
T4	692411	50	0	0
T5	2917	47	0	0
T14	28251	166	0	0
T15	219321	1947	0	0
T17	165156	95	0	0
T18	864	8	0	0
T19	961478	2564	0	0
T20	404490	727	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1476394	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1476394	0	0
T2	3658	51	0	0
T3	388547	0	0	0
T4	692411	246	0	0
T5	2917	45	0	0
T14	28251	462	0	0
T15	219321	1708	0	0
T16	0	238	0	0
T17	165156	1168	0	0
T18	864	6	0	0
T19	961478	9206	0	0
T20	404490	3536	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2650467	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2650467	0	0
T2	3658	51	0	0
T3	388547	0	0	0
T4	692411	63	0	0
T5	2917	45	0	0
T14	28251	208	0	0
T15	219321	1713	0	0
T16	0	85	0	0
T17	165156	732	0	0
T18	864	6	0	0
T19	961478	3503	0	0
T20	404490	1000	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1574130	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1574130	0	0
T2	3658	37	0	0
T3	388547	961	0	0
T4	692411	219	0	0
T5	2917	36	0	0
T14	28251	428	0	0
T15	219321	1926	0	0
T17	165156	2756	0	0
T18	864	2	0	0
T19	961478	12286	0	0
T20	404490	4578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3632139	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3632139	0	0
T2	3658	37	0	0
T3	388547	71012	0	0
T4	692411	161	0	0
T5	2917	36	0	0
T14	28251	187	0	0
T15	219321	1896	0	0
T17	165156	466	0	0
T18	864	2	0	0
T19	961478	2689	0	0
T20	404490	1395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1502990	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1502990	0	0
T2	3658	50	0	0
T3	388547	1214	0	0
T4	692411	212	0	0
T5	2917	39	0	0
T14	28251	271	0	0
T15	219321	1793	0	0
T17	165156	2357	0	0
T18	864	11	0	0
T19	961478	16364	0	0
T20	404490	2561	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3491216	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3491216	0	0
T2	3658	50	0	0
T3	388547	86987	0	0
T4	692411	52	0	0
T5	2917	39	0	0
T14	28251	133	0	0
T15	219321	1592	0	0
T17	165156	1358	0	0
T18	864	11	0	0
T19	961478	5290	0	0
T20	404490	1279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1486603	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1486603	0	0
T1	872556	1410	0	0
T2	3658	48	0	0
T3	388547	1304	0	0
T4	692411	251	0	0
T5	2917	49	0	0
T14	28251	348	0	0
T15	219321	1770	0	0
T17	165156	2732	0	0
T18	864	4	0	0
T19	961478	14137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2876993	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2876993	0	0
T1	872556	103002	0	0
T2	3658	48	0	0
T3	388547	100551	0	0
T4	692411	58	0	0
T5	2917	49	0	0
T14	28251	163	0	0
T15	219321	1696	0	0
T17	165156	711	0	0
T18	864	4	0	0
T19	961478	4733	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1488865	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1488865	0	0
T2	3658	45	0	0
T3	388547	0	0	0
T4	692411	233	0	0
T5	2917	47	0	0
T14	28251	495	0	0
T15	219321	1838	0	0
T16	0	273	0	0
T17	165156	899	0	0
T18	864	8	0	0
T19	961478	10534	0	0
T20	404490	4324	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3101454	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3101454	0	0
T2	3658	45	0	0
T3	388547	0	0	0
T4	692411	489	0	0
T5	2917	47	0	0
T14	28251	195	0	0
T15	219321	1938	0	0
T16	0	80	0	0
T17	165156	384	0	0
T18	864	8	0	0
T19	961478	5436	0	0
T20	404490	850	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1431185	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1431185	0	0
T2	3658	42	0	0
T3	388547	0	0	0
T4	692411	210	0	0
T5	2917	41	0	0
T14	28251	259	0	0
T15	219321	1674	0	0
T16	0	218	0	0
T17	165156	2323	0	0
T18	864	7	0	0
T19	961478	11337	0	0
T20	404490	2562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3094118	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3094118	0	0
T2	3658	42	0	0
T3	388547	0	0	0
T4	692411	47	0	0
T5	2917	41	0	0
T14	28251	114	0	0
T15	219321	1653	0	0
T16	0	107	0	0
T17	165156	265	0	0
T18	864	7	0	0
T19	961478	4618	0	0
T20	404490	766	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1506050	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1506050	0	0
T2	3658	43	0	0
T3	388547	1253	0	0
T4	692411	148	0	0
T5	2917	56	0	0
T14	28251	260	0	0
T15	219321	1618	0	0
T17	165156	3500	0	0
T18	864	3	0	0
T19	961478	11240	0	0
T20	404490	2066	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3171494	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3171494	0	0
T2	3658	43	0	0
T3	388547	100224	0	0
T4	692411	37	0	0
T5	2917	56	0	0
T14	28251	130	0	0
T15	219321	1430	0	0
T17	165156	1891	0	0
T18	864	3	0	0
T19	961478	4625	0	0
T20	404490	786	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1523004	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1523004	0	0
T2	3658	47	0	0
T3	388547	0	0	0
T4	692411	192	0	0
T5	2917	51	0	0
T14	28251	415	0	0
T15	219321	1889	0	0
T16	0	232	0	0
T17	165156	615	0	0
T18	864	13	0	0
T19	961478	14714	0	0
T20	404490	2745	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2949913	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2949913	0	0
T2	3658	47	0	0
T3	388547	0	0	0
T4	692411	872	0	0
T5	2917	51	0	0
T14	28251	171	0	0
T15	219321	1762	0	0
T16	0	100	0	0
T17	165156	41	0	0
T18	864	13	0	0
T19	961478	6273	0	0
T20	404490	552	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1465799	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1465799	0	0
T2	3658	42	0	0
T3	388547	1346	0	0
T4	692411	186	0	0
T5	2917	50	0	0
T14	28251	289	0	0
T15	219321	1598	0	0
T17	165156	2979	0	0
T18	864	7	0	0
T19	961478	11980	0	0
T20	404490	5056	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3460682	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3460682	0	0
T2	3658	42	0	0
T3	388547	108963	0	0
T4	692411	50	0	0
T5	2917	50	0	0
T14	28251	162	0	0
T15	219321	1505	0	0
T17	165156	925	0	0
T18	864	7	0	0
T19	961478	4682	0	0
T20	404490	2020	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1501694	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1501694	0	0
T2	3658	49	0	0
T3	388547	1268	0	0
T4	692411	174	0	0
T5	2917	43	0	0
T14	28251	387	0	0
T15	219321	1804	0	0
T17	165156	1332	0	0
T18	864	11	0	0
T19	961478	8589	0	0
T20	404490	3553	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	2976014	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	2976014	0	0
T2	3658	49	0	0
T3	388547	95223	0	0
T4	692411	44	0	0
T5	2917	43	0	0
T14	28251	153	0	0
T15	219321	1870	0	0
T17	165156	3	0	0
T18	864	11	0	0
T19	961478	2973	0	0
T20	404490	872	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1552778	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1552778	0	0
T1	872556	1005	0	0
T2	3658	43	0	0
T3	388547	0	0	0
T4	692411	277	0	0
T5	2917	59	0	0
T14	28251	374	0	0
T15	219321	1970	0	0
T17	165156	2192	0	0
T18	864	6	0	0
T19	961478	9555	0	0
T20	0	3796	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3133718	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3133718	0	0
T1	872556	76558	0	0
T2	3658	43	0	0
T3	388547	0	0	0
T4	692411	60	0	0
T5	2917	59	0	0
T14	28251	165	0	0
T15	219321	1880	0	0
T17	165156	1542	0	0
T18	864	6	0	0
T19	961478	1730	0	0
T20	0	3202	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	1514296	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	1514296	0	0
T1	872556	1140	0	0
T2	3658	43	0	0
T3	388547	0	0	0
T4	692411	232	0	0
T5	2917	49	0	0
T14	28251	270	0	0
T15	219321	1757	0	0
T17	165156	4678	0	0
T18	864	5	0	0
T19	961478	12290	0	0
T20	0	7461	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304636071	3744644	0	0
DepthKnown_A	304636071	304515484	0	0
RvalidKnown_A	304636071	304515484	0	0
WreadyKnown_A	304636071	304515484	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	3744644	0	0
T1	872556	86249	0	0
T2	3658	43	0	0
T3	388547	0	0	0
T4	692411	50	0	0
T5	2917	49	0	0
T14	28251	119	0	0
T15	219321	1632	0	0
T17	165156	603	0	0
T18	864	5	0	0
T19	961478	3618	0	0
T20	0	2355	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304636071	304515484	0	0
T1	872556	872504	0	0
T2	3658	3512	0	0
T3	388547	388540	0	0
T4	692411	692365	0	0
T5	2917	2858	0	0
T14	28251	28234	0	0
T15	219321	218931	0	0
T17	165156	165085	0	0
T18	864	810	0	0
T19	961478	961431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0