Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1630911	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255484

1

T1

88

T2

198

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	638917	1			T1	411		T2	487		T3	36
values[0x0]	609224	1			T1	72		T2	500		T3	40
values[0x1]	638254	1			T1	398		T2	522		T3	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1263991	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

622404

1

T1

335

T2

499

T3

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7653	1			T1	1		T13	3		T14	15
valid_sources[0x01]	7397	1			T1	7		T14	17		T16	15
valid_sources[0x02]	7118	1			T1	3		T13	2		T14	15
valid_sources[0x03]	7538	1			T1	3		T14	15		T16	9
valid_sources[0x04]	6974	1			T1	8		T13	7		T14	16
valid_sources[0x05]	8366	1			T1	2		T13	1		T14	16
valid_sources[0x06]	6641	1			T1	13		T14	17		T16	4
valid_sources[0x07]	6890	1			T1	1		T14	17		T16	4
valid_sources[0x08]	6782	1			T1	6		T13	2		T14	16
valid_sources[0x09]	7381	1			T1	4		T13	3		T14	16
valid_sources[0x0a]	7022	1			T1	1		T13	2		T14	14
valid_sources[0x0b]	7464	1			T1	6		T13	1		T14	16
valid_sources[0x0c]	7688	1			T1	3		T4	17		T11	1
valid_sources[0x0d]	7111	1			T1	6		T13	2		T14	15
valid_sources[0x0e]	7122	1			T13	1		T14	16		T15	1
valid_sources[0x0f]	7890	1			T1	4		T11	1		T13	1
valid_sources[0x10]	6815	1			T1	6		T11	1		T13	1
valid_sources[0x11]	8116	1			T13	3		T14	15		T16	9
valid_sources[0x12]	6884	1			T1	11		T11	1		T13	5
valid_sources[0x13]	7434	1			T1	7		T11	1		T13	1
valid_sources[0x14]	7621	1			T1	9		T13	1		T14	16
valid_sources[0x15]	7392	1			T1	7		T13	3		T14	18
valid_sources[0x16]	7113	1			T1	3		T13	3		T14	17
valid_sources[0x17]	7003	1			T1	4		T13	3		T14	16
valid_sources[0x18]	7427	1			T1	5		T13	4		T14	17
valid_sources[0x19]	7129	1			T1	5		T13	1		T14	19
valid_sources[0x1a]	7332	1			T1	5		T13	4		T14	16
valid_sources[0x1b]	6918	1			T1	1		T13	1		T14	17
valid_sources[0x1c]	7697	1			T1	8		T13	3		T14	13
valid_sources[0x1d]	7934	1			T1	3		T13	2		T14	15
valid_sources[0x1e]	7103	1			T1	3		T2	88		T13	1
valid_sources[0x1f]	6623	1			T1	2		T13	5		T14	15
valid_sources[0x20]	7414	1			T1	2		T13	1		T14	16
valid_sources[0x21]	9309	1			T1	3		T14	17		T16	12
valid_sources[0x22]	7771	1			T2	280		T14	17		T16	13
valid_sources[0x23]	6817	1			T1	7		T13	1		T14	17
valid_sources[0x24]	6406	1			T1	7		T14	15		T16	13
valid_sources[0x25]	8224	1			T1	4		T4	4		T13	3
valid_sources[0x26]	7424	1			T1	2		T13	2		T14	14
valid_sources[0x27]	7778	1			T1	6		T2	95		T13	3
valid_sources[0x28]	6913	1			T1	4		T13	8		T14	17
valid_sources[0x29]	7302	1			T1	4		T13	4		T14	14
valid_sources[0x2a]	7666	1			T1	2		T13	1		T14	18
valid_sources[0x2b]	7164	1			T1	2		T13	3		T14	16
valid_sources[0x2c]	7243	1			T1	3		T13	3		T14	15
valid_sources[0x2d]	6592	1			T1	3		T13	3		T14	16
valid_sources[0x2e]	8006	1			T1	1		T13	3		T14	16
valid_sources[0x2f]	6983	1			T1	1		T13	1		T14	17
valid_sources[0x30]	8024	1			T1	3		T13	2		T14	18
valid_sources[0x31]	8120	1			T1	3		T14	15		T16	7
valid_sources[0x32]	7983	1			T1	3		T13	2		T14	16
valid_sources[0x33]	8751	1			T1	1		T14	16		T16	3
valid_sources[0x34]	7849	1			T1	2		T13	4		T14	14
valid_sources[0x35]	7564	1			T1	6		T13	5		T14	17
valid_sources[0x36]	7142	1			T1	2		T13	1		T14	16
valid_sources[0x37]	7475	1			T1	5		T13	3		T14	15
valid_sources[0x38]	7284	1			T1	2		T4	1		T13	1
valid_sources[0x39]	7717	1			T1	4		T13	1		T14	16
valid_sources[0x3a]	7542	1			T1	2		T13	1		T14	16
valid_sources[0x3b]	7935	1			T1	5		T13	1		T14	15
valid_sources[0x3c]	6835	1			T1	3		T14	17		T16	8
valid_sources[0x3d]	7209	1			T1	9		T13	6		T14	16
valid_sources[0x3e]	7346	1			T1	2		T14	15		T16	15
valid_sources[0x3f]	7594	1			T1	3		T14	17		T16	11
valid_sources[0x40]	7117	1			T1	4		T13	4		T14	17
valid_sources[0x41]	7872	1			T1	3		T13	3		T14	20
valid_sources[0x42]	6661	1			T1	3		T13	2		T14	17
valid_sources[0x43]	7430	1			T1	7		T13	2		T14	15
valid_sources[0x44]	7481	1			T1	8		T13	1		T14	18
valid_sources[0x45]	7510	1			T14	17		T15	2		T16	4
valid_sources[0x46]	6619	1			T1	2		T11	2		T13	1
valid_sources[0x47]	7000	1			T1	5		T13	2		T14	17
valid_sources[0x48]	6816	1			T1	2		T11	1		T13	2
valid_sources[0x49]	7195	1			T1	3		T13	5		T14	18
valid_sources[0x4a]	7273	1			T1	4		T13	3		T14	15
valid_sources[0x4b]	8423	1			T1	1		T13	2		T14	16
valid_sources[0x4c]	7001	1			T13	2		T14	16		T16	5
valid_sources[0x4d]	7019	1			T1	5		T13	3		T14	16
valid_sources[0x4e]	7128	1			T1	4		T13	3		T14	16
valid_sources[0x4f]	6816	1			T1	13		T4	10		T13	2
valid_sources[0x50]	7618	1			T1	2		T13	6		T14	16
valid_sources[0x51]	8787	1			T1	2		T11	1		T13	3
valid_sources[0x52]	7458	1			T1	4		T13	1		T14	17
valid_sources[0x53]	7801	1			T1	2		T13	3		T14	18
valid_sources[0x54]	6942	1			T1	1		T14	17		T16	15
valid_sources[0x55]	7162	1			T1	6		T13	5		T14	16
valid_sources[0x56]	7274	1			T1	1		T14	16		T16	13
valid_sources[0x57]	7931	1			T1	3		T13	2		T14	16
valid_sources[0x58]	7007	1			T1	1		T13	1		T14	16
valid_sources[0x59]	7652	1			T1	7		T13	1		T14	15
valid_sources[0x5a]	7945	1			T1	6		T11	1		T13	6
valid_sources[0x5b]	7978	1			T1	2		T13	3		T14	17
valid_sources[0x5c]	7020	1			T1	2		T14	16		T16	3
valid_sources[0x5d]	8870	1			T1	3		T13	1		T14	14
valid_sources[0x5e]	7265	1			T1	3		T14	16		T16	8
valid_sources[0x5f]	6991	1			T1	8		T13	1		T14	16
valid_sources[0x60]	7267	1			T1	1		T13	3		T14	16
valid_sources[0x61]	7364	1			T1	8		T14	14		T16	9
valid_sources[0x62]	6883	1			T1	8		T13	2		T14	16
valid_sources[0x63]	7331	1			T13	2		T14	18		T16	6
valid_sources[0x64]	7355	1			T1	4		T13	3		T14	18
valid_sources[0x65]	7270	1			T1	2		T13	2		T14	19
valid_sources[0x66]	10047	1			T1	4		T4	35		T13	6
valid_sources[0x67]	7418	1			T1	1		T4	11		T13	1
valid_sources[0x68]	8218	1			T1	2		T13	2		T14	16
valid_sources[0x69]	7295	1			T1	1		T4	3		T14	17
valid_sources[0x6a]	7873	1			T1	2		T13	4		T14	16
valid_sources[0x6b]	7882	1			T1	5		T13	4		T14	14
valid_sources[0x6c]	7141	1			T13	1		T14	16		T16	9
valid_sources[0x6d]	7462	1			T1	3		T11	1		T14	14
valid_sources[0x6e]	6877	1			T1	2		T14	16		T15	5
valid_sources[0x6f]	7341	1			T1	6		T13	2		T14	16
valid_sources[0x70]	7238	1			T1	2		T13	3		T14	18
valid_sources[0x71]	7264	1			T1	3		T14	15		T16	9
valid_sources[0x72]	7438	1			T1	5		T4	16		T13	4
valid_sources[0x73]	7857	1			T1	8		T13	2		T14	14
valid_sources[0x74]	7766	1			T1	2		T4	12		T13	4
valid_sources[0x75]	7302	1			T1	4		T11	1		T13	4
valid_sources[0x76]	7559	1			T1	2		T4	8		T13	2
valid_sources[0x77]	7145	1			T1	2		T13	2		T14	15
valid_sources[0x78]	6492	1			T1	4		T13	5		T14	17
valid_sources[0x79]	7524	1			T1	3		T14	18		T15	8
valid_sources[0x7a]	8170	1			T1	3		T14	17		T16	17
valid_sources[0x7b]	7248	1			T1	6		T14	17		T16	8
valid_sources[0x7c]	7195	1			T1	4		T4	11		T11	1
valid_sources[0x7d]	7374	1			T1	3		T2	99		T13	2
valid_sources[0x7e]	7080	1			T1	5		T4	10		T13	2
valid_sources[0x7f]	7070	1			T1	1		T13	3		T14	15
valid_sources[0x80]	7296	1			T1	4		T14	16		T15	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26816

1

T1

22

T2

20

T3

2

values[0x0]

all_enables

biggest_size

201996

1

T1

33

T2

155

T3

9

values[0x1]

all_enables

biggest_size

26672

1

T1

33

T2

23

T3

1