Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	353560758	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	353560758	0	0
T1	26142816	472559	0	0
T2	169176	7396	0	0
T3	34944	577	0	0
T4	257488	4781	0	0
T10	0	2440	0	0
T11	559216	12539	0	0
T13	81256	2412	0	0
T14	19994800	1657570	0	0
T15	159936	2797	0	0
T16	175112	10432	0	0
T17	120064	3196	0	0
T18	0	10287	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	26142816	26062008	0	0
T2	169176	168000	0	0
T3	34944	31584	0	0
T4	257488	255808	0	0
T11	559216	555240	0	0
T13	81256	78120	0	0
T14	19994800	19994632	0	0
T15	159936	158648	0	0
T16	175112	170408	0	0
T17	120064	116480	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	26142816	26062008	0	0
T2	169176	168000	0	0
T3	34944	31584	0	0
T4	257488	255808	0	0
T11	559216	555240	0	0
T13	81256	78120	0	0
T14	19994800	19994632	0	0
T15	159936	158648	0	0
T16	175112	170408	0	0
T17	120064	116480	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	26142816	26062008	0	0
T2	169176	168000	0	0
T3	34944	31584	0	0
T4	257488	255808	0	0
T11	559216	555240	0	0
T13	81256	78120	0	0
T14	19994800	19994632	0	0
T15	159936	158648	0	0
T16	175112	170408	0	0
T17	120064	116480	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T11	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	127376001	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	127376001	0	0
T1	466836	197732	0	0
T2	3021	2869	0	0
T3	624	223	0	0
T4	4598	1992	0	0
T11	9986	5181	0	0
T13	1451	944	0	0
T14	357050	18904	0	0
T15	2856	1229	0	0
T16	3127	2608	0	0
T17	2144	800	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	93962797	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	93962797	0	0
T1	466836	70708	0	0
T2	3021	1509	0	0
T3	624	118	0	0
T4	4598	681	0	0
T11	9986	3738	0	0
T13	1451	490	0	0
T14	357050	147251	0	0
T15	2856	378	0	0
T16	3127	2608	0	0
T17	2144	800	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1424811	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1424811	0	0
T1	466836	4729	0	0
T2	3021	47	0	0
T3	624	8	0	0
T4	4598	33	0	0
T10	0	56	0	0
T11	9986	81	0	0
T13	1451	12	0	0
T14	357050	0	0	0
T15	2856	19	0	0
T16	3127	213	0	0
T17	2144	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3197268	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3197268	0	0
T1	466836	2291	0	0
T2	3021	47	0	0
T3	624	8	0	0
T4	4598	19	0	0
T10	0	56	0	0
T11	9986	88	0	0
T13	1451	12	0	0
T14	357050	0	0	0
T15	2856	6	0	0
T16	3127	213	0	0
T17	2144	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1477651	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1477651	0	0
T1	466836	7272	0	0
T2	3021	40	0	0
T3	624	4	0	0
T4	4598	112	0	0
T11	9986	46	0	0
T13	1451	17	0	0
T14	357050	1163	0	0
T15	2856	17	0	0
T16	3127	266	0	0
T17	2144	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	2937847	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	2937847	0	0
T1	466836	4187	0	0
T2	3021	40	0	0
T3	624	4	0	0
T4	4598	49	0	0
T11	9986	29	0	0
T13	1451	17	0	0
T14	357050	91046	0	0
T15	2856	4	0	0
T16	3127	266	0	0
T17	2144	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1464076	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1464076	0	0
T1	466836	4437	0	0
T2	3021	68	0	0
T3	624	3	0	0
T4	4598	11	0	0
T10	0	43	0	0
T11	9986	74	0	0
T13	1451	16	0	0
T14	357050	0	0	0
T15	2856	8	0	0
T16	3127	212	0	0
T17	2144	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3515114	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3515114	0	0
T1	466836	2069	0	0
T2	3021	68	0	0
T3	624	3	0	0
T4	4598	17	0	0
T10	0	43	0	0
T11	9986	96	0	0
T13	1451	16	0	0
T14	357050	0	0	0
T15	2856	6	0	0
T16	3127	212	0	0
T17	2144	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1508177	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1508177	0	0
T1	466836	7484	0	0
T2	3021	54	0	0
T3	624	5	0	0
T4	4598	59	0	0
T11	9986	48	0	0
T13	1451	23	0	0
T14	357050	1218	0	0
T15	2856	35	0	0
T16	3127	264	0	0
T17	2144	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3431498	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3431498	0	0
T1	466836	3924	0	0
T2	3021	54	0	0
T3	624	5	0	0
T4	4598	68	0	0
T11	9986	63	0	0
T13	1451	23	0	0
T14	357050	89895	0	0
T15	2856	11	0	0
T16	3127	264	0	0
T17	2144	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1409691	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1409691	0	0
T1	466836	4168	0	0
T2	3021	40	0	0
T3	624	5	0	0
T4	4598	92	0	0
T10	0	59	0	0
T11	9986	66	0	0
T13	1451	16	0	0
T14	357050	0	0	0
T15	2856	26	0	0
T16	3127	0	0	0
T17	2144	23	0	0
T18	0	838	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3371775	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3371775	0	0
T1	466836	1912	0	0
T2	3021	40	0	0
T3	624	5	0	0
T4	4598	30	0	0
T10	0	59	0	0
T11	9986	80	0	0
T13	1451	16	0	0
T14	357050	0	0	0
T15	2856	17	0	0
T16	3127	0	0	0
T17	2144	23	0	0
T18	0	399	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1491822	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1491822	0	0
T1	466836	5833	0	0
T2	3021	66	0	0
T3	624	5	0	0
T4	4598	36	0	0
T10	0	52	0	0
T11	9986	85	0	0
T13	1451	21	0	0
T14	357050	1309	0	0
T15	2856	12	0	0
T16	3127	0	0	0
T17	2144	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3357082	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3357082	0	0
T1	466836	2619	0	0
T2	3021	66	0	0
T3	624	5	0	0
T4	4598	12	0	0
T10	0	52	0	0
T11	9986	144	0	0
T13	1451	21	0	0
T14	357050	97729	0	0
T15	2856	4	0	0
T16	3127	0	0	0
T17	2144	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1430655	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1430655	0	0
T1	466836	4106	0	0
T2	3021	61	0	0
T3	624	3	0	0
T4	4598	91	0	0
T10	0	52	0	0
T11	9986	80	0	0
T13	1451	19	0	0
T14	357050	2071	0	0
T15	2856	17	0	0
T16	3127	0	0	0
T17	2144	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3642126	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3642126	0	0
T1	466836	2402	0	0
T2	3021	61	0	0
T3	624	3	0	0
T4	4598	21	0	0
T10	0	52	0	0
T11	9986	86	0	0
T13	1451	19	0	0
T14	357050	171778	0	0
T15	2856	2	0	0
T16	3127	0	0	0
T17	2144	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1397033	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1397033	0	0
T1	466836	4839	0	0
T2	3021	46	0	0
T3	624	2	0	0
T4	4598	28	0	0
T10	0	61	0	0
T11	9986	89	0	0
T13	1451	17	0	0
T14	357050	0	0	0
T15	2856	23	0	0
T16	3127	0	0	0
T17	2144	36	0	0
T18	0	735	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	2993386	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	2993386	0	0
T1	466836	2203	0	0
T2	3021	46	0	0
T3	624	2	0	0
T4	4598	32	0	0
T10	0	61	0	0
T11	9986	66	0	0
T13	1451	17	0	0
T14	357050	0	0	0
T15	2856	17	0	0
T16	3127	0	0	0
T17	2144	36	0	0
T18	0	369	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1471586	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1471586	0	0
T1	466836	4778	0	0
T2	3021	59	0	0
T3	624	2	0	0
T4	4598	85	0	0
T10	0	52	0	0
T11	9986	67	0	0
T13	1451	17	0	0
T14	357050	1024	0	0
T15	2856	42	0	0
T16	3127	0	0	0
T17	2144	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	4625702	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	4625702	0	0
T1	466836	2169	0	0
T2	3021	59	0	0
T3	624	2	0	0
T4	4598	18	0	0
T10	0	52	0	0
T11	9986	65	0	0
T13	1451	17	0	0
T14	357050	90221	0	0
T15	2856	41	0	0
T16	3127	0	0	0
T17	2144	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1482771	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1482771	0	0
T1	466836	4848	0	0
T2	3021	56	0	0
T3	624	5	0	0
T4	4598	45	0	0
T10	0	52	0	0
T11	9986	43	0	0
T13	1451	22	0	0
T14	357050	0	0	0
T15	2856	37	0	0
T16	3127	0	0	0
T17	2144	27	0	0
T18	0	734	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	2968201	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	2968201	0	0
T1	466836	2250	0	0
T2	3021	56	0	0
T3	624	5	0	0
T4	4598	11	0	0
T10	0	52	0	0
T11	9986	45	0	0
T13	1451	22	0	0
T14	357050	0	0	0
T15	2856	23	0	0
T16	3127	0	0	0
T17	2144	27	0	0
T18	0	265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1437276	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1437276	0	0
T1	466836	4397	0	0
T2	3021	59	0	0
T3	624	4	0	0
T4	4598	67	0	0
T10	0	44	0	0
T11	9986	54	0	0
T13	1451	16	0	0
T14	357050	0	0	0
T15	2856	13	0	0
T16	3127	293	0	0
T17	2144	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3154981	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3154981	0	0
T1	466836	1954	0	0
T2	3021	59	0	0
T3	624	4	0	0
T4	4598	28	0	0
T10	0	44	0	0
T11	9986	75	0	0
T13	1451	16	0	0
T14	357050	0	0	0
T15	2856	4	0	0
T16	3127	293	0	0
T17	2144	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1547111	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1547111	0	0
T1	466836	5916	0	0
T2	3021	59	0	0
T3	624	3	0	0
T4	4598	94	0	0
T10	0	64	0	0
T11	9986	114	0	0
T13	1451	16	0	0
T14	357050	1083	0	0
T15	2856	61	0	0
T16	3127	0	0	0
T17	2144	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3801302	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3801302	0	0
T1	466836	2553	0	0
T2	3021	59	0	0
T3	624	3	0	0
T4	4598	17	0	0
T10	0	64	0	0
T11	9986	72	0	0
T13	1451	16	0	0
T14	357050	85794	0	0
T15	2856	27	0	0
T16	3127	0	0	0
T17	2144	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1524746	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1524746	0	0
T1	466836	4456	0	0
T2	3021	43	0	0
T3	624	4	0	0
T4	4598	41	0	0
T10	0	61	0	0
T11	9986	39	0	0
T13	1451	17	0	0
T14	357050	1254	0	0
T15	2856	46	0	0
T16	3127	0	0	0
T17	2144	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	4563160	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	4563160	0	0
T1	466836	2194	0	0
T2	3021	43	0	0
T3	624	4	0	0
T4	4598	32	0	0
T10	0	61	0	0
T11	9986	36	0	0
T13	1451	17	0	0
T14	357050	94116	0	0
T15	2856	22	0	0
T16	3127	0	0	0
T17	2144	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1441152	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1441152	0	0
T1	466836	4779	0	0
T2	3021	60	0	0
T3	624	4	0	0
T4	4598	19	0	0
T10	0	43	0	0
T11	9986	13	0	0
T13	1451	18	0	0
T14	357050	1325	0	0
T15	2856	43	0	0
T16	3127	0	0	0
T17	2144	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3628189	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3628189	0	0
T1	466836	2316	0	0
T2	3021	60	0	0
T3	624	4	0	0
T4	4598	27	0	0
T10	0	43	0	0
T11	9986	44	0	0
T13	1451	18	0	0
T14	357050	103487	0	0
T15	2856	4	0	0
T16	3127	0	0	0
T17	2144	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1423504	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1423504	0	0
T1	466836	4718	0	0
T2	3021	49	0	0
T3	624	3	0	0
T4	4598	45	0	0
T10	0	52	0	0
T11	9986	74	0	0
T13	1451	22	0	0
T14	357050	0	0	0
T15	2856	75	0	0
T16	3127	0	0	0
T17	2144	22	0	0
T18	0	873	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	2680139	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	2680139	0	0
T1	466836	2870	0	0
T2	3021	49	0	0
T3	624	3	0	0
T4	4598	22	0	0
T10	0	52	0	0
T11	9986	69	0	0
T13	1451	22	0	0
T14	357050	0	0	0
T15	2856	17	0	0
T16	3127	0	0	0
T17	2144	22	0	0
T18	0	337	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1441281	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1441281	0	0
T1	466836	3334	0	0
T2	3021	68	0	0
T3	624	7	0	0
T4	4598	46	0	0
T10	0	44	0	0
T11	9986	52	0	0
T13	1451	17	0	0
T14	357050	0	0	0
T15	2856	66	0	0
T16	3127	0	0	0
T17	2144	23	0	0
T18	0	828	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	2924370	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	2924370	0	0
T1	466836	1658	0	0
T2	3021	68	0	0
T3	624	7	0	0
T4	4598	35	0	0
T10	0	44	0	0
T11	9986	24	0	0
T13	1451	17	0	0
T14	357050	0	0	0
T15	2856	23	0	0
T16	3127	0	0	0
T17	2144	23	0	0
T18	0	320	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1452782	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1452782	0	0
T1	466836	2582	0	0
T2	3021	71	0	0
T3	624	3	0	0
T4	4598	31	0	0
T10	0	57	0	0
T11	9986	106	0	0
T13	1451	17	0	0
T14	357050	2367	0	0
T15	2856	10	0	0
T16	3127	0	0	0
T17	2144	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3284131	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3284131	0	0
T1	466836	1184	0	0
T2	3021	71	0	0
T3	624	3	0	0
T4	4598	24	0	0
T10	0	57	0	0
T11	9986	100	0	0
T13	1451	17	0	0
T14	357050	178770	0	0
T15	2856	5	0	0
T16	3127	0	0	0
T17	2144	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1478968	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1478968	0	0
T1	466836	2831	0	0
T2	3021	61	0	0
T3	624	6	0	0
T4	4598	59	0	0
T10	0	60	0	0
T11	9986	38	0	0
T13	1451	17	0	0
T14	357050	0	0	0
T15	2856	29	0	0
T16	3127	297	0	0
T17	2144	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3305709	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3305709	0	0
T1	466836	1448	0	0
T2	3021	61	0	0
T3	624	6	0	0
T4	4598	37	0	0
T10	0	60	0	0
T11	9986	18	0	0
T13	1451	17	0	0
T14	357050	0	0	0
T15	2856	6	0	0
T16	3127	297	0	0
T17	2144	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1454300	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1454300	0	0
T1	466836	2674	0	0
T2	3021	45	0	0
T3	624	5	0	0
T4	4598	28	0	0
T10	0	52	0	0
T11	9986	72	0	0
T13	1451	18	0	0
T14	357050	0	0	0
T15	2856	21	0	0
T16	3127	0	0	0
T17	2144	27	0	0
T18	0	770	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3988275	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3988275	0	0
T1	466836	1243	0	0
T2	3021	45	0	0
T3	624	5	0	0
T4	4598	8	0	0
T10	0	52	0	0
T11	9986	40	0	0
T13	1451	18	0	0
T14	357050	0	0	0
T15	2856	18	0	0
T16	3127	0	0	0
T17	2144	27	0	0
T18	0	333	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1410996	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1410996	0	0
T1	466836	5168	0	0
T2	3021	59	0	0
T3	624	3	0	0
T4	4598	65	0	0
T10	0	42	0	0
T11	9986	96	0	0
T13	1451	16	0	0
T14	357050	0	0	0
T15	2856	10	0	0
T16	3127	267	0	0
T17	2144	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3889002	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3889002	0	0
T1	466836	3382	0	0
T2	3021	59	0	0
T3	624	3	0	0
T4	4598	39	0	0
T10	0	42	0	0
T11	9986	104	0	0
T13	1451	16	0	0
T14	357050	0	0	0
T15	2856	1	0	0
T16	3127	267	0	0
T17	2144	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1421255	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1421255	0	0
T1	466836	6742	0	0
T2	3021	58	0	0
T3	624	4	0	0
T4	4598	40	0	0
T10	0	50	0	0
T11	9986	65	0	0
T13	1451	21	0	0
T14	357050	1136	0	0
T15	2856	39	0	0
T16	3127	0	0	0
T17	2144	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3121765	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3121765	0	0
T1	466836	3749	0	0
T2	3021	58	0	0
T3	624	4	0	0
T4	4598	28	0	0
T10	0	50	0	0
T11	9986	97	0	0
T13	1451	21	0	0
T14	357050	86047	0	0
T15	2856	30	0	0
T16	3127	0	0	0
T17	2144	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1434353	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1434353	0	0
T1	466836	5260	0	0
T2	3021	46	0	0
T3	624	3	0	0
T4	4598	64	0	0
T10	0	57	0	0
T11	9986	79	0	0
T13	1451	23	0	0
T14	357050	1355	0	0
T15	2856	26	0	0
T16	3127	0	0	0
T17	2144	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	4152461	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	4152461	0	0
T1	466836	2359	0	0
T2	3021	46	0	0
T3	624	3	0	0
T4	4598	18	0	0
T10	0	57	0	0
T11	9986	71	0	0
T13	1451	23	0	0
T14	357050	98315	0	0
T15	2856	18	0	0
T16	3127	0	0	0
T17	2144	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1440042	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1440042	0	0
T1	466836	4493	0	0
T2	3021	55	0	0
T3	624	4	0	0
T4	4598	25	0	0
T11	9986	50	0	0
T13	1451	17	0	0
T14	357050	1200	0	0
T15	2856	9	0	0
T16	3127	259	0	0
T17	2144	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	4084493	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	4084493	0	0
T1	466836	2185	0	0
T2	3021	55	0	0
T3	624	4	0	0
T4	4598	24	0	0
T11	9986	77	0	0
T13	1451	17	0	0
T14	357050	95928	0	0
T15	2856	17	0	0
T16	3127	259	0	0
T17	2144	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1447460	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1447460	0	0
T1	466836	8603	0	0
T2	3021	54	0	0
T3	624	4	0	0
T4	4598	12	0	0
T10	0	50	0	0
T11	9986	42	0	0
T13	1451	20	0	0
T14	357050	0	0	0
T15	2856	55	0	0
T16	3127	0	0	0
T17	2144	28	0	0
T18	0	620	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	2859016	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	2859016	0	0
T1	466836	4225	0	0
T2	3021	54	0	0
T3	624	4	0	0
T4	4598	15	0	0
T10	0	50	0	0
T11	9986	61	0	0
T13	1451	20	0	0
T14	357050	0	0	0
T15	2856	26	0	0
T16	3127	0	0	0
T17	2144	28	0	0
T18	0	312	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1409852	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1409852	0	0
T1	466836	2669	0	0
T2	3021	57	0	0
T3	624	8	0	0
T4	4598	92	0	0
T11	9986	66	0	0
T13	1451	15	0	0
T14	357050	2399	0	0
T15	2856	15	0	0
T16	3127	537	0	0
T17	2144	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	2987827	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	2987827	0	0
T1	466836	1141	0	0
T2	3021	57	0	0
T3	624	8	0	0
T4	4598	22	0	0
T11	9986	63	0	0
T13	1451	15	0	0
T14	357050	189385	0	0
T15	2856	14	0	0
T16	3127	537	0	0
T17	2144	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1446826	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1446826	0	0
T1	466836	8248	0	0
T2	3021	61	0	0
T3	624	6	0	0
T4	4598	50	0	0
T10	0	62	0	0
T11	9986	97	0	0
T13	1451	16	0	0
T14	357050	0	0	0
T15	2856	36	0	0
T16	3127	0	0	0
T17	2144	41	0	0
T18	0	818	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	3500465	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	3500465	0	0
T1	466836	3743	0	0
T2	3021	61	0	0
T3	624	6	0	0
T4	4598	8	0	0
T10	0	62	0	0
T11	9986	79	0	0
T13	1451	16	0	0
T14	357050	0	0	0
T15	2856	5	0	0
T16	3127	0	0	0
T17	2144	41	0	0
T18	0	348	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	1527424	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	1527424	0	0
T1	466836	6646	0	0
T2	3021	67	0	0
T3	624	5	0	0
T4	4598	57	0	0
T10	0	55	0	0
T11	9986	41	0	0
T13	1451	23	0	0
T14	357050	0	0	0
T15	2856	22	0	0
T16	3127	0	0	0
T17	2144	30	0	0
T18	0	968	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316908310	2959075	0	0
DepthKnown_A	316908310	316794018	0	0
RvalidKnown_A	316908310	316794018	0	0
WreadyKnown_A	316908310	316794018	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	2959075	0	0
T1	466836	3879	0	0
T2	3021	67	0	0
T3	624	5	0	0
T4	4598	20	0	0
T10	0	55	0	0
T11	9986	51	0	0
T13	1451	23	0	0
T14	357050	0	0	0
T15	2856	10	0	0
T16	3127	0	0	0
T17	2144	30	0	0
T18	0	420	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316908310	316794018	0	0
T1	466836	465393	0	0
T2	3021	3000	0	0
T3	624	564	0	0
T4	4598	4568	0	0
T11	9986	9915	0	0
T13	1451	1395	0	0
T14	357050	357047	0	0
T15	2856	2833	0	0
T16	3127	3043	0	0
T17	2144	2080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0