Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1615648	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253494

1

T1

161

T2

47

T3

45

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	631186	1			T1	440		T2	136		T3	114
values[0x0]	606474	1			T1	412		T2	145		T3	121
values[0x1]	631482	1			T1	428		T2	129		T3	107

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1253082	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

616060

1

T1

393

T2

124

T3

112

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7149	1			T1	6		T4	15		T5	2
valid_sources[0x01]	7306	1			T1	7		T2	5		T4	5
valid_sources[0x02]	7916	1			T1	6		T3	14		T4	7
valid_sources[0x03]	6381	1			T1	3		T4	1		T5	1
valid_sources[0x04]	6684	1			T1	3		T4	15		T5	3
valid_sources[0x05]	6579	1			T1	8		T4	6		T5	1
valid_sources[0x06]	8158	1			T1	2		T4	14		T5	1
valid_sources[0x07]	7021	1			T1	6		T4	5		T18	26
valid_sources[0x08]	7057	1			T1	9		T2	5		T3	18
valid_sources[0x09]	6328	1			T1	4		T4	9		T17	2
valid_sources[0x0a]	7598	1			T1	6		T4	1		T5	1
valid_sources[0x0b]	7350	1			T1	9		T4	7		T18	40
valid_sources[0x0c]	6611	1			T1	5		T2	18		T4	10
valid_sources[0x0d]	7676	1			T1	7		T4	12		T5	4
valid_sources[0x0e]	7316	1			T1	3		T2	30		T4	6
valid_sources[0x0f]	9248	1			T1	9		T4	4		T5	1
valid_sources[0x10]	9932	1			T1	8		T4	5		T5	2
valid_sources[0x11]	6944	1			T1	5		T4	9		T5	1
valid_sources[0x12]	6310	1			T1	8		T4	6		T18	15
valid_sources[0x13]	6924	1			T1	4		T4	9		T5	2
valid_sources[0x14]	8528	1			T1	6		T4	7		T5	3
valid_sources[0x15]	6652	1			T1	3		T3	10		T4	7
valid_sources[0x16]	7426	1			T1	2		T4	13		T5	1
valid_sources[0x17]	7118	1			T1	5		T3	18		T4	2
valid_sources[0x18]	7461	1			T1	5		T4	12		T5	1
valid_sources[0x19]	6200	1			T1	5		T3	10		T4	12
valid_sources[0x1a]	7646	1			T1	4		T4	11		T5	2
valid_sources[0x1b]	8312	1			T1	4		T4	5		T5	4
valid_sources[0x1c]	6752	1			T1	4		T3	9		T4	4
valid_sources[0x1d]	7211	1			T1	4		T4	9		T20	1
valid_sources[0x1e]	6581	1			T1	1		T4	9		T18	23
valid_sources[0x1f]	7906	1			T1	3		T4	10		T5	3
valid_sources[0x20]	8155	1			T1	4		T4	5		T20	5
valid_sources[0x21]	7219	1			T1	3		T4	1		T5	2
valid_sources[0x22]	7066	1			T1	5		T4	16		T20	1
valid_sources[0x23]	6619	1			T1	15		T4	3		T5	4
valid_sources[0x24]	7050	1			T1	3		T4	7		T5	1
valid_sources[0x25]	10262	1			T1	8		T4	9		T5	7
valid_sources[0x26]	7091	1			T1	4		T4	5		T18	31
valid_sources[0x27]	7352	1			T1	4		T2	14		T4	8
valid_sources[0x28]	7433	1			T1	5		T4	9		T5	3
valid_sources[0x29]	7045	1			T1	5		T2	18		T4	2
valid_sources[0x2a]	8336	1			T1	7		T4	8		T5	1
valid_sources[0x2b]	7299	1			T1	6		T4	11		T5	1
valid_sources[0x2c]	7866	1			T1	8		T4	5		T5	2
valid_sources[0x2d]	6927	1			T1	5		T4	6		T17	2
valid_sources[0x2e]	7842	1			T1	7		T4	4		T20	1
valid_sources[0x2f]	7111	1			T1	6		T2	18		T4	5
valid_sources[0x30]	6849	1			T1	5		T4	18		T5	2
valid_sources[0x31]	7143	1			T1	7		T4	18		T5	2
valid_sources[0x32]	7284	1			T1	10		T4	10		T17	2
valid_sources[0x33]	8021	1			T1	4		T4	9		T18	21
valid_sources[0x34]	7033	1			T1	7		T4	3		T17	1
valid_sources[0x35]	7457	1			T1	3		T4	15		T5	5
valid_sources[0x36]	7919	1			T1	6		T3	14		T4	11
valid_sources[0x37]	6775	1			T1	5		T4	2		T5	2
valid_sources[0x38]	7504	1			T1	11		T4	9		T17	2
valid_sources[0x39]	7530	1			T1	4		T4	9		T5	3
valid_sources[0x3a]	6837	1			T1	7		T4	4		T17	1
valid_sources[0x3b]	6738	1			T4	9		T5	5		T20	2
valid_sources[0x3c]	7045	1			T1	3		T4	9		T5	1
valid_sources[0x3d]	7470	1			T1	2		T4	3		T5	2
valid_sources[0x3e]	6816	1			T1	5		T4	3		T5	1
valid_sources[0x3f]	6959	1			T1	7		T4	9		T5	1
valid_sources[0x40]	6537	1			T1	5		T4	10		T5	2
valid_sources[0x41]	8644	1			T1	2		T2	6		T4	15
valid_sources[0x42]	7591	1			T1	6		T4	6		T20	5
valid_sources[0x43]	5912	1			T1	2		T4	6		T5	2
valid_sources[0x44]	6665	1			T1	4		T4	5		T18	22
valid_sources[0x45]	7606	1			T1	8		T2	10		T4	5
valid_sources[0x46]	6692	1			T1	4		T4	5		T18	34
valid_sources[0x47]	8075	1			T1	5		T4	5		T5	1
valid_sources[0x48]	7835	1			T1	2		T4	9		T5	5
valid_sources[0x49]	8419	1			T1	7		T2	18		T4	9
valid_sources[0x4a]	6635	1			T1	4		T4	17		T5	1
valid_sources[0x4b]	8430	1			T1	4		T4	16		T5	1
valid_sources[0x4c]	7131	1			T1	7		T4	10		T18	33
valid_sources[0x4d]	7633	1			T1	6		T4	6		T5	1
valid_sources[0x4e]	7100	1			T1	3		T4	6		T20	1
valid_sources[0x4f]	7666	1			T1	3		T4	14		T18	56
valid_sources[0x50]	6341	1			T1	8		T4	6		T5	1
valid_sources[0x51]	7615	1			T1	6		T4	19		T5	1
valid_sources[0x52]	7798	1			T1	2		T3	13		T4	3
valid_sources[0x53]	9230	1			T1	4		T4	9		T5	7
valid_sources[0x54]	6675	1			T1	3		T4	22		T5	2
valid_sources[0x55]	6886	1			T1	3		T4	5		T5	1
valid_sources[0x56]	7456	1			T1	5		T4	13		T18	29
valid_sources[0x57]	7725	1			T1	6		T4	3		T5	2
valid_sources[0x58]	7313	1			T1	3		T4	2		T17	1
valid_sources[0x59]	6240	1			T1	7		T2	16		T3	8
valid_sources[0x5a]	8156	1			T1	5		T4	5		T5	2
valid_sources[0x5b]	6865	1			T1	5		T4	5		T5	2
valid_sources[0x5c]	7070	1			T1	7		T4	10		T5	1
valid_sources[0x5d]	7651	1			T1	3		T4	18		T20	1
valid_sources[0x5e]	7255	1			T1	8		T4	5		T5	2
valid_sources[0x5f]	7113	1			T1	4		T4	6		T20	1
valid_sources[0x60]	6912	1			T1	3		T4	2		T16	1
valid_sources[0x61]	7300	1			T1	5		T2	7		T4	12
valid_sources[0x62]	6727	1			T1	6		T4	13		T5	1
valid_sources[0x63]	7357	1			T1	2		T4	11		T5	2
valid_sources[0x64]	7392	1			T1	5		T4	29		T18	27
valid_sources[0x65]	7060	1			T1	8		T3	14		T4	13
valid_sources[0x66]	6672	1			T1	7		T2	15		T3	11
valid_sources[0x67]	7060	1			T1	1		T4	3		T5	5
valid_sources[0x68]	8034	1			T1	8		T2	7		T4	15
valid_sources[0x69]	6488	1			T1	6		T4	10		T5	1
valid_sources[0x6a]	7906	1			T1	6		T4	4		T5	4
valid_sources[0x6b]	8098	1			T1	7		T4	8		T20	2
valid_sources[0x6c]	7132	1			T1	5		T4	6		T20	1
valid_sources[0x6d]	7694	1			T1	6		T4	8		T18	46
valid_sources[0x6e]	6457	1			T1	4		T2	7		T4	4
valid_sources[0x6f]	7291	1			T1	6		T4	9		T18	19
valid_sources[0x70]	7157	1			T1	2		T4	6		T5	3
valid_sources[0x71]	6960	1			T1	6		T2	8		T4	20
valid_sources[0x72]	7579	1			T1	5		T4	7		T5	1
valid_sources[0x73]	7027	1			T1	4		T4	6		T5	4
valid_sources[0x74]	6843	1			T1	4		T4	12		T5	1
valid_sources[0x75]	7710	1			T1	8		T2	15		T4	5
valid_sources[0x76]	7113	1			T1	3		T4	16		T5	3
valid_sources[0x77]	6775	1			T1	4		T4	14		T18	49
valid_sources[0x78]	6256	1			T1	8		T4	10		T20	1
valid_sources[0x79]	7155	1			T1	5		T4	6		T5	3
valid_sources[0x7a]	7460	1			T1	5		T4	9		T17	1
valid_sources[0x7b]	7476	1			T1	15		T2	12		T3	14
valid_sources[0x7c]	7902	1			T1	5		T4	18		T18	23
valid_sources[0x7d]	8028	1			T1	7		T4	3		T18	21
valid_sources[0x7e]	6590	1			T1	8		T4	9		T5	3
valid_sources[0x7f]	8591	1			T1	8		T4	3		T5	3
valid_sources[0x80]	8955	1			T1	6		T2	5		T4	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26354

1

T1

25

T2

2

T3

1

values[0x0]

all_enables

biggest_size

200529

1

T1

123

T2

39

T3

39

values[0x1]

all_enables

biggest_size

26611

1

T1

13

T2

6

T3

5