Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	341960540	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	341960540	0	0
T1	6148128	1026190	0	0
T2	946344	13090	0	0
T3	744912	10144	0	0
T4	262864	10622	0	0
T5	9896096	195258	0	0
T16	855568	14710	0	0
T17	5374320	164167	0	0
T18	10210704	190680	0	0
T19	48104	2030	0	0
T20	5116160	169659	0	0
T21	0	6952	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6148128	6147848	0	0
T2	946344	943488	0	0
T3	744912	741888	0	0
T4	262864	258608	0	0
T5	9896096	9887080	0	0
T16	855568	817656	0	0
T17	5374320	5373872	0	0
T18	10210704	10197320	0	0
T19	48104	47600	0	0
T20	5116160	5112968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6148128	6147848	0	0
T2	946344	943488	0	0
T3	744912	741888	0	0
T4	262864	258608	0	0
T5	9896096	9887080	0	0
T16	855568	817656	0	0
T17	5374320	5373872	0	0
T18	10210704	10197320	0	0
T19	48104	47600	0	0
T20	5116160	5112968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6148128	6147848	0	0
T2	946344	943488	0	0
T3	744912	741888	0	0
T4	262864	258608	0	0
T5	9896096	9887080	0	0
T16	855568	817656	0	0
T17	5374320	5373872	0	0
T18	10210704	10197320	0	0
T19	48104	47600	0	0
T20	5116160	5112968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	126678370	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	126678370	0	0
T1	109788	107971	0	0
T2	16899	3273	0	0
T3	13302	2586	0	0
T4	4694	4127	0	0
T5	176716	72679	0	0
T16	15278	6512	0	0
T17	95970	94555	0	0
T18	182334	83907	0	0
T19	859	791	0	0
T20	91360	89827	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	88438327	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	88438327	0	0
T1	109788	456401	0	0
T2	16899	3275	0	0
T3	13302	2486	0	0
T4	4694	2165	0	0
T5	176716	32299	0	0
T16	15278	2058	0	0
T17	95970	34556	0	0
T18	182334	26414	0	0
T19	859	413	0	0
T20	91360	39705	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1448277	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1448277	0	0
T1	109788	212	0	0
T2	16899	120	0	0
T3	13302	114	0	0
T4	4694	82	0	0
T5	176716	666	0	0
T16	15278	279	0	0
T17	95970	26	0	0
T18	182334	3065	0	0
T19	859	9	0	0
T20	91360	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3044197	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3044197	0	0
T1	109788	22030	0	0
T2	16899	91	0	0
T3	13302	124	0	0
T4	4694	82	0	0
T5	176716	445	0	0
T16	15278	141	0	0
T17	95970	1434	0	0
T18	182334	1556	0	0
T19	859	9	0	0
T20	91360	1875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1472380	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1472380	0	0
T1	109788	178	0	0
T2	16899	114	0	0
T3	13302	61	0	0
T4	4694	75	0	0
T5	176716	626	0	0
T16	15278	75	0	0
T17	95970	12	0	0
T18	182334	1342	0	0
T19	859	18	0	0
T20	91360	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	4274856	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	4274856	0	0
T1	109788	15999	0	0
T2	16899	171	0	0
T3	13302	88	0	0
T4	4694	75	0	0
T5	176716	406	0	0
T16	15278	71	0	0
T17	95970	1487	0	0
T18	182334	566	0	0
T19	859	18	0	0
T20	91360	1144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1454403	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1454403	0	0
T1	109788	234	0	0
T2	16899	91	0	0
T3	13302	67	0	0
T4	4694	82	0	0
T5	176716	2282	0	0
T16	15278	174	0	0
T17	95970	18	0	0
T18	182334	1149	0	0
T19	859	10	0	0
T20	91360	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	2872317	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	2872317	0	0
T1	109788	15418	0	0
T2	16899	73	0	0
T3	13302	73	0	0
T4	4694	82	0	0
T5	176716	1271	0	0
T16	15278	116	0	0
T17	95970	391	0	0
T18	182334	542	0	0
T19	859	10	0	0
T20	91360	2551	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1462513	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1462513	0	0
T1	109788	228	0	0
T2	16899	110	0	0
T3	13302	84	0	0
T4	4694	77	0	0
T5	176716	3100	0	0
T16	15278	196	0	0
T17	95970	51	0	0
T18	182334	1284	0	0
T19	859	14	0	0
T20	91360	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3530249	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3530249	0	0
T1	109788	18862	0	0
T2	16899	123	0	0
T3	13302	117	0	0
T4	4694	77	0	0
T5	176716	1635	0	0
T16	15278	104	0	0
T17	95970	3272	0	0
T18	182334	655	0	0
T19	859	14	0	0
T20	91360	861	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1429313	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1429313	0	0
T1	109788	183	0	0
T2	16899	164	0	0
T3	13302	35	0	0
T4	4694	87	0	0
T5	176716	657	0	0
T16	15278	231	0	0
T17	95970	29	0	0
T18	182334	1286	0	0
T19	859	21	0	0
T20	91360	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3012492	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3012492	0	0
T1	109788	15119	0	0
T2	16899	150	0	0
T3	13302	33	0	0
T4	4694	87	0	0
T5	176716	448	0	0
T16	15278	91	0	0
T17	95970	1897	0	0
T18	182334	583	0	0
T19	859	21	0	0
T20	91360	2339	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1435453	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1435453	0	0
T1	109788	162	0	0
T2	16899	107	0	0
T3	13302	91	0	0
T4	4694	85	0	0
T5	176716	974	0	0
T16	15278	200	0	0
T17	95970	11	0	0
T18	182334	1446	0	0
T19	859	15	0	0
T20	91360	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3196015	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3196015	0	0
T1	109788	13149	0	0
T2	16899	102	0	0
T3	13302	93	0	0
T4	4694	85	0	0
T5	176716	552	0	0
T16	15278	132	0	0
T17	95970	276	0	0
T18	182334	664	0	0
T19	859	15	0	0
T20	91360	664	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1440517	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1440517	0	0
T1	109788	176	0	0
T2	16899	124	0	0
T3	13302	66	0	0
T4	4694	84	0	0
T5	176716	2423	0	0
T16	15278	97	0	0
T17	95970	15	0	0
T18	182334	5419	0	0
T19	859	11	0	0
T20	91360	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3412863	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3412863	0	0
T1	109788	16946	0	0
T2	16899	151	0	0
T3	13302	63	0	0
T4	4694	84	0	0
T5	176716	1553	0	0
T16	15278	25	0	0
T17	95970	2041	0	0
T18	182334	2591	0	0
T19	859	11	0	0
T20	91360	2282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1487121	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1487121	0	0
T1	109788	232	0	0
T2	16899	73	0	0
T3	13302	75	0	0
T4	4694	66	0	0
T5	176716	757	0	0
T16	15278	99	0	0
T17	95970	11	0	0
T18	182334	1454	0	0
T19	859	15	0	0
T20	91360	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	2986670	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	2986670	0	0
T1	109788	16653	0	0
T2	16899	76	0	0
T3	13302	97	0	0
T4	4694	66	0	0
T5	176716	432	0	0
T16	15278	68	0	0
T17	95970	1147	0	0
T18	182334	668	0	0
T19	859	15	0	0
T20	91360	2670	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1459572	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1459572	0	0
T1	109788	133	0	0
T2	16899	97	0	0
T3	13302	65	0	0
T4	4694	81	0	0
T5	176716	774	0	0
T16	15278	59	0	0
T17	95970	7	0	0
T18	182334	1648	0	0
T19	859	24	0	0
T20	91360	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3556476	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3556476	0	0
T1	109788	11852	0	0
T2	16899	93	0	0
T3	13302	52	0	0
T4	4694	81	0	0
T5	176716	472	0	0
T16	15278	14	0	0
T17	95970	558	0	0
T18	182334	845	0	0
T19	859	24	0	0
T20	91360	2236	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1451864	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1451864	0	0
T1	109788	253	0	0
T2	16899	135	0	0
T3	13302	155	0	0
T4	4694	71	0	0
T5	176716	758	0	0
T16	15278	304	0	0
T17	95970	28	0	0
T18	182334	1337	0	0
T19	859	14	0	0
T20	91360	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3179006	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3179006	0	0
T1	109788	17441	0	0
T2	16899	144	0	0
T3	13302	119	0	0
T4	4694	71	0	0
T5	176716	436	0	0
T16	15278	116	0	0
T17	95970	820	0	0
T18	182334	475	0	0
T19	859	14	0	0
T20	91360	3293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1400926	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1400926	0	0
T1	109788	276	0	0
T2	16899	118	0	0
T3	13302	117	0	0
T4	4694	75	0	0
T5	176716	822	0	0
T16	15278	149	0	0
T17	95970	17	0	0
T18	182334	3344	0	0
T19	859	18	0	0
T20	91360	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3275623	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3275623	0	0
T1	109788	23264	0	0
T2	16899	119	0	0
T3	13302	75	0	0
T4	4694	75	0	0
T5	176716	536	0	0
T16	15278	66	0	0
T17	95970	1229	0	0
T18	182334	1549	0	0
T19	859	18	0	0
T20	91360	1402	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1464710	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1464710	0	0
T1	109788	187	0	0
T2	16899	101	0	0
T3	13302	54	0	0
T4	4694	76	0	0
T5	176716	3102	0	0
T16	15278	357	0	0
T17	95970	0	0	0
T18	182334	1160	0	0
T19	859	20	0	0
T20	91360	14	0	0
T21	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3020831	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3020831	0	0
T1	109788	13572	0	0
T2	16899	111	0	0
T3	13302	62	0	0
T4	4694	76	0	0
T5	176716	1568	0	0
T16	15278	177	0	0
T17	95970	0	0	0
T18	182334	622	0	0
T19	859	20	0	0
T20	91360	2231	0	0
T21	0	3621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1481563	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1481563	0	0
T1	109788	188	0	0
T2	16899	132	0	0
T3	13302	91	0	0
T4	4694	83	0	0
T5	176716	2316	0	0
T16	15278	94	0	0
T17	95970	41	0	0
T18	182334	2759	0	0
T19	859	17	0	0
T20	91360	0	0	0
T21	0	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	2945695	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	2945695	0	0
T1	109788	13847	0	0
T2	16899	116	0	0
T3	13302	66	0	0
T4	4694	83	0	0
T5	176716	1297	0	0
T16	15278	47	0	0
T17	95970	557	0	0
T18	182334	1536	0	0
T19	859	17	0	0
T20	91360	0	0	0
T21	0	3253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1461386	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1461386	0	0
T1	109788	170	0	0
T2	16899	112	0	0
T3	13302	152	0	0
T4	4694	92	0	0
T5	176716	2626	0	0
T16	15278	113	0	0
T17	95970	6	0	0
T18	182334	3083	0	0
T19	859	13	0	0
T20	91360	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3605211	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3605211	0	0
T1	109788	13797	0	0
T2	16899	110	0	0
T3	13302	113	0	0
T4	4694	92	0	0
T5	176716	1393	0	0
T16	15278	39	0	0
T17	95970	136	0	0
T18	182334	1385	0	0
T19	859	13	0	0
T20	91360	1201	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1421459	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1421459	0	0
T1	109788	211	0	0
T2	16899	109	0	0
T3	13302	148	0	0
T4	4694	83	0	0
T5	176716	2939	0	0
T16	15278	17	0	0
T17	95970	9	0	0
T18	182334	1427	0	0
T19	859	12	0	0
T20	91360	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	2741678	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	2741678	0	0
T1	109788	17906	0	0
T2	16899	105	0	0
T3	13302	110	0	0
T4	4694	83	0	0
T5	176716	1398	0	0
T16	15278	3	0	0
T17	95970	319	0	0
T18	182334	748	0	0
T19	859	12	0	0
T20	91360	801	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1443219	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1443219	0	0
T1	109788	185	0	0
T2	16899	130	0	0
T3	13302	82	0	0
T4	4694	90	0	0
T5	176716	2349	0	0
T16	15278	119	0	0
T17	95970	6	0	0
T18	182334	1531	0	0
T19	859	18	0	0
T20	91360	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	2518914	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	2518914	0	0
T1	109788	17889	0	0
T2	16899	113	0	0
T3	13302	58	0	0
T4	4694	90	0	0
T5	176716	1182	0	0
T16	15278	51	0	0
T17	95970	1091	0	0
T18	182334	673	0	0
T19	859	18	0	0
T20	91360	1003	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1482096	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1482096	0	0
T1	109788	198	0	0
T2	16899	95	0	0
T3	13302	125	0	0
T4	4694	78	0	0
T5	176716	754	0	0
T16	15278	57	0	0
T17	95970	14	0	0
T18	182334	1613	0	0
T19	859	11	0	0
T20	91360	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	4014742	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	4014742	0	0
T1	109788	16383	0	0
T2	16899	132	0	0
T3	13302	110	0	0
T4	4694	78	0	0
T5	176716	477	0	0
T16	15278	42	0	0
T17	95970	494	0	0
T18	182334	801	0	0
T19	859	11	0	0
T20	91360	1637	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1450759	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1450759	0	0
T1	109788	200	0	0
T2	16899	149	0	0
T3	13302	90	0	0
T4	4694	77	0	0
T5	176716	3170	0	0
T16	15278	78	0	0
T17	95970	13	0	0
T18	182334	1752	0	0
T19	859	13	0	0
T20	91360	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3205082	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3205082	0	0
T1	109788	13978	0	0
T2	16899	87	0	0
T3	13302	73	0	0
T4	4694	77	0	0
T5	176716	1344	0	0
T16	15278	44	0	0
T17	95970	1345	0	0
T18	182334	805	0	0
T19	859	13	0	0
T20	91360	575	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1430045	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1430045	0	0
T1	109788	132	0	0
T2	16899	122	0	0
T3	13302	77	0	0
T4	4694	80	0	0
T5	176716	6422	0	0
T16	15278	211	0	0
T17	95970	27	0	0
T18	182334	1416	0	0
T19	859	18	0	0
T20	91360	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	2960420	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	2960420	0	0
T1	109788	15421	0	0
T2	16899	134	0	0
T3	13302	80	0	0
T4	4694	80	0	0
T5	176716	3226	0	0
T16	15278	93	0	0
T17	95970	2331	0	0
T18	182334	615	0	0
T19	859	18	0	0
T20	91360	1007	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1416305	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1416305	0	0
T1	109788	249	0	0
T2	16899	108	0	0
T3	13302	107	0	0
T4	4694	67	0	0
T5	176716	2260	0	0
T16	15278	122	0	0
T17	95970	20	0	0
T18	182334	1658	0	0
T19	859	15	0	0
T20	91360	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3524502	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3524502	0	0
T1	109788	22751	0	0
T2	16899	106	0	0
T3	13302	78	0	0
T4	4694	67	0	0
T5	176716	1085	0	0
T16	15278	45	0	0
T17	95970	2392	0	0
T18	182334	695	0	0
T19	859	15	0	0
T20	91360	720	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1465124	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1465124	0	0
T1	109788	204	0	0
T2	16899	93	0	0
T3	13302	84	0	0
T4	4694	73	0	0
T5	176716	776	0	0
T16	15278	171	0	0
T17	95970	17	0	0
T18	182334	5260	0	0
T19	859	20	0	0
T20	91360	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3216178	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3216178	0	0
T1	109788	14574	0	0
T2	16899	131	0	0
T3	13302	111	0	0
T4	4694	73	0	0
T5	176716	505	0	0
T16	15278	95	0	0
T17	95970	1801	0	0
T18	182334	2295	0	0
T19	859	20	0	0
T20	91360	1134	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1507211	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1507211	0	0
T1	109788	221	0	0
T2	16899	229	0	0
T3	13302	177	0	0
T4	4694	83	0	0
T5	176716	3167	0	0
T16	15278	164	0	0
T17	95970	23	0	0
T18	182334	1557	0	0
T19	859	14	0	0
T20	91360	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3466992	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3466992	0	0
T1	109788	19229	0	0
T2	16899	246	0	0
T3	13302	194	0	0
T4	4694	83	0	0
T5	176716	1415	0	0
T16	15278	57	0	0
T17	95970	2289	0	0
T18	182334	780	0	0
T19	859	14	0	0
T20	91360	1228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1388961	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1388961	0	0
T1	109788	192	0	0
T2	16899	125	0	0
T3	13302	107	0	0
T4	4694	88	0	0
T5	176716	702	0	0
T16	15278	202	0	0
T17	95970	13	0	0
T18	182334	1423	0	0
T19	859	17	0	0
T20	91360	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	2814430	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	2814430	0	0
T1	109788	17121	0	0
T2	16899	101	0	0
T3	13302	79	0	0
T4	4694	88	0	0
T5	176716	481	0	0
T16	15278	93	0	0
T17	95970	1835	0	0
T18	182334	610	0	0
T19	859	17	0	0
T20	91360	1032	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1514374	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1514374	0	0
T1	109788	185	0	0
T2	16899	170	0	0
T3	13302	105	0	0
T4	4694	84	0	0
T5	176716	881	0	0
T16	15278	79	0	0
T17	95970	10	0	0
T18	182334	1353	0	0
T19	859	12	0	0
T20	91360	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3228972	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3228972	0	0
T1	109788	17435	0	0
T2	16899	195	0	0
T3	13302	116	0	0
T4	4694	84	0	0
T5	176716	578	0	0
T16	15278	36	0	0
T17	95970	966	0	0
T18	182334	706	0	0
T19	859	12	0	0
T20	91360	802	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1425455	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1425455	0	0
T1	109788	220	0	0
T2	16899	154	0	0
T3	13302	97	0	0
T4	4694	74	0	0
T5	176716	4970	0	0
T16	15278	326	0	0
T17	95970	29	0	0
T18	182334	1496	0	0
T19	859	15	0	0
T20	91360	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	4048129	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	4048129	0	0
T1	109788	24257	0	0
T2	16899	159	0	0
T3	13302	103	0	0
T4	4694	74	0	0
T5	176716	2800	0	0
T16	15278	150	0	0
T17	95970	2326	0	0
T18	182334	725	0	0
T19	859	15	0	0
T20	91360	1951	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1457896	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1457896	0	0
T1	109788	199	0	0
T2	16899	69	0	0
T3	13302	111	0	0
T4	4694	79	0	0
T5	176716	4686	0	0
T16	15278	75	0	0
T17	95970	31	0	0
T18	182334	1355	0	0
T19	859	18	0	0
T20	91360	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	3028133	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	3028133	0	0
T1	109788	12936	0	0
T2	16899	56	0	0
T3	13302	154	0	0
T4	4694	79	0	0
T5	176716	2265	0	0
T16	15278	25	0	0
T17	95970	1153	0	0
T18	182334	617	0	0
T19	859	18	0	0
T20	91360	646	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	1464465	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	1464465	0	0
T1	109788	209	0	0
T2	16899	121	0	0
T3	13302	49	0	0
T4	4694	93	0	0
T5	176716	3618	0	0
T16	15278	76	0	0
T17	95970	16	0	0
T18	182334	3033	0	0
T19	859	11	0	0
T20	91360	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	313979358	2945803	0	0
DepthKnown_A	313979358	313854319	0	0
RvalidKnown_A	313979358	313854319	0	0
WreadyKnown_A	313979358	313854319	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	2945803	0	0
T1	109788	18572	0	0
T2	16899	75	0	0
T3	13302	45	0	0
T4	4694	93	0	0
T5	176716	2503	0	0
T16	15278	75	0	0
T17	95970	969	0	0
T18	182334	1402	0	0
T19	859	11	0	0
T20	91360	2420	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313979358	313854319	0	0
T1	109788	109783	0	0
T2	16899	16848	0	0
T3	13302	13248	0	0
T4	4694	4618	0	0
T5	176716	176555	0	0
T16	15278	14601	0	0
T17	95970	95962	0	0
T18	182334	182095	0	0
T19	859	850	0	0
T20	91360	91303	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0