Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1705705	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

268126

1

T1

15

T2

357

T3

62

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	668325	1			T1	36		T2	938		T3	162
values[0x0]	636196	1			T1	38		T2	922		T3	165
values[0x1]	669310	1			T1	37		T2	924		T3	183

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1320926	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

652905

1

T1

32

T2

860

T3

150

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7575	1			T16	1		T13	1		T17	13
valid_sources[0x01]	7101	1			T1	2		T16	1		T17	15
valid_sources[0x02]	7206	1			T13	1		T17	14		T15	2
valid_sources[0x03]	8636	1			T3	1		T17	15		T15	10
valid_sources[0x04]	7634	1			T1	5		T2	213		T3	5
valid_sources[0x05]	7138	1			T13	1		T17	13		T15	4
valid_sources[0x06]	7536	1			T3	7		T13	1		T17	16
valid_sources[0x07]	7456	1			T1	2		T17	14		T15	3
valid_sources[0x08]	7689	1			T13	1		T17	17		T15	3
valid_sources[0x09]	6975	1			T13	2		T17	15		T15	9
valid_sources[0x0a]	7373	1			T13	1		T17	16		T15	6
valid_sources[0x0b]	7338	1			T13	1		T17	14		T15	4
valid_sources[0x0c]	8290	1			T17	13		T15	7		T14	5
valid_sources[0x0d]	7863	1			T17	11		T15	7		T14	2
valid_sources[0x0e]	7545	1			T3	3		T17	16		T15	10
valid_sources[0x0f]	6534	1			T17	14		T15	10		T14	4
valid_sources[0x10]	7656	1			T17	14		T15	4		T18	19
valid_sources[0x11]	7866	1			T17	14		T15	5		T14	1
valid_sources[0x12]	7259	1			T1	1		T2	203		T17	13
valid_sources[0x13]	7642	1			T13	1		T17	15		T15	2
valid_sources[0x14]	7519	1			T17	12		T15	5		T14	1
valid_sources[0x15]	7828	1			T13	1		T17	16		T15	6
valid_sources[0x16]	8072	1			T2	76		T16	1		T17	14
valid_sources[0x17]	7524	1			T3	4		T17	14		T15	4
valid_sources[0x18]	7146	1			T2	1		T17	14		T15	3
valid_sources[0x19]	8451	1			T2	3		T17	16		T15	2
valid_sources[0x1a]	8077	1			T3	11		T16	1		T17	14
valid_sources[0x1b]	8033	1			T1	1		T2	50		T13	1
valid_sources[0x1c]	7522	1			T2	66		T3	5		T13	1
valid_sources[0x1d]	8393	1			T2	3		T17	14		T15	7
valid_sources[0x1e]	7414	1			T2	62		T17	13		T15	4
valid_sources[0x1f]	7700	1			T3	7		T17	14		T15	1
valid_sources[0x20]	8080	1			T17	15		T15	4		T14	7
valid_sources[0x21]	7437	1			T13	1		T17	15		T15	3
valid_sources[0x22]	8300	1			T1	3		T16	1		T17	17
valid_sources[0x23]	8309	1			T2	7		T13	1		T17	17
valid_sources[0x24]	8521	1			T3	2		T13	1		T17	13
valid_sources[0x25]	7711	1			T13	2		T17	15		T15	2
valid_sources[0x26]	7387	1			T1	1		T2	36		T13	3
valid_sources[0x27]	7489	1			T1	1		T17	16		T15	3
valid_sources[0x28]	7772	1			T1	5		T3	1		T13	1
valid_sources[0x29]	7767	1			T13	1		T17	16		T15	9
valid_sources[0x2a]	7251	1			T2	3		T3	13		T17	12
valid_sources[0x2b]	7602	1			T17	15		T15	3		T14	21
valid_sources[0x2c]	7804	1			T2	2		T13	4		T17	16
valid_sources[0x2d]	7125	1			T1	1		T2	9		T17	12
valid_sources[0x2e]	7296	1			T17	14		T15	11		T14	18
valid_sources[0x2f]	7955	1			T13	1		T17	16		T15	6
valid_sources[0x30]	7921	1			T16	1		T17	14		T15	6
valid_sources[0x31]	7532	1			T2	12		T3	17		T17	13
valid_sources[0x32]	7840	1			T3	1		T17	12		T15	3
valid_sources[0x33]	7009	1			T2	54		T17	15		T15	10
valid_sources[0x34]	7137	1			T3	3		T13	1		T17	16
valid_sources[0x35]	7867	1			T3	1		T17	16		T15	5
valid_sources[0x36]	7838	1			T17	14		T15	3		T14	18
valid_sources[0x37]	7314	1			T1	3		T17	14		T15	7
valid_sources[0x38]	6742	1			T17	14		T15	5		T14	10
valid_sources[0x39]	7285	1			T13	1		T17	14		T15	3
valid_sources[0x3a]	6296	1			T2	10		T13	2		T17	15
valid_sources[0x3b]	7313	1			T16	1		T13	1		T17	13
valid_sources[0x3c]	8700	1			T13	1		T17	14		T15	3
valid_sources[0x3d]	7952	1			T13	1		T17	14		T15	5
valid_sources[0x3e]	7873	1			T2	47		T17	15		T15	6
valid_sources[0x3f]	7472	1			T17	15		T15	4		T14	17
valid_sources[0x40]	7060	1			T16	1		T13	1		T17	17
valid_sources[0x41]	8257	1			T1	1		T2	89		T16	1
valid_sources[0x42]	7667	1			T1	2		T17	16		T15	4
valid_sources[0x43]	7944	1			T2	29		T17	14		T15	10
valid_sources[0x44]	7245	1			T13	1		T17	14		T15	4
valid_sources[0x45]	8656	1			T16	1		T17	16		T15	2
valid_sources[0x46]	7096	1			T13	1		T17	15		T15	2
valid_sources[0x47]	6812	1			T1	1		T2	1		T3	57
valid_sources[0x48]	8166	1			T2	7		T13	2		T17	14
valid_sources[0x49]	8394	1			T1	3		T17	14		T15	11
valid_sources[0x4a]	7020	1			T2	7		T3	1		T13	1
valid_sources[0x4b]	7823	1			T3	6		T17	14		T15	3
valid_sources[0x4c]	7690	1			T13	2		T17	16		T15	8
valid_sources[0x4d]	8620	1			T2	45		T13	2		T17	15
valid_sources[0x4e]	7115	1			T17	14		T15	1		T14	9
valid_sources[0x4f]	8465	1			T3	2		T16	1		T13	2
valid_sources[0x50]	7700	1			T17	14		T15	2		T14	5
valid_sources[0x51]	7936	1			T13	3		T17	14		T15	5
valid_sources[0x52]	8312	1			T1	2		T16	1		T13	1
valid_sources[0x53]	8199	1			T2	83		T3	9		T17	15
valid_sources[0x54]	7554	1			T2	71		T3	2		T17	14
valid_sources[0x55]	7479	1			T17	14		T15	3		T14	2
valid_sources[0x56]	7892	1			T3	4		T13	1		T17	13
valid_sources[0x57]	8094	1			T1	1		T17	12		T15	8
valid_sources[0x58]	7178	1			T17	15		T15	7		T14	3
valid_sources[0x59]	8424	1			T1	1		T17	16		T15	12
valid_sources[0x5a]	7937	1			T13	1		T17	14		T15	8
valid_sources[0x5b]	7189	1			T13	1		T17	17		T15	6
valid_sources[0x5c]	7209	1			T17	17		T15	13		T14	10
valid_sources[0x5d]	8087	1			T3	2		T16	1		T17	14
valid_sources[0x5e]	8174	1			T2	138		T13	2		T17	14
valid_sources[0x5f]	7768	1			T2	1		T13	1		T17	14
valid_sources[0x60]	7445	1			T17	14		T15	1		T14	3
valid_sources[0x61]	7474	1			T3	4		T17	15		T15	3
valid_sources[0x62]	7604	1			T16	1		T17	15		T15	11
valid_sources[0x63]	7981	1			T13	1		T17	14		T15	1
valid_sources[0x64]	7829	1			T3	3		T13	1		T17	15
valid_sources[0x65]	7578	1			T1	3		T13	3		T17	16
valid_sources[0x66]	7775	1			T3	1		T17	13		T15	8
valid_sources[0x67]	7280	1			T3	1		T17	16		T15	5
valid_sources[0x68]	7085	1			T17	14		T15	6		T14	1
valid_sources[0x69]	6942	1			T13	1		T17	15		T15	3
valid_sources[0x6a]	6939	1			T17	15		T15	4		T14	16
valid_sources[0x6b]	7444	1			T1	1		T2	21		T13	1
valid_sources[0x6c]	9056	1			T2	31		T3	11		T17	14
valid_sources[0x6d]	7374	1			T2	14		T17	14		T15	1
valid_sources[0x6e]	8014	1			T3	3		T13	1		T17	14
valid_sources[0x6f]	8016	1			T3	22		T17	13		T15	8
valid_sources[0x70]	7131	1			T1	1		T17	15		T15	6
valid_sources[0x71]	7271	1			T17	14		T15	3		T18	17
valid_sources[0x72]	8056	1			T3	6		T17	17		T15	4
valid_sources[0x73]	6984	1			T13	2		T17	12		T15	5
valid_sources[0x74]	8246	1			T17	16		T15	5		T14	4
valid_sources[0x75]	8052	1			T16	1		T13	2		T17	15
valid_sources[0x76]	7398	1			T1	2		T3	7		T16	1
valid_sources[0x77]	7192	1			T1	1		T16	1		T17	12
valid_sources[0x78]	7292	1			T2	21		T3	14		T13	1
valid_sources[0x79]	8036	1			T2	62		T13	2		T17	15
valid_sources[0x7a]	7455	1			T17	15		T15	8		T14	22
valid_sources[0x7b]	7492	1			T3	13		T17	14		T15	2
valid_sources[0x7c]	7210	1			T3	4		T13	1		T17	16
valid_sources[0x7d]	7740	1			T2	35		T16	1		T13	1
valid_sources[0x7e]	7911	1			T13	2		T17	13		T15	4
valid_sources[0x7f]	7171	1			T13	1		T17	12		T15	11
valid_sources[0x80]	8526	1			T3	8		T17	15		T15	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28631

1

T1

4

T2

41

T3

7

values[0x0]

all_enables

biggest_size

211078

1

T1

10

T2

281

T3

47

values[0x1]

all_enables

biggest_size

28417

1

T1

1

T2

35

T3

8