Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	357817687	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	357817687	0	0
T1	24136	546	0	0
T2	2627296	40104	0	0
T3	81424	2032	0	0
T13	11820032	282491	0	0
T14	1859816	27801	0	0
T15	6395984	941580	0	0
T16	1304408	25032	0	0
T17	18821096	1479805	0	0
T18	22569176	1868511	0	0
T19	3294704	48040	0	0
T20	0	1588	0	0
T21	0	102945	0	0
T22	0	428	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	24136	22624	0	0
T2	2627296	2625224	0	0
T3	81424	77392	0	0
T13	11820032	11815384	0	0
T14	1859816	1856064	0	0
T15	6395984	6395592	0	0
T16	1304408	1303120	0	0
T17	18821096	18820984	0	0
T18	22569176	22568728	0	0
T19	3294704	3293640	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	24136	22624	0	0
T2	2627296	2625224	0	0
T3	81424	77392	0	0
T13	11820032	11815384	0	0
T14	1859816	1856064	0	0
T15	6395984	6395592	0	0
T16	1304408	1303120	0	0
T17	18821096	18820984	0	0
T18	22569176	22568728	0	0
T19	3294704	3293640	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	24136	22624	0	0
T2	2627296	2625224	0	0
T3	81424	77392	0	0
T13	11820032	11815384	0	0
T14	1859816	1856064	0	0
T15	6395984	6395592	0	0
T16	1304408	1303120	0	0
T17	18821096	18820984	0	0
T18	22569176	22568728	0	0
T19	3294704	3293640	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	127056273	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	127056273	0	0
T1	431	213	0	0
T2	46916	18263	0	0
T3	1454	992	0	0
T13	211072	122950	0	0
T14	33211	13027	0	0
T15	114214	112690	0	0
T16	23293	10945	0	0
T17	336091	17187	0	0
T18	403021	21615	0	0
T19	58834	11964	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	94900405	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	94900405	0	0
T1	431	111	0	0
T2	46916	6322	0	0
T3	1454	510	0	0
T13	211072	51728	0	0
T14	33211	4087	0	0
T15	114214	411169	0	0
T16	23293	3394	0	0
T17	336091	131402	0	0
T18	403021	165935	0	0
T19	58834	12061	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1519146	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1519146	0	0
T1	431	3	0	0
T2	46916	420	0	0
T3	1454	14	0	0
T13	211072	3064	0	0
T14	33211	308	0	0
T15	114214	205	0	0
T16	23293	216	0	0
T17	336091	0	0	0
T18	403021	2539	0	0
T19	58834	459	0	0
T20	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3539270	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3539270	0	0
T1	431	3	0	0
T2	46916	180	0	0
T3	1454	14	0	0
T13	211072	1472	0	0
T14	33211	159	0	0
T15	114214	12539	0	0
T16	23293	121	0	0
T17	336091	0	0	0
T18	403021	190348	0	0
T19	58834	389	0	0
T20	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1577111	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1577111	0	0
T1	431	4	0	0
T2	46916	415	0	0
T3	1454	9	0	0
T13	211072	3611	0	0
T14	33211	223	0	0
T15	114214	299	0	0
T16	23293	274	0	0
T17	336091	1090	0	0
T18	403021	1239	0	0
T19	58834	517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3468807	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3468807	0	0
T1	431	4	0	0
T2	46916	181	0	0
T3	1454	9	0	0
T13	211072	2145	0	0
T14	33211	92	0	0
T15	114214	19122	0	0
T16	23293	124	0	0
T17	336091	83757	0	0
T18	403021	90602	0	0
T19	58834	465	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1621957	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1621957	0	0
T1	431	3	0	0
T2	46916	387	0	0
T3	1454	13	0	0
T13	211072	247	0	0
T14	33211	273	0	0
T15	114214	235	0	0
T16	23293	304	0	0
T17	336091	1197	0	0
T18	403021	1129	0	0
T19	58834	424	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3406196	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3406196	0	0
T1	431	3	0	0
T2	46916	154	0	0
T3	1454	13	0	0
T13	211072	388	0	0
T14	33211	139	0	0
T15	114214	16123	0	0
T16	23293	104	0	0
T17	336091	103402	0	0
T18	403021	83597	0	0
T19	58834	386	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1517861	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1517861	0	0
T1	431	3	0	0
T2	46916	250	0	0
T3	1454	9	0	0
T13	211072	3763	0	0
T14	33211	208	0	0
T15	114214	191	0	0
T16	23293	328	0	0
T17	336091	1119	0	0
T18	403021	1020	0	0
T19	58834	430	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	2515144	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	2515144	0	0
T1	431	3	0	0
T2	46916	135	0	0
T3	1454	9	0	0
T13	211072	2125	0	0
T14	33211	97	0	0
T15	114214	12355	0	0
T16	23293	172	0	0
T17	336091	84824	0	0
T18	403021	77982	0	0
T19	58834	397	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1514140	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1514140	0	0
T1	431	1	0	0
T2	46916	424	0	0
T3	1454	6	0	0
T13	211072	326	0	0
T14	33211	155	0	0
T15	114214	240	0	0
T16	23293	247	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	381	0	0
T20	0	29	0	0
T22	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3813572	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3813572	0	0
T1	431	1	0	0
T2	46916	224	0	0
T3	1454	6	0	0
T13	211072	810	0	0
T14	33211	65	0	0
T15	114214	16793	0	0
T16	23293	78	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	447	0	0
T20	0	29	0	0
T22	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1530196	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1530196	0	0
T1	431	3	0	0
T2	46916	332	0	0
T3	1454	16	0	0
T13	211072	1981	0	0
T14	33211	301	0	0
T15	114214	351	0	0
T16	23293	267	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	462	0	0
T20	0	38	0	0
T22	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3143566	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3143566	0	0
T1	431	3	0	0
T2	46916	167	0	0
T3	1454	16	0	0
T13	211072	3142	0	0
T14	33211	91	0	0
T15	114214	25634	0	0
T16	23293	137	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	386	0	0
T20	0	38	0	0
T22	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1536365	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1536365	0	0
T1	431	5	0	0
T2	46916	469	0	0
T3	1454	8	0	0
T13	211072	806	0	0
T14	33211	318	0	0
T15	114214	258	0	0
T16	23293	192	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	439	0	0
T20	0	42	0	0
T21	0	1195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3791105	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3791105	0	0
T1	431	5	0	0
T2	46916	129	0	0
T3	1454	8	0	0
T13	211072	1306	0	0
T14	33211	109	0	0
T15	114214	15822	0	0
T16	23293	80	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	382	0	0
T20	0	42	0	0
T21	0	101750	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1634342	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1634342	0	0
T1	431	5	0	0
T2	46916	377	0	0
T3	1454	10	0	0
T13	211072	1483	0	0
T14	33211	196	0	0
T15	114214	194	0	0
T16	23293	278	0	0
T17	336091	0	0	0
T18	403021	1084	0	0
T19	58834	492	0	0
T20	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	4069633	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	4069633	0	0
T1	431	5	0	0
T2	46916	248	0	0
T3	1454	10	0	0
T13	211072	1937	0	0
T14	33211	93	0	0
T15	114214	11689	0	0
T16	23293	105	0	0
T17	336091	0	0	0
T18	403021	82845	0	0
T19	58834	497	0	0
T20	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1534439	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1534439	0	0
T1	431	3	0	0
T2	46916	320	0	0
T3	1454	11	0	0
T13	211072	3519	0	0
T14	33211	372	0	0
T15	114214	307	0	0
T16	23293	258	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	390	0	0
T20	0	45	0	0
T22	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3269795	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3269795	0	0
T1	431	3	0	0
T2	46916	118	0	0
T3	1454	11	0	0
T13	211072	2323	0	0
T14	33211	133	0	0
T15	114214	18636	0	0
T16	23293	102	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	408	0	0
T20	0	45	0	0
T22	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1589086	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1589086	0	0
T1	431	5	0	0
T2	46916	301	0	0
T3	1454	6	0	0
T13	211072	2685	0	0
T14	33211	274	0	0
T15	114214	236	0	0
T16	23293	178	0	0
T17	336091	1029	0	0
T18	403021	0	0	0
T19	58834	483	0	0
T20	0	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3614357	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3614357	0	0
T1	431	5	0	0
T2	46916	135	0	0
T3	1454	6	0	0
T13	211072	2167	0	0
T14	33211	137	0	0
T15	114214	15793	0	0
T16	23293	88	0	0
T17	336091	81981	0	0
T18	403021	0	0	0
T19	58834	451	0	0
T20	0	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1557743	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1557743	0	0
T1	431	2	0	0
T2	46916	334	0	0
T3	1454	4	0	0
T13	211072	1695	0	0
T14	33211	369	0	0
T15	114214	168	0	0
T16	23293	323	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	458	0	0
T20	0	46	0	0
T22	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3094353	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3094353	0	0
T1	431	2	0	0
T2	46916	152	0	0
T3	1454	4	0	0
T13	211072	2338	0	0
T14	33211	146	0	0
T15	114214	13001	0	0
T16	23293	102	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	426	0	0
T20	0	46	0	0
T22	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1511787	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1511787	0	0
T1	431	3	0	0
T2	46916	359	0	0
T3	1454	10	0	0
T13	211072	1292	0	0
T14	33211	236	0	0
T15	114214	281	0	0
T16	23293	326	0	0
T17	336091	0	0	0
T18	403021	1309	0	0
T19	58834	498	0	0
T20	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3559122	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3559122	0	0
T1	431	3	0	0
T2	46916	158	0	0
T3	1454	10	0	0
T13	211072	1293	0	0
T14	33211	125	0	0
T15	114214	19501	0	0
T16	23293	163	0	0
T17	336091	0	0	0
T18	403021	96443	0	0
T19	58834	449	0	0
T20	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1555723	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1555723	0	0
T1	431	6	0	0
T2	46916	356	0	0
T3	1454	8	0	0
T13	211072	1824	0	0
T14	33211	278	0	0
T15	114214	261	0	0
T16	23293	298	0	0
T17	336091	0	0	0
T18	403021	2562	0	0
T19	58834	343	0	0
T20	0	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3546481	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3546481	0	0
T1	431	6	0	0
T2	46916	144	0	0
T3	1454	8	0	0
T13	211072	1980	0	0
T14	33211	82	0	0
T15	114214	12947	0	0
T16	23293	141	0	0
T17	336091	0	0	0
T18	403021	196502	0	0
T19	58834	448	0	0
T20	0	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1589456	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1589456	0	0
T1	431	4	0	0
T2	46916	355	0	0
T3	1454	4	0	0
T13	211072	2950	0	0
T14	33211	287	0	0
T15	114214	219	0	0
T16	23293	411	0	0
T17	336091	1273	0	0
T18	403021	0	0	0
T19	58834	409	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3750666	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3750666	0	0
T1	431	4	0	0
T2	46916	234	0	0
T3	1454	4	0	0
T13	211072	2086	0	0
T14	33211	102	0	0
T15	114214	13694	0	0
T16	23293	205	0	0
T17	336091	84016	0	0
T18	403021	0	0	0
T19	58834	413	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1547144	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1547144	0	0
T1	431	3	0	0
T2	46916	454	0	0
T3	1454	12	0	0
T13	211072	2195	0	0
T14	33211	311	0	0
T15	114214	260	0	0
T16	23293	341	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	502	0	0
T20	0	41	0	0
T22	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3648686	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3648686	0	0
T1	431	3	0	0
T2	46916	187	0	0
T3	1454	12	0	0
T13	211072	2349	0	0
T14	33211	99	0	0
T15	114214	18687	0	0
T16	23293	109	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	581	0	0
T20	0	41	0	0
T22	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1560910	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1560910	0	0
T1	431	4	0	0
T2	46916	356	0	0
T3	1454	14	0	0
T13	211072	980	0	0
T14	33211	407	0	0
T15	114214	207	0	0
T16	23293	307	0	0
T17	336091	1366	0	0
T18	403021	2509	0	0
T19	58834	357	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3961782	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3961782	0	0
T1	431	4	0	0
T2	46916	224	0	0
T3	1454	14	0	0
T13	211072	1071	0	0
T14	33211	141	0	0
T15	114214	14320	0	0
T16	23293	151	0	0
T17	336091	105488	0	0
T18	403021	200008	0	0
T19	58834	436	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1572279	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1572279	0	0
T1	431	3	0	0
T2	46916	448	0	0
T3	1454	9	0	0
T13	211072	2216	0	0
T14	33211	279	0	0
T15	114214	236	0	0
T16	23293	298	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	404	0	0
T20	0	32	0	0
T22	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3932175	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3932175	0	0
T1	431	3	0	0
T2	46916	159	0	0
T3	1454	9	0	0
T13	211072	1138	0	0
T14	33211	109	0	0
T15	114214	13489	0	0
T16	23293	125	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	422	0	0
T20	0	32	0	0
T22	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1531131	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1531131	0	0
T1	431	3	0	0
T2	46916	426	0	0
T3	1454	10	0	0
T13	211072	1624	0	0
T14	33211	216	0	0
T15	114214	261	0	0
T16	23293	264	0	0
T17	336091	0	0	0
T18	403021	2473	0	0
T19	58834	519	0	0
T20	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3496373	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3496373	0	0
T1	431	3	0	0
T2	46916	171	0	0
T3	1454	10	0	0
T13	211072	1244	0	0
T14	33211	98	0	0
T15	114214	15688	0	0
T16	23293	110	0	0
T17	336091	0	0	0
T18	403021	189267	0	0
T19	58834	492	0	0
T20	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1586333	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1586333	0	0
T1	431	2	0	0
T2	46916	322	0	0
T3	1454	8	0	0
T13	211072	947	0	0
T14	33211	203	0	0
T15	114214	199	0	0
T16	23293	198	0	0
T17	336091	2316	0	0
T18	403021	1032	0	0
T19	58834	370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3632796	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3632796	0	0
T1	431	2	0	0
T2	46916	180	0	0
T3	1454	8	0	0
T13	211072	2097	0	0
T14	33211	69	0	0
T15	114214	12016	0	0
T16	23293	133	0	0
T17	336091	188763	0	0
T18	403021	83349	0	0
T19	58834	330	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1586833	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1586833	0	0
T1	431	8	0	0
T2	46916	539	0	0
T3	1454	14	0	0
T13	211072	2240	0	0
T14	33211	282	0	0
T15	114214	239	0	0
T16	23293	200	0	0
T17	336091	903	0	0
T18	403021	0	0	0
T19	58834	615	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3872056	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3872056	0	0
T1	431	8	0	0
T2	46916	249	0	0
T3	1454	14	0	0
T13	211072	2898	0	0
T14	33211	129	0	0
T15	114214	17438	0	0
T16	23293	124	0	0
T17	336091	68188	0	0
T18	403021	0	0	0
T19	58834	550	0	0
T20	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1585944	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1585944	0	0
T1	431	5	0	0
T2	46916	433	0	0
T3	1454	8	0	0
T13	211072	1894	0	0
T14	33211	290	0	0
T15	114214	268	0	0
T16	23293	303	0	0
T17	336091	0	0	0
T18	403021	900	0	0
T19	58834	294	0	0
T20	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	2938731	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	2938731	0	0
T1	431	5	0	0
T2	46916	275	0	0
T3	1454	8	0	0
T13	211072	655	0	0
T14	33211	165	0	0
T15	114214	16395	0	0
T16	23293	186	0	0
T17	336091	0	0	0
T18	403021	67247	0	0
T19	58834	312	0	0
T20	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1538078	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1538078	0	0
T1	431	5	0	0
T2	46916	535	0	0
T3	1454	12	0	0
T13	211072	240	0	0
T14	33211	241	0	0
T15	114214	241	0	0
T16	23293	245	0	0
T17	336091	1158	0	0
T18	403021	0	0	0
T19	58834	427	0	0
T20	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3223898	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3223898	0	0
T1	431	5	0	0
T2	46916	199	0	0
T3	1454	12	0	0
T13	211072	1039	0	0
T14	33211	64	0	0
T15	114214	11260	0	0
T16	23293	114	0	0
T17	336091	89324	0	0
T18	403021	0	0	0
T19	58834	439	0	0
T20	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1533128	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1533128	0	0
T1	431	7	0	0
T2	46916	431	0	0
T3	1454	16	0	0
T13	211072	1523	0	0
T14	33211	206	0	0
T15	114214	230	0	0
T16	23293	277	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	472	0	0
T20	0	37	0	0
T22	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3326530	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3326530	0	0
T1	431	7	0	0
T2	46916	186	0	0
T3	1454	16	0	0
T13	211072	926	0	0
T14	33211	96	0	0
T15	114214	14174	0	0
T16	23293	140	0	0
T17	336091	0	0	0
T18	403021	0	0	0
T19	58834	532	0	0
T20	0	37	0	0
T22	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1528645	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1528645	0	0
T1	431	8	0	0
T2	46916	469	0	0
T3	1454	9	0	0
T13	211072	2922	0	0
T14	33211	316	0	0
T15	114214	236	0	0
T16	23293	180	0	0
T17	336091	1137	0	0
T18	403021	2561	0	0
T19	58834	534	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3813436	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3813436	0	0
T1	431	8	0	0
T2	46916	231	0	0
T3	1454	9	0	0
T13	211072	2985	0	0
T14	33211	158	0	0
T15	114214	14680	0	0
T16	23293	116	0	0
T17	336091	88309	0	0
T18	403021	200936	0	0
T19	58834	472	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1533500	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1533500	0	0
T1	431	9	0	0
T2	46916	348	0	0
T3	1454	7	0	0
T13	211072	2407	0	0
T14	33211	396	0	0
T15	114214	222	0	0
T16	23293	297	0	0
T17	336091	2331	0	0
T18	403021	0	0	0
T19	58834	435	0	0
T20	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3380151	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3380151	0	0
T1	431	9	0	0
T2	46916	145	0	0
T3	1454	7	0	0
T13	211072	2870	0	0
T14	33211	169	0	0
T15	114214	13728	0	0
T16	23293	156	0	0
T17	336091	171273	0	0
T18	403021	0	0	0
T19	58834	580	0	0
T20	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1546022	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1546022	0	0
T1	431	2	0	0
T2	46916	395	0	0
T3	1454	7	0	0
T13	211072	3787	0	0
T14	33211	353	0	0
T15	114214	272	0	0
T16	23293	259	0	0
T17	336091	1290	0	0
T18	403021	1256	0	0
T19	58834	403	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	3350036	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	3350036	0	0
T1	431	2	0	0
T2	46916	221	0	0
T3	1454	7	0	0
T13	211072	4188	0	0
T14	33211	149	0	0
T15	114214	14495	0	0
T16	23293	83	0	0
T17	336091	93409	0	0
T18	403021	100222	0	0
T19	58834	501	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	1534761	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	1534761	0	0
T1	431	2	0	0
T2	46916	331	0	0
T3	1454	11	0	0
T13	211072	3864	0	0
T14	33211	279	0	0
T15	114214	237	0	0
T16	23293	230	0	0
T17	336091	978	0	0
T18	403021	0	0	0
T19	58834	442	0	0
T20	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	327000231	2728232	0	0
DepthKnown_A	327000231	326874485	0	0
RvalidKnown_A	327000231	326874485	0	0
WreadyKnown_A	327000231	326874485	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	2728232	0	0
T1	431	2	0	0
T2	46916	147	0	0
T3	1454	11	0	0
T13	211072	2756	0	0
T14	33211	94	0	0
T15	114214	11149	0	0
T16	23293	125	0	0
T17	336091	71295	0	0
T18	403021	0	0	0
T19	58834	465	0	0
T20	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327000231	326874485	0	0
T1	431	404	0	0
T2	46916	46879	0	0
T3	1454	1382	0	0
T13	211072	210989	0	0
T14	33211	33144	0	0
T15	114214	114207	0	0
T16	23293	23270	0	0
T17	336091	336089	0	0
T18	403021	403013	0	0
T19	58834	58815	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0