Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1694039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

267003

1

T1

175

T4

66

T2

288

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	663922	1			T1	409		T4	184		T2	750
values[0x0]	633855	1			T1	410		T4	171		T2	729
values[0x1]	663265	1			T1	414		T4	167		T2	736

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1312832	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

648210

1

T1

407

T4

172

T2

729

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7324	1			T1	4		T3	1		T5	27
valid_sources[0x01]	7323	1			T1	5		T5	20		T19	20
valid_sources[0x02]	7203	1			T1	5		T2	41		T3	1
valid_sources[0x03]	7600	1			T1	7		T4	20		T3	1
valid_sources[0x04]	8273	1			T1	4		T4	37		T5	12
valid_sources[0x05]	7422	1			T1	5		T2	10		T5	22
valid_sources[0x06]	7451	1			T1	5		T2	20		T5	21
valid_sources[0x07]	6701	1			T1	3		T5	18		T19	19
valid_sources[0x08]	7321	1			T1	6		T2	9		T3	1
valid_sources[0x09]	7074	1			T1	5		T2	8		T3	1
valid_sources[0x0a]	7331	1			T1	4		T2	15		T5	13
valid_sources[0x0b]	8181	1			T1	5		T2	20		T3	1
valid_sources[0x0c]	6838	1			T1	5		T2	13		T3	1
valid_sources[0x0d]	6986	1			T1	4		T2	9		T3	1
valid_sources[0x0e]	7495	1			T1	4		T5	15		T19	17
valid_sources[0x0f]	6761	1			T1	5		T3	2		T5	19
valid_sources[0x10]	7613	1			T1	5		T3	1		T5	19
valid_sources[0x11]	7074	1			T1	5		T2	7		T3	1
valid_sources[0x12]	8305	1			T1	4		T2	5		T3	1
valid_sources[0x13]	8641	1			T1	5		T5	25		T19	18
valid_sources[0x14]	7571	1			T1	5		T4	20		T2	9
valid_sources[0x15]	8847	1			T1	5		T4	17		T2	16
valid_sources[0x16]	7446	1			T1	5		T5	23		T19	19
valid_sources[0x17]	7284	1			T1	5		T2	14		T3	1
valid_sources[0x18]	7069	1			T1	5		T4	12		T5	20
valid_sources[0x19]	6856	1			T1	4		T5	18		T6	4
valid_sources[0x1a]	6741	1			T1	5		T5	16		T6	5
valid_sources[0x1b]	8898	1			T1	4		T2	8		T5	19
valid_sources[0x1c]	8963	1			T1	5		T5	21		T19	16
valid_sources[0x1d]	7819	1			T1	4		T3	2		T5	13
valid_sources[0x1e]	7235	1			T1	5		T2	30		T5	15
valid_sources[0x1f]	7540	1			T1	5		T4	9		T5	14
valid_sources[0x20]	7357	1			T1	5		T4	13		T3	1
valid_sources[0x21]	7305	1			T1	4		T2	19		T3	1
valid_sources[0x22]	6778	1			T1	5		T2	8		T3	1
valid_sources[0x23]	7352	1			T1	3		T2	14		T5	15
valid_sources[0x24]	7070	1			T1	5		T4	17		T3	1
valid_sources[0x25]	7047	1			T1	4		T2	26		T3	1
valid_sources[0x26]	6807	1			T1	5		T2	18		T5	20
valid_sources[0x27]	9563	1			T1	6		T4	20		T2	10
valid_sources[0x28]	7854	1			T1	5		T3	1		T5	24
valid_sources[0x29]	7654	1			T1	5		T2	26		T5	25
valid_sources[0x2a]	7024	1			T1	4		T5	19		T19	16
valid_sources[0x2b]	6775	1			T1	5		T2	13		T3	1
valid_sources[0x2c]	7275	1			T1	6		T2	21		T5	10
valid_sources[0x2d]	7310	1			T1	6		T4	5		T2	5
valid_sources[0x2e]	7569	1			T1	5		T3	1		T5	11
valid_sources[0x2f]	7564	1			T1	6		T4	18		T5	19
valid_sources[0x30]	7022	1			T1	4		T5	22		T19	19
valid_sources[0x31]	7625	1			T1	6		T4	16		T2	12
valid_sources[0x32]	7061	1			T1	6		T3	2		T5	20
valid_sources[0x33]	7165	1			T1	5		T2	7		T3	2
valid_sources[0x34]	7254	1			T1	5		T2	5		T5	17
valid_sources[0x35]	6567	1			T1	5		T3	3		T5	16
valid_sources[0x36]	6966	1			T1	5		T3	1		T5	16
valid_sources[0x37]	7124	1			T1	6		T3	2		T5	18
valid_sources[0x38]	8568	1			T1	4		T2	45		T5	23
valid_sources[0x39]	7104	1			T1	5		T2	11		T5	20
valid_sources[0x3a]	9427	1			T1	5		T2	16		T5	12
valid_sources[0x3b]	8602	1			T1	5		T2	14		T5	19
valid_sources[0x3c]	7530	1			T1	4		T4	7		T5	17
valid_sources[0x3d]	6933	1			T1	5		T2	39		T5	22
valid_sources[0x3e]	7130	1			T1	5		T2	9		T3	2
valid_sources[0x3f]	7926	1			T1	4		T2	5		T3	1
valid_sources[0x40]	7453	1			T1	5		T3	1		T5	26
valid_sources[0x41]	8540	1			T1	7		T2	17		T5	15
valid_sources[0x42]	7140	1			T1	4		T4	6		T3	2
valid_sources[0x43]	7580	1			T1	5		T4	17		T3	1
valid_sources[0x44]	7922	1			T1	5		T3	1		T5	18
valid_sources[0x45]	8880	1			T1	5		T3	1		T5	17
valid_sources[0x46]	7849	1			T1	6		T2	26		T5	15
valid_sources[0x47]	7305	1			T1	4		T2	11		T3	1
valid_sources[0x48]	7513	1			T1	5		T2	19		T3	1
valid_sources[0x49]	7095	1			T1	5		T4	12		T2	10
valid_sources[0x4a]	7525	1			T1	5		T3	1		T5	7
valid_sources[0x4b]	7539	1			T1	5		T2	13		T5	17
valid_sources[0x4c]	9207	1			T1	5		T2	18		T3	2
valid_sources[0x4d]	7263	1			T1	3		T4	8		T2	16
valid_sources[0x4e]	7708	1			T1	6		T4	15		T2	5
valid_sources[0x4f]	7093	1			T1	5		T5	15		T19	17
valid_sources[0x50]	7044	1			T1	4		T3	1		T5	12
valid_sources[0x51]	7619	1			T1	5		T3	1		T5	23
valid_sources[0x52]	8211	1			T1	4		T5	20		T19	18
valid_sources[0x53]	6941	1			T1	4		T2	17		T5	14
valid_sources[0x54]	7021	1			T1	5		T5	26		T6	3
valid_sources[0x55]	7879	1			T1	5		T2	7		T3	1
valid_sources[0x56]	8191	1			T1	4		T5	18		T6	1
valid_sources[0x57]	8337	1			T1	5		T3	1		T5	17
valid_sources[0x58]	6669	1			T1	5		T4	9		T5	19
valid_sources[0x59]	7946	1			T1	5		T2	38		T5	24
valid_sources[0x5a]	7259	1			T1	5		T3	1		T5	21
valid_sources[0x5b]	8228	1			T1	5		T5	23		T19	15
valid_sources[0x5c]	7593	1			T1	5		T2	40		T3	1
valid_sources[0x5d]	7029	1			T1	5		T2	20		T3	1
valid_sources[0x5e]	7084	1			T1	3		T2	39		T5	15
valid_sources[0x5f]	7576	1			T1	5		T3	2		T5	22
valid_sources[0x60]	7608	1			T1	5		T2	7		T5	24
valid_sources[0x61]	7316	1			T1	4		T3	1		T5	21
valid_sources[0x62]	7058	1			T1	6		T4	10		T3	1
valid_sources[0x63]	7451	1			T1	6		T3	1		T5	16
valid_sources[0x64]	8193	1			T1	5		T4	15		T5	20
valid_sources[0x65]	7789	1			T1	5		T2	17		T5	16
valid_sources[0x66]	8438	1			T1	5		T2	14		T5	15
valid_sources[0x67]	8299	1			T1	5		T2	13		T3	1
valid_sources[0x68]	7826	1			T1	5		T5	21		T19	17
valid_sources[0x69]	8261	1			T1	2		T2	5		T5	16
valid_sources[0x6a]	7965	1			T1	5		T3	1		T5	17
valid_sources[0x6b]	7787	1			T1	5		T2	19		T3	1
valid_sources[0x6c]	7461	1			T1	4		T5	22		T6	5
valid_sources[0x6d]	7681	1			T1	4		T5	19		T19	16
valid_sources[0x6e]	8212	1			T1	3		T4	7		T5	24
valid_sources[0x6f]	7298	1			T1	5		T5	25		T19	15
valid_sources[0x70]	7682	1			T1	5		T4	7		T2	18
valid_sources[0x71]	7118	1			T1	5		T5	10		T19	20
valid_sources[0x72]	8288	1			T1	5		T3	1		T5	12
valid_sources[0x73]	7303	1			T1	5		T4	8		T2	14
valid_sources[0x74]	8191	1			T1	5		T2	18		T5	18
valid_sources[0x75]	8447	1			T1	6		T2	19		T5	23
valid_sources[0x76]	7861	1			T1	5		T5	15		T19	18
valid_sources[0x77]	8258	1			T1	5		T2	27		T5	20
valid_sources[0x78]	8150	1			T1	5		T2	10		T5	27
valid_sources[0x79]	8337	1			T1	5		T5	20		T6	14
valid_sources[0x7a]	8068	1			T1	5		T2	25		T5	16
valid_sources[0x7b]	8188	1			T1	5		T2	8		T3	1
valid_sources[0x7c]	7919	1			T1	4		T2	9		T5	18
valid_sources[0x7d]	7621	1			T1	5		T2	6		T5	13
valid_sources[0x7e]	7171	1			T1	5		T2	6		T5	19
valid_sources[0x7f]	7464	1			T1	4		T2	15		T3	1
valid_sources[0x80]	8581	1			T1	4		T2	17		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28264

1

T1

19

T4

6

T2

20

values[0x0]

all_enables

biggest_size

210516

1

T1

136

T4

56

T2

236

values[0x1]

all_enables

biggest_size

28223

1

T1

20

T4

4

T2

32