Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	363841462	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	363841462	0	0
T1	1212340	929130	0	0
T2	4668496	68626	0	0
T3	3267880	67913	0	0
T4	74144	2088	0	0
T5	5457984	107067	0	0
T6	2975728	42923	0	0
T12	10653832	212123	0	0
T19	21006272	1752653	0	0
T20	651392	9366	0	0
T21	8532048	289001	0	0
T22	2405294	24228	0	0
T23	0	45652	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6789104	6788936	0	0
T2	4668496	4665024	0	0
T3	3267880	3264520	0	0
T4	74144	72464	0	0
T5	5457984	5456472	0	0
T6	2975728	2975224	0	0
T12	10653832	10576216	0	0
T19	21006272	21005880	0	0
T20	651392	649544	0	0
T21	8532048	8529528	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6789104	6788936	0	0
T2	4668496	4665024	0	0
T3	3267880	3264520	0	0
T4	74144	72464	0	0
T5	5457984	5456472	0	0
T6	2975728	2975224	0	0
T12	10653832	10576216	0	0
T19	21006272	21005880	0	0
T20	651392	649544	0	0
T21	8532048	8529528	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6789104	6788936	0	0
T2	4668496	4665024	0	0
T3	3267880	3264520	0	0
T4	74144	72464	0	0
T5	5457984	5456472	0	0
T6	2975728	2975224	0	0
T12	10653832	10576216	0	0
T19	21006272	21005880	0	0
T20	651392	649544	0	0
T21	8532048	8529528	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T12	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	132713398	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	132713398	0	0
T1	121234	5807	0	0
T2	83366	16724	0	0
T3	58355	31523	0	0
T4	1324	522	0	0
T5	97464	38900	0	0
T6	53138	19637	0	0
T12	190247	87592	0	0
T19	375112	20100	0	0
T20	11632	4301	0	0
T21	152358	150812	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	95625535	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	95625535	0	0
T1	121234	458758	0	0
T2	83366	17606	0	0
T3	58355	8396	0	0
T4	1324	522	0	0
T5	97464	18575	0	0
T6	53138	6506	0	0
T12	190247	31705	0	0
T19	375112	155677	0	0
T20	11632	1451	0	0
T21	152358	68719	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1547040	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1547040	0	0
T2	83366	517	0	0
T3	58355	702	0	0
T4	1324	22	0	0
T5	97464	158	0	0
T6	53138	419	0	0
T12	190247	5462	0	0
T19	375112	2383	0	0
T20	11632	114	0	0
T21	152358	29	0	0
T22	52289	581	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3673345	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3673345	0	0
T2	83366	501	0	0
T3	58355	301	0	0
T4	1324	22	0	0
T5	97464	105	0	0
T6	53138	203	0	0
T12	190247	2386	0	0
T19	375112	187559	0	0
T20	11632	43	0	0
T21	152358	1859	0	0
T22	52289	386	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1545977	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1545977	0	0
T1	121234	1463	0	0
T2	83366	555	0	0
T3	58355	764	0	0
T4	1324	18	0	0
T5	97464	255	0	0
T6	53138	453	0	0
T12	190247	2811	0	0
T19	375112	0	0	0
T20	11632	137	0	0
T21	152358	60	0	0
T22	0	541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3871952	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3871952	0	0
T1	121234	106941	0	0
T2	83366	558	0	0
T3	58355	398	0	0
T4	1324	18	0	0
T5	97464	146	0	0
T6	53138	212	0	0
T12	190247	1417	0	0
T19	375112	0	0	0
T20	11632	49	0	0
T21	152358	4521	0	0
T22	0	468	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1517233	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1517233	0	0
T2	83366	672	0	0
T3	58355	499	0	0
T4	1324	13	0	0
T5	97464	2122	0	0
T6	53138	560	0	0
T12	190247	927	0	0
T19	375112	1338	0	0
T20	11632	122	0	0
T21	152358	8	0	0
T22	52289	651	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	4020739	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	4020739	0	0
T2	83366	723	0	0
T3	58355	286	0	0
T4	1324	13	0	0
T5	97464	1129	0	0
T6	53138	221	0	0
T12	190247	484	0	0
T19	375112	97007	0	0
T20	11632	40	0	0
T21	152358	704	0	0
T22	52289	387	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1507957	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1507957	0	0
T2	83366	678	0	0
T3	58355	711	0	0
T4	1324	18	0	0
T5	97464	4308	0	0
T6	53138	337	0	0
T12	190247	957	0	0
T19	375112	2352	0	0
T20	11632	100	0	0
T21	152358	19	0	0
T22	52289	444	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3474135	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3474135	0	0
T2	83366	696	0	0
T3	58355	328	0	0
T4	1324	18	0	0
T5	97464	2163	0	0
T6	53138	158	0	0
T12	190247	514	0	0
T19	375112	185551	0	0
T20	11632	66	0	0
T21	152358	2305	0	0
T22	52289	320	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1476883	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1476883	0	0
T2	83366	572	0	0
T3	58355	642	0	0
T4	1324	20	0	0
T5	97464	226	0	0
T6	53138	405	0	0
T12	190247	6630	0	0
T19	375112	0	0	0
T20	11632	110	0	0
T21	152358	7	0	0
T22	52289	453	0	0
T23	0	1460	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3233693	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3233693	0	0
T2	83366	674	0	0
T3	58355	320	0	0
T4	1324	20	0	0
T5	97464	119	0	0
T6	53138	161	0	0
T12	190247	3415	0	0
T19	375112	0	0	0
T20	11632	19	0	0
T21	152358	1572	0	0
T22	52289	397	0	0
T23	0	1562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1505902	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1505902	0	0
T2	83366	684	0	0
T3	58355	715	0	0
T4	1324	13	0	0
T5	97464	4237	0	0
T6	53138	496	0	0
T12	190247	6030	0	0
T19	375112	0	0	0
T20	11632	85	0	0
T21	152358	31	0	0
T22	52289	551	0	0
T23	0	1599	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3297342	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3297342	0	0
T2	83366	803	0	0
T3	58355	295	0	0
T4	1324	13	0	0
T5	97464	1991	0	0
T6	53138	254	0	0
T12	190247	2723	0	0
T19	375112	0	0	0
T20	11632	33	0	0
T21	152358	1637	0	0
T22	52289	380	0	0
T23	0	1569	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1526110	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1526110	0	0
T2	83366	548	0	0
T3	58355	767	0	0
T4	1324	19	0	0
T5	97464	238	0	0
T6	53138	501	0	0
T12	190247	3037	0	0
T19	375112	3786	0	0
T20	11632	95	0	0
T21	152358	25	0	0
T22	52289	566	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3190164	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3190164	0	0
T2	83366	622	0	0
T3	58355	323	0	0
T4	1324	19	0	0
T5	97464	93	0	0
T6	53138	197	0	0
T12	190247	1312	0	0
T19	375112	295270	0	0
T20	11632	26	0	0
T21	152358	2668	0	0
T22	52289	372	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1509302	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1509302	0	0
T1	121234	1160	0	0
T2	83366	572	0	0
T3	58355	685	0	0
T4	1324	24	0	0
T5	97464	3932	0	0
T6	53138	581	0	0
T12	190247	2110	0	0
T19	375112	1064	0	0
T20	11632	85	0	0
T21	152358	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3590039	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3590039	0	0
T1	121234	90937	0	0
T2	83366	641	0	0
T3	58355	309	0	0
T4	1324	24	0	0
T5	97464	2800	0	0
T6	53138	239	0	0
T12	190247	918	0	0
T19	375112	88296	0	0
T20	11632	33	0	0
T21	152358	3544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1485553	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1485553	0	0
T2	83366	490	0	0
T3	58355	771	0	0
T4	1324	22	0	0
T5	97464	1471	0	0
T6	53138	415	0	0
T12	190247	2104	0	0
T19	375112	0	0	0
T20	11632	97	0	0
T21	152358	15	0	0
T22	52289	590	0	0
T23	0	1771	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	2590199	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	2590199	0	0
T2	83366	528	0	0
T3	58355	302	0	0
T4	1324	22	0	0
T5	97464	1351	0	0
T6	53138	215	0	0
T12	190247	1570	0	0
T19	375112	0	0	0
T20	11632	38	0	0
T21	152358	3353	0	0
T22	52289	471	0	0
T23	0	1726	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1526397	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1526397	0	0
T2	83366	657	0	0
T3	58355	768	0	0
T4	1324	16	0	0
T5	97464	185	0	0
T6	53138	549	0	0
T12	190247	963	0	0
T19	375112	0	0	0
T20	11632	89	0	0
T21	152358	23	0	0
T22	52289	729	0	0
T23	0	1791	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3840399	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3840399	0	0
T2	83366	651	0	0
T3	58355	283	0	0
T4	1324	16	0	0
T5	97464	112	0	0
T6	53138	307	0	0
T12	190247	502	0	0
T19	375112	0	0	0
T20	11632	53	0	0
T21	152358	2354	0	0
T22	52289	467	0	0
T23	0	1970	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1500342	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1500342	0	0
T2	83366	499	0	0
T3	58355	766	0	0
T4	1324	18	0	0
T5	97464	199	0	0
T6	53138	375	0	0
T12	190247	3077	0	0
T19	375112	0	0	0
T20	11632	64	0	0
T21	152358	18	0	0
T22	52289	575	0	0
T23	0	1813	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	2911460	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	2911460	0	0
T2	83366	576	0	0
T3	58355	328	0	0
T4	1324	18	0	0
T5	97464	69	0	0
T6	53138	163	0	0
T12	190247	1629	0	0
T19	375112	0	0	0
T20	11632	62	0	0
T21	152358	3702	0	0
T22	52289	498	0	0
T23	0	1877	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1565307	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1565307	0	0
T2	83366	597	0	0
T3	58355	889	0	0
T4	1324	16	0	0
T5	97464	211	0	0
T6	53138	340	0	0
T12	190247	1029	0	0
T19	375112	1396	0	0
T20	11632	75	0	0
T21	152358	56	0	0
T22	52289	605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3467878	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3467878	0	0
T2	83366	621	0	0
T3	58355	361	0	0
T4	1324	16	0	0
T5	97464	72	0	0
T6	53138	128	0	0
T12	190247	473	0	0
T19	375112	105741	0	0
T20	11632	34	0	0
T21	152358	2496	0	0
T22	52289	521	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1478689	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1478689	0	0
T2	83366	869	0	0
T3	58355	916	0	0
T4	1324	12	0	0
T5	97464	156	0	0
T6	53138	350	0	0
T12	190247	897	0	0
T19	375112	0	0	0
T20	11632	99	0	0
T21	152358	37	0	0
T22	52289	532	0	0
T23	0	1965	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3555522	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3555522	0	0
T2	83366	935	0	0
T3	58355	367	0	0
T4	1324	12	0	0
T5	97464	88	0	0
T6	53138	167	0	0
T12	190247	494	0	0
T19	375112	0	0	0
T20	11632	44	0	0
T21	152358	4535	0	0
T22	52289	443	0	0
T23	0	1822	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1514158	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1514158	0	0
T2	83366	628	0	0
T3	58355	725	0	0
T4	1324	16	0	0
T5	97464	260	0	0
T6	53138	456	0	0
T12	190247	2783	0	0
T19	375112	1179	0	0
T20	11632	101	0	0
T21	152358	45	0	0
T22	52289	487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3650208	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3650208	0	0
T2	83366	644	0	0
T3	58355	334	0	0
T4	1324	16	0	0
T5	97464	87	0	0
T6	53138	162	0	0
T12	190247	1289	0	0
T19	375112	98319	0	0
T20	11632	27	0	0
T21	152358	5267	0	0
T22	52289	363	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1484733	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1484733	0	0
T1	121234	2190	0	0
T2	83366	523	0	0
T3	58355	683	0	0
T4	1324	19	0	0
T5	97464	1293	0	0
T6	53138	422	0	0
T12	190247	2719	0	0
T19	375112	1191	0	0
T20	11632	88	0	0
T21	152358	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3776222	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3776222	0	0
T1	121234	171872	0	0
T2	83366	657	0	0
T3	58355	303	0	0
T4	1324	19	0	0
T5	97464	981	0	0
T6	53138	158	0	0
T12	190247	1391	0	0
T19	375112	91931	0	0
T20	11632	66	0	0
T21	152358	942	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1543066	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1543066	0	0
T2	83366	609	0	0
T3	58355	573	0	0
T4	1324	28	0	0
T5	97464	131	0	0
T6	53138	498	0	0
T12	190247	2892	0	0
T19	375112	0	0	0
T20	11632	58	0	0
T21	152358	35	0	0
T22	52289	472	0	0
T23	0	1870	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3236097	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3236097	0	0
T2	83366	660	0	0
T3	58355	240	0	0
T4	1324	28	0	0
T5	97464	49	0	0
T6	53138	236	0	0
T12	190247	1378	0	0
T19	375112	0	0	0
T20	11632	21	0	0
T21	152358	1906	0	0
T22	52289	350	0	0
T23	0	1739	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1526967	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1526967	0	0
T2	83366	607	0	0
T3	58355	716	0	0
T4	1324	17	0	0
T5	97464	176	0	0
T6	53138	299	0	0
T12	190247	860	0	0
T19	375112	0	0	0
T20	11632	70	0	0
T21	152358	16	0	0
T22	52289	483	0	0
T23	0	1526	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3810691	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3810691	0	0
T2	83366	689	0	0
T3	58355	330	0	0
T4	1324	17	0	0
T5	97464	70	0	0
T6	53138	166	0	0
T12	190247	505	0	0
T19	375112	0	0	0
T20	11632	56	0	0
T21	152358	943	0	0
T22	52289	489	0	0
T23	0	1678	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1501189	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1501189	0	0
T1	121234	994	0	0
T2	83366	640	0	0
T3	58355	588	0	0
T4	1324	15	0	0
T5	97464	269	0	0
T6	53138	397	0	0
T12	190247	2548	0	0
T19	375112	0	0	0
T20	11632	98	0	0
T21	152358	25	0	0
T22	0	465	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3378780	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3378780	0	0
T1	121234	89008	0	0
T2	83366	536	0	0
T3	58355	267	0	0
T4	1324	15	0	0
T5	97464	138	0	0
T6	53138	174	0	0
T12	190247	1263	0	0
T19	375112	0	0	0
T20	11632	58	0	0
T21	152358	3718	0	0
T22	0	385	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1514974	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1514974	0	0
T2	83366	604	0	0
T3	58355	745	0	0
T4	1324	26	0	0
T5	97464	2362	0	0
T6	53138	291	0	0
T12	190247	1035	0	0
T19	375112	956	0	0
T20	11632	64	0	0
T21	152358	45	0	0
T22	52289	516	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3419938	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3419938	0	0
T2	83366	676	0	0
T3	58355	311	0	0
T4	1324	26	0	0
T5	97464	1148	0	0
T6	53138	119	0	0
T12	190247	500	0	0
T19	375112	78929	0	0
T20	11632	36	0	0
T21	152358	4165	0	0
T22	52289	504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1523273	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1523273	0	0
T2	83366	553	0	0
T3	58355	680	0	0
T4	1324	26	0	0
T5	97464	183	0	0
T6	53138	495	0	0
T12	190247	823	0	0
T19	375112	0	0	0
T20	11632	86	0	0
T21	152358	36	0	0
T22	52289	577	0	0
T23	0	1782	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3476325	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3476325	0	0
T2	83366	626	0	0
T3	58355	293	0	0
T4	1324	26	0	0
T5	97464	89	0	0
T6	53138	224	0	0
T12	190247	376	0	0
T19	375112	0	0	0
T20	11632	38	0	0
T21	152358	2752	0	0
T22	52289	502	0	0
T23	0	1793	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1565502	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1565502	0	0
T2	83366	661	0	0
T3	58355	727	0	0
T4	1324	14	0	0
T5	97464	223	0	0
T6	53138	404	0	0
T12	190247	2489	0	0
T19	375112	0	0	0
T20	11632	76	0	0
T21	152358	17	0	0
T22	52289	435	0	0
T23	0	2022	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3873488	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3873488	0	0
T2	83366	745	0	0
T3	58355	240	0	0
T4	1324	14	0	0
T5	97464	78	0	0
T6	53138	144	0	0
T12	190247	1266	0	0
T19	375112	0	0	0
T20	11632	21	0	0
T21	152358	1002	0	0
T22	52289	370	0	0
T23	0	1877	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1475322	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1475322	0	0
T2	83366	628	0	0
T3	58355	738	0	0
T4	1324	19	0	0
T5	97464	1892	0	0
T6	53138	518	0	0
T12	190247	2042	0	0
T19	375112	1255	0	0
T20	11632	114	0	0
T21	152358	20	0	0
T22	52289	397	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3292201	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3292201	0	0
T2	83366	657	0	0
T3	58355	322	0	0
T4	1324	19	0	0
T5	97464	839	0	0
T6	53138	236	0	0
T12	190247	1122	0	0
T19	375112	87105	0	0
T20	11632	57	0	0
T21	152358	1505	0	0
T22	52289	420	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1496239	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1496239	0	0
T2	83366	483	0	0
T3	58355	830	0	0
T4	1324	19	0	0
T5	97464	164	0	0
T6	53138	507	0	0
T12	190247	2130	0	0
T19	375112	990	0	0
T20	11632	94	0	0
T21	152358	21	0	0
T22	52289	640	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3318877	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3318877	0	0
T2	83366	521	0	0
T3	58355	347	0	0
T4	1324	19	0	0
T5	97464	82	0	0
T6	53138	208	0	0
T12	190247	1562	0	0
T19	375112	77919	0	0
T20	11632	39	0	0
T21	152358	1811	0	0
T22	52289	519	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1476679	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1476679	0	0
T2	83366	580	0	0
T3	58355	738	0	0
T4	1324	15	0	0
T5	97464	256	0	0
T6	53138	460	0	0
T12	190247	774	0	0
T19	375112	2210	0	0
T20	11632	109	0	0
T21	152358	13	0	0
T22	52289	532	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3550254	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3550254	0	0
T2	83366	573	0	0
T3	58355	298	0	0
T4	1324	15	0	0
T5	97464	93	0	0
T6	53138	166	0	0
T12	190247	441	0	0
T19	375112	163149	0	0
T20	11632	44	0	0
T21	152358	1828	0	0
T22	52289	531	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1483602	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1483602	0	0
T2	83366	849	0	0
T3	58355	704	0	0
T4	1324	24	0	0
T5	97464	168	0	0
T6	53138	444	0	0
T12	190247	2748	0	0
T19	375112	0	0	0
T20	11632	117	0	0
T21	152358	25	0	0
T22	52289	555	0	0
T23	0	1733	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3637323	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3637323	0	0
T2	83366	759	0	0
T3	58355	293	0	0
T4	1324	24	0	0
T5	97464	75	0	0
T6	53138	192	0	0
T12	190247	1380	0	0
T19	375112	0	0	0
T20	11632	37	0	0
T21	152358	1449	0	0
T22	52289	491	0	0
T23	0	1569	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1490565	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1490565	0	0
T2	83366	739	0	0
T3	58355	866	0	0
T4	1324	28	0	0
T5	97464	2068	0	0
T6	53138	375	0	0
T12	190247	911	0	0
T19	375112	0	0	0
T20	11632	36	0	0
T21	152358	48	0	0
T22	52289	558	0	0
T23	0	1652	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3955029	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3955029	0	0
T2	83366	670	0	0
T3	58355	326	0	0
T4	1324	28	0	0
T5	97464	918	0	0
T6	53138	157	0	0
T12	190247	387	0	0
T19	375112	0	0	0
T20	11632	14	0	0
T21	152358	4152	0	0
T22	52289	386	0	0
T23	0	1833	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	1507011	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	1507011	0	0
T2	83366	693	0	0
T3	58355	691	0	0
T4	1324	25	0	0
T5	97464	4243	0	0
T6	53138	350	0	0
T12	190247	868	0	0
T19	375112	0	0	0
T20	11632	130	0	0
T21	152358	26	0	0
T22	52289	480	0	0
T23	0	1793	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	324087087	3614257	0	0
DepthKnown_A	324087087	323956946	0	0
RvalidKnown_A	324087087	323956946	0	0
WreadyKnown_A	324087087	323956946	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	3614257	0	0
T2	83366	647	0	0
T3	58355	290	0	0
T4	1324	25	0	0
T5	97464	3321	0	0
T6	53138	116	0	0
T12	190247	473	0	0
T19	375112	0	0	0
T20	11632	47	0	0
T21	152358	2029	0	0
T22	52289	393	0	0
T23	0	1860	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324087087	323956946	0	0
T1	121234	121231	0	0
T2	83366	83304	0	0
T3	58355	58295	0	0
T4	1324	1294	0	0
T5	97464	97437	0	0
T6	53138	53129	0	0
T12	190247	188861	0	0
T19	375112	375105	0	0
T20	11632	11599	0	0
T21	152358	152313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0