Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1882753	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

297261

1

T1

26

T2

27

T3

303

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	736240	1			T1	51		T2	65		T3	803
values[0x0]	706109	1			T1	52		T2	66		T3	741
values[0x1]	737665	1			T1	53		T2	69		T3	824

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1458590	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

721424

1

T1

55

T2

58

T3

774

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8219	1			T1	1		T4	19		T18	6
valid_sources[0x01]	8384	1			T3	4		T4	9		T18	6
valid_sources[0x02]	9185	1			T2	2		T3	21		T4	5
valid_sources[0x03]	7813	1			T3	7		T4	14		T18	12
valid_sources[0x04]	7898	1			T3	4		T4	11		T18	7
valid_sources[0x05]	8315	1			T3	23		T4	9		T18	9
valid_sources[0x06]	8669	1			T2	2		T3	2		T4	4
valid_sources[0x07]	8325	1			T1	1		T4	19		T18	6
valid_sources[0x08]	8792	1			T4	3		T18	10		T16	12
valid_sources[0x09]	8694	1			T3	1		T4	10		T18	8
valid_sources[0x0a]	8873	1			T1	1		T4	5		T18	13
valid_sources[0x0b]	8059	1			T4	25		T18	13		T16	3
valid_sources[0x0c]	9181	1			T1	1		T3	12		T4	11
valid_sources[0x0d]	8020	1			T3	29		T4	3		T18	11
valid_sources[0x0e]	8461	1			T1	1		T4	2		T18	13
valid_sources[0x0f]	9162	1			T3	29		T4	9		T18	9
valid_sources[0x10]	7780	1			T1	2		T4	7		T18	10
valid_sources[0x11]	8216	1			T3	5		T4	5		T18	11
valid_sources[0x12]	8302	1			T4	21		T18	10		T16	4
valid_sources[0x13]	8833	1			T1	1		T2	2		T4	22
valid_sources[0x14]	8792	1			T1	2		T3	53		T4	8
valid_sources[0x15]	8284	1			T1	1		T3	26		T4	17
valid_sources[0x16]	7628	1			T1	1		T4	8		T18	10
valid_sources[0x17]	7756	1			T1	1		T4	9		T18	9
valid_sources[0x18]	7819	1			T3	1		T4	12		T18	7
valid_sources[0x19]	8736	1			T2	1		T4	19		T18	9
valid_sources[0x1a]	7803	1			T1	1		T2	1		T4	12
valid_sources[0x1b]	8303	1			T1	2		T3	13		T4	8
valid_sources[0x1c]	8558	1			T1	2		T2	8		T4	6
valid_sources[0x1d]	8641	1			T1	1		T4	12		T18	13
valid_sources[0x1e]	8788	1			T4	17		T18	12		T16	8
valid_sources[0x1f]	7882	1			T3	12		T4	3		T18	6
valid_sources[0x20]	9174	1			T3	35		T4	7		T18	9
valid_sources[0x21]	8260	1			T1	1		T4	9		T18	14
valid_sources[0x22]	7803	1			T2	2		T4	10		T18	9
valid_sources[0x23]	8791	1			T1	2		T3	18		T4	17
valid_sources[0x24]	9082	1			T1	1		T2	2		T3	49
valid_sources[0x25]	8093	1			T2	1		T4	14		T18	17
valid_sources[0x26]	8271	1			T2	6		T4	10		T18	7
valid_sources[0x27]	8727	1			T4	3		T18	6		T16	5
valid_sources[0x28]	7889	1			T1	2		T3	6		T4	11
valid_sources[0x29]	8142	1			T1	3		T2	2		T4	7
valid_sources[0x2a]	9480	1			T1	1		T3	15		T4	19
valid_sources[0x2b]	8617	1			T4	2		T18	10		T16	6
valid_sources[0x2c]	8260	1			T1	1		T3	2		T4	3
valid_sources[0x2d]	8385	1			T2	6		T3	9		T4	4
valid_sources[0x2e]	9487	1			T3	11		T4	17		T18	14
valid_sources[0x2f]	8837	1			T4	5		T18	7		T16	3
valid_sources[0x30]	9817	1			T1	4		T4	9		T18	9
valid_sources[0x31]	9597	1			T4	13		T18	5		T16	5
valid_sources[0x32]	8948	1			T2	1		T3	3		T4	4
valid_sources[0x33]	8682	1			T4	14		T18	9		T16	1
valid_sources[0x34]	9516	1			T4	6		T18	10		T16	5
valid_sources[0x35]	9002	1			T4	3		T18	8		T16	9
valid_sources[0x36]	8866	1			T2	5		T4	32		T18	13
valid_sources[0x37]	9189	1			T1	1		T4	7		T18	9
valid_sources[0x38]	9083	1			T1	1		T4	9		T18	16
valid_sources[0x39]	8146	1			T2	3		T4	8		T18	13
valid_sources[0x3a]	8059	1			T3	2		T4	10		T18	15
valid_sources[0x3b]	7895	1			T1	2		T4	11		T18	11
valid_sources[0x3c]	8609	1			T1	1		T4	5		T18	8
valid_sources[0x3d]	9802	1			T1	1		T3	4		T4	13
valid_sources[0x3e]	8049	1			T1	1		T4	3		T18	12
valid_sources[0x3f]	7591	1			T4	26		T18	8		T16	3
valid_sources[0x40]	8357	1			T2	2		T3	10		T4	4
valid_sources[0x41]	8417	1			T3	21		T4	10		T18	6
valid_sources[0x42]	7977	1			T2	4		T4	7		T18	6
valid_sources[0x43]	8901	1			T3	3		T4	14		T18	12
valid_sources[0x44]	7424	1			T1	2		T3	2		T4	8
valid_sources[0x45]	8183	1			T1	1		T2	7		T4	5
valid_sources[0x46]	7936	1			T1	1		T3	11		T4	17
valid_sources[0x47]	7953	1			T4	5		T18	13		T16	5
valid_sources[0x48]	8405	1			T1	2		T2	1		T3	4
valid_sources[0x49]	9386	1			T2	2		T4	6		T18	15
valid_sources[0x4a]	8604	1			T1	2		T3	1		T4	10
valid_sources[0x4b]	7855	1			T4	10		T18	7		T16	11
valid_sources[0x4c]	7618	1			T1	1		T2	2		T4	4
valid_sources[0x4d]	8464	1			T1	2		T2	1		T3	1
valid_sources[0x4e]	8956	1			T1	1		T4	4		T18	12
valid_sources[0x4f]	8769	1			T4	4		T18	12		T16	13
valid_sources[0x50]	8071	1			T4	15		T18	10		T16	9
valid_sources[0x51]	8055	1			T4	10		T18	7		T16	3
valid_sources[0x52]	8118	1			T4	16		T18	16		T16	9
valid_sources[0x53]	8337	1			T4	4		T18	15		T16	14
valid_sources[0x54]	8002	1			T4	13		T18	8		T16	4
valid_sources[0x55]	8773	1			T1	1		T3	1		T4	25
valid_sources[0x56]	8821	1			T4	4		T18	6		T16	6
valid_sources[0x57]	8606	1			T1	1		T3	56		T4	14
valid_sources[0x58]	9016	1			T1	1		T4	10		T18	9
valid_sources[0x59]	9436	1			T4	12		T18	9		T16	11
valid_sources[0x5a]	8345	1			T1	1		T3	2		T4	5
valid_sources[0x5b]	8280	1			T1	1		T4	3		T18	5
valid_sources[0x5c]	9341	1			T4	5		T18	9		T16	8
valid_sources[0x5d]	8335	1			T4	19		T18	12		T16	12
valid_sources[0x5e]	8782	1			T1	1		T3	17		T4	10
valid_sources[0x5f]	8668	1			T2	6		T4	3		T18	6
valid_sources[0x60]	8829	1			T4	8		T18	15		T16	1
valid_sources[0x61]	8558	1			T3	4		T4	18		T18	11
valid_sources[0x62]	9101	1			T1	2		T3	4		T4	7
valid_sources[0x63]	9667	1			T1	2		T4	18		T18	7
valid_sources[0x64]	7997	1			T3	4		T4	8		T18	10
valid_sources[0x65]	8742	1			T1	1		T3	3		T4	9
valid_sources[0x66]	9030	1			T1	1		T3	1		T4	12
valid_sources[0x67]	8895	1			T3	2		T4	10		T18	12
valid_sources[0x68]	8209	1			T2	9		T3	25		T4	11
valid_sources[0x69]	8111	1			T4	15		T18	5		T16	6
valid_sources[0x6a]	9631	1			T4	3		T18	5		T16	4
valid_sources[0x6b]	8972	1			T1	1		T4	3		T18	6
valid_sources[0x6c]	8181	1			T1	1		T2	2		T3	16
valid_sources[0x6d]	8625	1			T1	1		T2	3		T4	3
valid_sources[0x6e]	9622	1			T3	2		T4	6		T18	10
valid_sources[0x6f]	8843	1			T4	5		T18	11		T16	9
valid_sources[0x70]	8201	1			T2	3		T4	10		T18	14
valid_sources[0x71]	9551	1			T3	10		T4	14		T18	10
valid_sources[0x72]	9670	1			T3	6		T4	2		T18	11
valid_sources[0x73]	8103	1			T2	4		T3	2		T4	13
valid_sources[0x74]	8967	1			T1	1		T3	58		T4	7
valid_sources[0x75]	7969	1			T3	124		T4	7		T18	6
valid_sources[0x76]	8344	1			T1	1		T4	8		T18	10
valid_sources[0x77]	8103	1			T4	5		T18	14		T16	2
valid_sources[0x78]	8344	1			T1	3		T3	7		T4	5
valid_sources[0x79]	8323	1			T1	1		T3	167		T4	6
valid_sources[0x7a]	9864	1			T1	1		T4	12		T18	11
valid_sources[0x7b]	7936	1			T3	46		T4	11		T18	10
valid_sources[0x7c]	7964	1			T1	2		T4	5		T18	10
valid_sources[0x7d]	8438	1			T4	3		T18	12		T16	5
valid_sources[0x7e]	8202	1			T1	2		T2	6		T3	4
valid_sources[0x7f]	8383	1			T4	13		T18	13		T16	10
valid_sources[0x80]	8782	1			T1	2		T3	14		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31276

1

T1

2

T2

6

T3

23

values[0x0]

all_enables

biggest_size

234728

1

T1

21

T2

20

T3

243

values[0x1]

all_enables

biggest_size

31257

1

T1

3

T2

1

T3

37