Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	334451558	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334451558	0	0
T1	233712	4134	0	0
T2	5611872	99583	0	0
T3	3030384	63737	0	0
T4	5114984	225513	0	0
T14	2274328	33684	0	0
T16	182504	5623	0	0
T17	28696136	530610	0	0
T18	4156712	98618	0	0
T19	24396848	1904315	0	0
T20	4455976	101690	0	0
T21	66842	5885	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	242368	240240	0	0
T2	5611872	5606888	0	0
T3	3030384	3029936	0	0
T4	5114984	5005672	0	0
T14	2274328	2272032	0	0
T16	182504	178976	0	0
T17	28696136	28691880	0	0
T18	4156712	4154696	0	0
T19	24396848	24396456	0	0
T20	4455976	4418344	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	242368	240240	0	0
T2	5611872	5606888	0	0
T3	3030384	3029936	0	0
T4	5114984	5005672	0	0
T14	2274328	2272032	0	0
T16	182504	178976	0	0
T17	28696136	28691880	0	0
T18	4156712	4154696	0	0
T19	24396848	24396456	0	0
T20	4455976	4418344	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	242368	240240	0	0
T2	5611872	5606888	0	0
T3	3030384	3029936	0	0
T4	5114984	5005672	0	0
T14	2274328	2272032	0	0
T16	182504	178976	0	0
T17	28696136	28691880	0	0
T18	4156712	4154696	0	0
T19	24396848	24396456	0	0
T20	4455976	4418344	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T14	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	123839195	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	123839195	0	0
T1	4328	1846	0	0
T2	100212	97376	0	0
T3	54114	28370	0	0
T4	91339	84045	0	0
T14	40613	15170	0	0
T16	3259	2784	0	0
T17	512431	214826	0	0
T18	74227	38724	0	0
T19	435658	21554	0	0
T20	79571	40313	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	87020180	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	87020180	0	0
T1	4328	541	0	0
T2	100212	660	0	0
T3	54114	8438	0	0
T4	91339	49721	0	0
T14	40613	5405	0	0
T16	3259	1413	0	0
T17	512431	81809	0	0
T18	74227	19906	0	0
T19	435658	169200	0	0
T20	79571	20491	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1444634	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1444634	0	0
T1	4328	54	0	0
T2	100212	36	0	0
T3	54114	854	0	0
T4	91339	2757	0	0
T14	40613	437	0	0
T16	3259	21	0	0
T17	512431	2653	0	0
T18	74227	657	0	0
T19	435658	0	0	0
T20	79571	853	0	0
T21	0	156	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	2156790	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	2156790	0	0
T1	4328	19	0	0
T2	100212	8	0	0
T3	54114	367	0	0
T4	91339	2757	0	0
T14	40613	123	0	0
T16	3259	21	0	0
T17	512431	1243	0	0
T18	74227	704	0	0
T19	435658	0	0	0
T20	79571	896	0	0
T21	0	126	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1396861	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1396861	0	0
T1	4328	49	0	0
T2	100212	47	0	0
T3	54114	758	0	0
T4	91339	1200	0	0
T14	40613	349	0	0
T16	3259	34	0	0
T17	512431	6603	0	0
T18	74227	696	0	0
T19	435658	1163	0	0
T20	79571	577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3281315	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3281315	0	0
T1	4328	24	0	0
T2	100212	10	0	0
T3	54114	307	0	0
T4	91339	1199	0	0
T14	40613	191	0	0
T16	3259	34	0	0
T17	512431	2969	0	0
T18	74227	775	0	0
T19	435658	99298	0	0
T20	79571	568	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1374867	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1374867	0	0
T1	4328	64	0	0
T2	100212	24	0	0
T3	54114	642	0	0
T4	91339	1732	0	0
T14	40613	347	0	0
T16	3259	22	0	0
T17	512431	3091	0	0
T18	74227	925	0	0
T19	435658	0	0	0
T20	79571	843	0	0
T21	0	164	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	2796819	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	2796819	0	0
T1	4328	23	0	0
T2	100212	7	0	0
T3	54114	277	0	0
T4	91339	1732	0	0
T14	40613	139	0	0
T16	3259	22	0	0
T17	512431	1434	0	0
T18	74227	837	0	0
T19	435658	0	0	0
T20	79571	961	0	0
T21	0	152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1434489	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1434489	0	0
T1	4328	10	0	0
T2	100212	11	0	0
T3	54114	586	0	0
T4	91339	1297	0	0
T14	40613	324	0	0
T16	3259	30	0	0
T17	512431	4839	0	0
T18	74227	763	0	0
T19	435658	1285	0	0
T20	79571	588	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3231132	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3231132	0	0
T1	4328	17	0	0
T2	100212	447	0	0
T3	54114	358	0	0
T4	91339	1297	0	0
T14	40613	171	0	0
T16	3259	30	0	0
T17	512431	1995	0	0
T18	74227	871	0	0
T19	435658	95386	0	0
T20	79571	610	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1380996	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1380996	0	0
T1	4328	56	0	0
T2	100212	35	0	0
T3	54114	595	0	0
T4	91339	1311	0	0
T14	40613	341	0	0
T16	3259	26	0	0
T17	512431	4877	0	0
T18	74227	553	0	0
T19	435658	950	0	0
T20	79571	655	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3131195	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3131195	0	0
T1	4328	20	0	0
T2	100212	8	0	0
T3	54114	283	0	0
T4	91339	1311	0	0
T14	40613	184	0	0
T16	3259	26	0	0
T17	512431	2167	0	0
T18	74227	558	0	0
T19	435658	75343	0	0
T20	79571	813	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1414726	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1414726	0	0
T2	100212	34	0	0
T3	54114	854	0	0
T4	91339	1487	0	0
T14	40613	393	0	0
T16	3259	21	0	0
T17	512431	4081	0	0
T18	74227	735	0	0
T19	435658	3613	0	0
T20	79571	715	0	0
T21	33421	277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3421569	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3421569	0	0
T2	100212	7	0	0
T3	54114	435	0	0
T4	91339	1487	0	0
T14	40613	182	0	0
T16	3259	21	0	0
T17	512431	2395	0	0
T18	74227	785	0	0
T19	435658	270646	0	0
T20	79571	630	0	0
T21	33421	210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1396524	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1396524	0	0
T1	4328	33	0	0
T2	100212	21	0	0
T3	54114	607	0	0
T4	91339	1243	0	0
T14	40613	312	0	0
T16	3259	18	0	0
T17	512431	6330	0	0
T18	74227	693	0	0
T19	435658	2129	0	0
T20	79571	773	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3367523	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3367523	0	0
T1	4328	31	0	0
T2	100212	4	0	0
T3	54114	319	0	0
T4	91339	1243	0	0
T14	40613	161	0	0
T16	3259	18	0	0
T17	512431	3668	0	0
T18	74227	680	0	0
T19	435658	167549	0	0
T20	79571	770	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1383930	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1383930	0	0
T1	4328	36	0	0
T2	100212	55	0	0
T3	54114	701	0	0
T4	91339	1957	0	0
T14	40613	222	0	0
T16	3259	33	0	0
T17	512431	2784	0	0
T18	74227	763	0	0
T19	435658	2130	0	0
T20	79571	620	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3015491	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3015491	0	0
T1	4328	14	0	0
T2	100212	9	0	0
T3	54114	348	0	0
T4	91339	1957	0	0
T14	40613	115	0	0
T16	3259	33	0	0
T17	512431	1445	0	0
T18	74227	751	0	0
T19	435658	166651	0	0
T20	79571	552	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1365517	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1365517	0	0
T1	4328	7	0	0
T2	100212	26	0	0
T3	54114	732	0	0
T4	91339	1223	0	0
T14	40613	435	0	0
T16	3259	27	0	0
T17	512431	7494	0	0
T18	74227	836	0	0
T19	435658	1230	0	0
T20	79571	963	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	2892660	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	2892660	0	0
T1	4328	12	0	0
T2	100212	5	0	0
T3	54114	395	0	0
T4	91339	1223	0	0
T14	40613	185	0	0
T16	3259	27	0	0
T17	512431	4176	0	0
T18	74227	805	0	0
T19	435658	105023	0	0
T20	79571	789	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1368319	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1368319	0	0
T1	4328	66	0	0
T2	100212	46	0	0
T3	54114	634	0	0
T4	91339	1979	0	0
T14	40613	285	0	0
T16	3259	32	0	0
T17	512431	2783	0	0
T18	74227	732	0	0
T19	435658	900	0	0
T20	79571	801	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3260037	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3260037	0	0
T1	4328	16	0	0
T2	100212	10	0	0
T3	54114	329	0	0
T4	91339	1979	0	0
T14	40613	80	0	0
T16	3259	32	0	0
T17	512431	1414	0	0
T18	74227	795	0	0
T19	435658	71802	0	0
T20	79571	829	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1396510	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1396510	0	0
T1	4328	98	0	0
T2	100212	18	0	0
T3	54114	786	0	0
T4	91339	1236	0	0
T14	40613	340	0	0
T16	3259	19	0	0
T17	512431	2649	0	0
T18	74227	804	0	0
T19	435658	3289	0	0
T20	79571	750	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	4127696	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	4127696	0	0
T1	4328	27	0	0
T2	100212	5	0	0
T3	54114	367	0	0
T4	91339	1236	0	0
T14	40613	107	0	0
T16	3259	19	0	0
T17	512431	1243	0	0
T18	74227	698	0	0
T19	435658	265067	0	0
T20	79571	671	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1363249	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1363249	0	0
T1	4328	42	0	0
T2	100212	15	0	0
T3	54114	523	0	0
T4	91339	2021	0	0
T14	40613	311	0	0
T16	3259	23	0	0
T17	512431	8888	0	0
T18	74227	762	0	0
T19	435658	0	0	0
T20	79571	703	0	0
T21	0	251	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3127213	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3127213	0	0
T1	4328	22	0	0
T2	100212	3	0	0
T3	54114	279	0	0
T4	91339	2021	0	0
T14	40613	166	0	0
T16	3259	23	0	0
T17	512431	5138	0	0
T18	74227	662	0	0
T19	435658	0	0	0
T20	79571	744	0	0
T21	0	189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1340553	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1340553	0	0
T1	4328	34	0	0
T2	100212	18	0	0
T3	54114	558	0	0
T4	91339	1633	0	0
T14	40613	318	0	0
T16	3259	34	0	0
T17	512431	5052	0	0
T18	74227	778	0	0
T19	435658	0	0	0
T20	79571	668	0	0
T21	0	114	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3703275	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3703275	0	0
T1	4328	36	0	0
T2	100212	3	0	0
T3	54114	231	0	0
T4	91339	1633	0	0
T14	40613	141	0	0
T16	3259	34	0	0
T17	512431	2729	0	0
T18	74227	849	0	0
T19	435658	0	0	0
T20	79571	737	0	0
T21	0	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1383706	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1383706	0	0
T1	4328	18	0	0
T2	100212	56	0	0
T3	54114	660	0	0
T4	91339	1065	0	0
T14	40613	338	0	0
T16	3259	23	0	0
T17	512431	6130	0	0
T18	74227	766	0	0
T19	435658	1352	0	0
T20	79571	839	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	2900146	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	2900146	0	0
T1	4328	1	0	0
T2	100212	13	0	0
T3	54114	319	0	0
T4	91339	1065	0	0
T14	40613	208	0	0
T16	3259	23	0	0
T17	512431	3882	0	0
T18	74227	841	0	0
T19	435658	103245	0	0
T20	79571	630	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1405910	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1405910	0	0
T1	4328	51	0	0
T2	100212	26	0	0
T3	54114	733	0	0
T4	91339	1728	0	0
T14	40613	331	0	0
T16	3259	14	0	0
T17	512431	5002	0	0
T18	74227	657	0	0
T19	435658	0	0	0
T20	79571	772	0	0
T21	0	286	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	2658922	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	2658922	0	0
T1	4328	24	0	0
T2	100212	10	0	0
T3	54114	332	0	0
T4	91339	1727	0	0
T14	40613	124	0	0
T16	3259	14	0	0
T17	512431	2261	0	0
T18	74227	631	0	0
T19	435658	0	0	0
T20	79571	811	0	0
T21	0	185	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1386086	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1386086	0	0
T1	4328	89	0	0
T2	100212	33	0	0
T3	54114	558	0	0
T4	91339	1799	0	0
T14	40613	394	0	0
T16	3259	32	0	0
T17	512431	9014	0	0
T18	74227	710	0	0
T19	435658	0	0	0
T20	79571	806	0	0
T21	0	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	2877351	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	2877351	0	0
T1	4328	40	0	0
T2	100212	6	0	0
T3	54114	306	0	0
T4	91339	1798	0	0
T14	40613	204	0	0
T16	3259	32	0	0
T17	512431	5618	0	0
T18	74227	716	0	0
T19	435658	0	0	0
T20	79571	721	0	0
T21	0	181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1417351	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1417351	0	0
T1	4328	36	0	0
T2	100212	49	0	0
T3	54114	787	0	0
T4	91339	1836	0	0
T14	40613	336	0	0
T16	3259	34	0	0
T17	512431	6981	0	0
T18	74227	764	0	0
T19	435658	857	0	0
T20	79571	791	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3366021	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3366021	0	0
T1	4328	17	0	0
T2	100212	19	0	0
T3	54114	265	0	0
T4	91339	1836	0	0
T14	40613	164	0	0
T16	3259	34	0	0
T17	512431	3453	0	0
T18	74227	643	0	0
T19	435658	72328	0	0
T20	79571	718	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1400291	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1400291	0	0
T1	4328	93	0	0
T2	100212	50	0	0
T3	54114	846	0	0
T4	91339	2401	0	0
T14	40613	230	0	0
T16	3259	32	0	0
T17	512431	4995	0	0
T18	74227	662	0	0
T19	435658	1404	0	0
T20	79571	790	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3240562	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3240562	0	0
T1	4328	36	0	0
T2	100212	13	0	0
T3	54114	361	0	0
T4	91339	2401	0	0
T14	40613	85	0	0
T16	3259	32	0	0
T17	512431	2234	0	0
T18	74227	803	0	0
T19	435658	106589	0	0
T20	79571	708	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1368804	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1368804	0	0
T1	4328	95	0	0
T2	100212	15	0	0
T3	54114	761	0	0
T4	91339	2812	0	0
T14	40613	242	0	0
T16	3259	15	0	0
T17	512431	3034	0	0
T18	74227	821	0	0
T19	435658	1251	0	0
T20	79571	669	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3142198	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3142198	0	0
T1	4328	43	0	0
T2	100212	6	0	0
T3	54114	276	0	0
T4	91339	2812	0	0
T14	40613	127	0	0
T16	3259	15	0	0
T17	512431	1423	0	0
T18	74227	725	0	0
T19	435658	93081	0	0
T20	79571	712	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1409478	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1409478	0	0
T1	4328	49	0	0
T2	100212	33	0	0
T3	54114	578	0	0
T4	91339	1658	0	0
T14	40613	311	0	0
T16	3259	33	0	0
T17	512431	6631	0	0
T18	74227	814	0	0
T19	435658	0	0	0
T20	79571	620	0	0
T21	0	246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3726757	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3726757	0	0
T1	4328	22	0	0
T2	100212	12	0	0
T3	54114	285	0	0
T4	91339	1658	0	0
T14	40613	155	0	0
T16	3259	33	0	0
T17	512431	3631	0	0
T18	74227	796	0	0
T19	435658	0	0	0
T20	79571	571	0	0
T21	0	256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1441783	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1441783	0	0
T1	4328	16	0	0
T2	100212	22	0	0
T3	54114	854	0	0
T4	91339	1603	0	0
T14	40613	207	0	0
T16	3259	27	0	0
T17	512431	5033	0	0
T18	74227	881	0	0
T19	435658	0	0	0
T20	79571	1260	0	0
T21	0	280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3087477	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3087477	0	0
T1	4328	10	0	0
T2	100212	6	0	0
T3	54114	379	0	0
T4	91339	1603	0	0
T14	40613	135	0	0
T16	3259	27	0	0
T17	512431	2580	0	0
T18	74227	842	0	0
T19	435658	0	0	0
T20	79571	1217	0	0
T21	0	266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1426783	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1426783	0	0
T1	4328	45	0	0
T2	100212	40	0	0
T3	54114	732	0	0
T4	91339	1971	0	0
T14	40613	360	0	0
T16	3259	32	0	0
T17	512431	12110	0	0
T18	74227	807	0	0
T19	435658	0	0	0
T20	79571	773	0	0
T21	0	226	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	2938225	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	2938225	0	0
T1	4328	17	0	0
T2	100212	7	0	0
T3	54114	318	0	0
T4	91339	1971	0	0
T14	40613	186	0	0
T16	3259	32	0	0
T17	512431	5955	0	0
T18	74227	728	0	0
T19	435658	0	0	0
T20	79571	771	0	0
T21	0	185	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1402598	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1402598	0	0
T1	4328	22	0	0
T2	100212	26	0	0
T3	54114	513	0	0
T4	91339	1261	0	0
T14	40613	320	0	0
T16	3259	22	0	0
T17	512431	8219	0	0
T18	74227	599	0	0
T19	435658	0	0	0
T20	79571	1136	0	0
T21	0	174	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	2993417	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	2993417	0	0
T1	4328	9	0	0
T2	100212	7	0	0
T3	54114	191	0	0
T4	91339	1261	0	0
T14	40613	141	0	0
T16	3259	22	0	0
T17	512431	4118	0	0
T18	74227	716	0	0
T19	435658	0	0	0
T20	79571	1084	0	0
T21	0	188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1410999	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1410999	0	0
T1	4328	10	0	0
T2	100212	19	0	0
T3	54114	744	0	0
T4	91339	1224	0	0
T14	40613	338	0	0
T16	3259	22	0	0
T17	512431	2761	0	0
T18	74227	707	0	0
T19	435658	0	0	0
T20	79571	632	0	0
T21	0	230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3294614	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3294614	0	0
T1	4328	7	0	0
T2	100212	5	0	0
T3	54114	308	0	0
T4	91339	1224	0	0
T14	40613	157	0	0
T16	3259	22	0	0
T17	512431	1427	0	0
T18	74227	740	0	0
T19	435658	0	0	0
T20	79571	618	0	0
T21	0	263	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1425048	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1425048	0	0
T1	4328	69	0	0
T2	100212	70	0	0
T3	54114	638	0	0
T4	91339	1498	0	0
T14	40613	326	0	0
T16	3259	31	0	0
T17	512431	9136	0	0
T18	74227	824	0	0
T19	435658	0	0	0
T20	79571	749	0	0
T21	0	172	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3330033	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3330033	0	0
T1	4328	25	0	0
T2	100212	15	0	0
T3	54114	262	0	0
T4	91339	1498	0	0
T14	40613	168	0	0
T16	3259	31	0	0
T17	512431	4369	0	0
T18	74227	782	0	0
T19	435658	0	0	0
T20	79571	537	0	0
T21	0	197	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1377853	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1377853	0	0
T1	4328	21	0	0
T2	100212	42	0	0
T3	54114	604	0	0
T4	91339	1865	0	0
T14	40613	482	0	0
T16	3259	27	0	0
T17	512431	6883	0	0
T18	74227	702	0	0
T19	435658	0	0	0
T20	79571	732	0	0
T21	0	177	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3526050	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3526050	0	0
T1	4328	6	0	0
T2	100212	10	0	0
T3	54114	296	0	0
T4	91339	1865	0	0
T14	40613	231	0	0
T16	3259	27	0	0
T17	512431	3746	0	0
T18	74227	540	0	0
T19	435658	0	0	0
T20	79571	742	0	0
T21	0	157	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	1441806	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	1441806	0	0
T1	4328	43	0	0
T2	100212	20	0	0
T3	54114	655	0	0
T4	91339	2078	0	0
T14	40613	319	0	0
T16	3259	29	0	0
T17	512431	5999	0	0
T18	74227	676	0	0
T19	435658	0	0	0
T20	79571	674	0	0
T21	0	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	299630131	3238024	0	0
DepthKnown_A	299630131	299493907	0	0
RvalidKnown_A	299630131	299493907	0	0
WreadyKnown_A	299630131	299493907	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	3238024	0	0
T1	4328	23	0	0
T2	100212	5	0	0
T3	54114	243	0	0
T4	91339	2078	0	0
T14	40613	131	0	0
T16	3259	29	0	0
T17	512431	3210	0	0
T18	74227	628	0	0
T19	435658	0	0	0
T20	79571	724	0	0
T21	0	131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	299630131	299493907	0	0
T1	4328	4290	0	0
T2	100212	100123	0	0
T3	54114	54106	0	0
T4	91339	89387	0	0
T14	40613	40572	0	0
T16	3259	3196	0	0
T17	512431	512355	0	0
T18	74227	74191	0	0
T19	435658	435651	0	0
T20	79571	78899	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0