Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1831773	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

289025

1

T1

269

T2

2

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	716441	1			T1	583		T2	5		T3	42
values[0x0]	688045	1			T1	608		T2	1		T3	50
values[0x1]	716312	1			T1	594		T2	8		T3	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1421742	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

699056

1

T1

642

T2

5

T3

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7873	1			T1	8		T14	10		T5	1
valid_sources[0x01]	8512	1			T1	9		T14	17		T20	7
valid_sources[0x02]	8215	1			T1	6		T3	71		T14	9
valid_sources[0x03]	8648	1			T1	7		T14	9		T20	7
valid_sources[0x04]	8208	1			T1	7		T14	8		T20	4
valid_sources[0x05]	8358	1			T1	7		T14	16		T20	2
valid_sources[0x06]	8475	1			T1	7		T14	6		T17	31
valid_sources[0x07]	8034	1			T1	6		T14	10		T5	31
valid_sources[0x08]	8037	1			T1	7		T14	9		T20	12
valid_sources[0x09]	7483	1			T1	7		T14	24		T20	3
valid_sources[0x0a]	9332	1			T1	6		T4	1		T14	8
valid_sources[0x0b]	9115	1			T1	6		T4	7		T14	12
valid_sources[0x0c]	7972	1			T1	8		T4	1		T14	9
valid_sources[0x0d]	8259	1			T1	6		T14	1		T20	8
valid_sources[0x0e]	8425	1			T1	7		T14	19		T20	9
valid_sources[0x0f]	8314	1			T1	6		T14	5		T20	6
valid_sources[0x10]	8004	1			T1	7		T14	10		T17	45
valid_sources[0x11]	8689	1			T1	9		T2	2		T14	11
valid_sources[0x12]	8631	1			T1	6		T14	16		T20	16
valid_sources[0x13]	8441	1			T1	6		T14	7		T20	12
valid_sources[0x14]	8153	1			T1	7		T14	16		T20	2
valid_sources[0x15]	9009	1			T1	8		T14	4		T20	9
valid_sources[0x16]	7637	1			T1	7		T14	13		T20	3
valid_sources[0x17]	8025	1			T1	7		T4	1		T14	4
valid_sources[0x18]	7513	1			T1	7		T14	7		T20	11
valid_sources[0x19]	9000	1			T1	8		T14	12		T20	3
valid_sources[0x1a]	8891	1			T1	9		T14	12		T5	50
valid_sources[0x1b]	8374	1			T1	6		T14	9		T20	8
valid_sources[0x1c]	8116	1			T1	6		T14	14		T20	7
valid_sources[0x1d]	8156	1			T1	6		T4	6		T14	24
valid_sources[0x1e]	8210	1			T1	8		T14	11		T20	11
valid_sources[0x1f]	8107	1			T1	6		T4	2		T14	17
valid_sources[0x20]	8265	1			T1	6		T14	5		T5	48
valid_sources[0x21]	8097	1			T1	8		T14	11		T20	13
valid_sources[0x22]	7963	1			T1	6		T14	17		T20	8
valid_sources[0x23]	7666	1			T1	7		T14	7		T20	8
valid_sources[0x24]	8104	1			T1	8		T14	11		T19	2
valid_sources[0x25]	8413	1			T1	7		T14	3		T20	5
valid_sources[0x26]	8314	1			T1	9		T14	12		T20	18
valid_sources[0x27]	8377	1			T1	7		T14	12		T5	82
valid_sources[0x28]	7680	1			T1	8		T14	14		T20	2
valid_sources[0x29]	8026	1			T1	6		T14	9		T20	4
valid_sources[0x2a]	8898	1			T1	7		T14	10		T17	37
valid_sources[0x2b]	7655	1			T1	7		T4	1		T14	5
valid_sources[0x2c]	8710	1			T1	6		T4	4		T14	8
valid_sources[0x2d]	8286	1			T1	8		T14	11		T20	6
valid_sources[0x2e]	8222	1			T1	6		T14	16		T20	2
valid_sources[0x2f]	8621	1			T1	7		T14	10		T19	2
valid_sources[0x30]	8479	1			T1	8		T14	8		T20	10
valid_sources[0x31]	7966	1			T1	7		T14	13		T5	1
valid_sources[0x32]	7867	1			T1	6		T14	10		T20	5
valid_sources[0x33]	7878	1			T1	7		T14	27		T5	112
valid_sources[0x34]	9262	1			T1	7		T14	7		T20	9
valid_sources[0x35]	8940	1			T1	6		T14	6		T20	12
valid_sources[0x36]	8373	1			T1	7		T14	10		T20	3
valid_sources[0x37]	8117	1			T1	9		T14	9		T20	12
valid_sources[0x38]	8768	1			T1	7		T14	15		T20	2
valid_sources[0x39]	8436	1			T1	7		T14	10		T19	1
valid_sources[0x3a]	8306	1			T1	6		T4	2		T14	16
valid_sources[0x3b]	8206	1			T1	7		T14	11		T20	19
valid_sources[0x3c]	8139	1			T1	7		T4	1		T14	9
valid_sources[0x3d]	8156	1			T1	6		T14	16		T5	46
valid_sources[0x3e]	8791	1			T1	7		T14	6		T19	4
valid_sources[0x3f]	7761	1			T1	8		T14	12		T20	3
valid_sources[0x40]	8359	1			T1	8		T4	1		T14	15
valid_sources[0x41]	8178	1			T1	7		T14	9		T20	2
valid_sources[0x42]	7957	1			T1	7		T14	16		T20	1
valid_sources[0x43]	8097	1			T1	7		T14	12		T20	1
valid_sources[0x44]	8768	1			T1	8		T14	18		T20	8
valid_sources[0x45]	8459	1			T1	8		T14	15		T20	4
valid_sources[0x46]	8106	1			T1	6		T14	5		T20	1
valid_sources[0x47]	7948	1			T1	7		T14	7		T19	2
valid_sources[0x48]	8890	1			T1	6		T14	21		T20	14
valid_sources[0x49]	7623	1			T1	7		T14	8		T20	4
valid_sources[0x4a]	8384	1			T1	7		T14	8		T20	5
valid_sources[0x4b]	8503	1			T1	6		T14	4		T20	3
valid_sources[0x4c]	8101	1			T1	7		T14	3		T19	3
valid_sources[0x4d]	8306	1			T1	7		T14	7		T20	1
valid_sources[0x4e]	8136	1			T1	6		T14	15		T20	10
valid_sources[0x4f]	8046	1			T1	6		T14	28		T19	7
valid_sources[0x50]	7738	1			T1	8		T14	11		T5	17
valid_sources[0x51]	7881	1			T1	6		T2	1		T4	1
valid_sources[0x52]	10628	1			T1	5		T14	5		T20	1
valid_sources[0x53]	8113	1			T1	9		T4	1		T14	14
valid_sources[0x54]	7905	1			T1	5		T14	17		T20	16
valid_sources[0x55]	8034	1			T1	7		T14	13		T5	9
valid_sources[0x56]	8387	1			T1	7		T4	4		T14	8
valid_sources[0x57]	8071	1			T1	8		T14	15		T19	1
valid_sources[0x58]	7693	1			T1	6		T14	12		T20	4
valid_sources[0x59]	7924	1			T1	7		T14	8		T20	29
valid_sources[0x5a]	8283	1			T1	7		T14	14		T5	69
valid_sources[0x5b]	8503	1			T1	6		T14	12		T19	2
valid_sources[0x5c]	7883	1			T1	8		T14	6		T20	5
valid_sources[0x5d]	8190	1			T1	7		T4	1		T14	9
valid_sources[0x5e]	7713	1			T1	9		T2	1		T14	10
valid_sources[0x5f]	8472	1			T1	7		T14	21		T20	1
valid_sources[0x60]	8384	1			T1	8		T14	15		T20	3
valid_sources[0x61]	9044	1			T1	6		T4	2		T14	14
valid_sources[0x62]	9302	1			T1	6		T14	21		T5	3
valid_sources[0x63]	8666	1			T1	8		T14	20		T20	5
valid_sources[0x64]	7789	1			T1	8		T4	1		T14	13
valid_sources[0x65]	7686	1			T1	6		T14	16		T20	2
valid_sources[0x66]	9006	1			T1	7		T3	30		T4	2
valid_sources[0x67]	7897	1			T1	7		T14	13		T20	7
valid_sources[0x68]	8613	1			T1	8		T14	12		T20	4
valid_sources[0x69]	8406	1			T1	7		T14	14		T20	1
valid_sources[0x6a]	7703	1			T1	7		T4	1		T14	10
valid_sources[0x6b]	9276	1			T1	6		T14	27		T20	7
valid_sources[0x6c]	9175	1			T1	6		T14	7		T20	10
valid_sources[0x6d]	7897	1			T1	6		T14	20		T20	4
valid_sources[0x6e]	8195	1			T1	8		T4	4		T14	7
valid_sources[0x6f]	7500	1			T1	7		T14	7		T20	7
valid_sources[0x70]	7755	1			T1	10		T4	1		T14	6
valid_sources[0x71]	8220	1			T1	7		T14	4		T20	18
valid_sources[0x72]	8433	1			T1	7		T14	14		T20	8
valid_sources[0x73]	7636	1			T1	7		T14	14		T20	14
valid_sources[0x74]	7456	1			T1	6		T14	1		T20	7
valid_sources[0x75]	9314	1			T1	6		T4	2		T14	7
valid_sources[0x76]	7736	1			T1	7		T14	7		T5	13
valid_sources[0x77]	8268	1			T1	7		T2	3		T14	17
valid_sources[0x78]	8013	1			T1	7		T14	8		T20	5
valid_sources[0x79]	8511	1			T1	8		T14	12		T20	3
valid_sources[0x7a]	8484	1			T1	9		T14	10		T20	8
valid_sources[0x7b]	7666	1			T1	7		T14	5		T19	6
valid_sources[0x7c]	8083	1			T1	7		T14	18		T20	21
valid_sources[0x7d]	8261	1			T1	6		T4	2		T14	15
valid_sources[0x7e]	8263	1			T1	7		T4	1		T14	7
valid_sources[0x7f]	7921	1			T1	7		T14	7		T20	3
valid_sources[0x80]	8889	1			T1	7		T14	13		T21	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30439

1

T1

25

T2

1

T3

2

values[0x0]

all_enables

biggest_size

228161

1

T1

224

T3

14

T4

7

values[0x1]

all_enables

biggest_size

30425

1

T1

20

T2

1

T3

5