Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	308777606	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	308777606	0	0
T1	2046192	1310632	0	0
T2	313092	7692	0	0
T3	40040	699	0	0
T4	5088048	117953	0	0
T5	7950880	1480702	0	0
T14	2906120	66322	0	0
T15	43300	5490	0	0
T17	943432	42920	0	0
T18	14843796	156017	0	0
T19	45304	614	0	0
T20	7765464	1300527	0	0
T21	4167856	60660	0	0
T22	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9548896	9548728	0	0
T2	324688	323960	0	0
T3	40040	37576	0	0
T4	5088048	5083736	0	0
T5	7950880	7950432	0	0
T14	2906120	2905616	0	0
T17	943432	941864	0	0
T19	45304	40096	0	0
T20	7765464	7765352	0	0
T21	4167856	4166008	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9548896	9548728	0	0
T2	324688	323960	0	0
T3	40040	37576	0	0
T4	5088048	5083736	0	0
T5	7950880	7950432	0	0
T14	2906120	2905616	0	0
T17	943432	941864	0	0
T19	45304	40096	0	0
T20	7765464	7765352	0	0
T21	4167856	4166008	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9548896	9548728	0	0
T2	324688	323960	0	0
T3	40040	37576	0	0
T4	5088048	5083736	0	0
T5	7950880	7950432	0	0
T14	2906120	2905616	0	0
T17	943432	941864	0	0
T19	45304	40096	0	0
T20	7765464	7765352	0	0
T21	4167856	4166008	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T14	56	56	0	0
T17	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	118003178	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	118003178	0	0
T1	170516	8279	0	0
T2	5798	2886	0	0
T3	715	273	0	0
T4	90858	48297	0	0
T5	141980	690759	0	0
T14	51895	21231	0	0
T17	16847	16519	0	0
T19	809	239	0	0
T20	138669	137003	0	0
T21	74426	14661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	76989259	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	76989259	0	0
T1	170516	647037	0	0
T2	5798	2712	0	0
T3	715	142	0	0
T4	90858	23331	0	0
T5	141980	159000	0	0
T14	51895	11932	0	0
T17	16847	9115	0	0
T19	809	125	0	0
T20	138669	578386	0	0
T21	74426	15719	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1386377	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1386377	0	0
T2	5798	48	0	0
T3	715	2	0	0
T4	90858	800	0	0
T5	141980	20812	0	0
T14	51895	1151	0	0
T17	16847	378	0	0
T18	337359	8006	0	0
T19	809	5	0	0
T20	138669	296	0	0
T21	74426	476	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2744641	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2744641	0	0
T2	5798	14	0	0
T3	715	2	0	0
T4	90858	869	0	0
T5	141980	6022	0	0
T14	51895	904	0	0
T17	16847	378	0	0
T18	337359	3892	0	0
T19	809	5	0	0
T20	138669	22415	0	0
T21	74426	461	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1407266	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1407266	0	0
T2	5798	37	0	0
T3	715	8	0	0
T4	90858	927	0	0
T5	141980	18247	0	0
T14	51895	0	0	0
T15	0	210	0	0
T17	16847	193	0	0
T18	337359	4621	0	0
T19	809	5	0	0
T20	138669	178	0	0
T21	74426	646	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2625082	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2625082	0	0
T2	5798	43	0	0
T3	715	8	0	0
T4	90858	950	0	0
T5	141980	7523	0	0
T14	51895	0	0	0
T15	0	120	0	0
T17	16847	193	0	0
T18	337359	2062	0	0
T19	809	5	0	0
T20	138669	18979	0	0
T21	74426	631	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1410810	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1410810	0	0
T2	5798	51	0	0
T3	715	2	0	0
T4	90858	927	0	0
T5	141980	17672	0	0
T14	51895	0	0	0
T15	0	256	0	0
T17	16847	164	0	0
T18	337359	2557	0	0
T19	809	3	0	0
T20	138669	232	0	0
T21	74426	489	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2945929	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2945929	0	0
T2	5798	72	0	0
T3	715	2	0	0
T4	90858	890	0	0
T5	141980	4105	0	0
T14	51895	0	0	0
T15	0	219	0	0
T17	16847	164	0	0
T18	337359	1318	0	0
T19	809	3	0	0
T20	138669	19811	0	0
T21	74426	486	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1411846	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1411846	0	0
T2	5798	46	0	0
T3	715	1	0	0
T4	90858	775	0	0
T5	141980	13661	0	0
T14	51895	1624	0	0
T17	16847	459	0	0
T18	337359	3839	0	0
T19	809	7	0	0
T20	138669	217	0	0
T21	74426	606	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2849307	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2849307	0	0
T2	5798	52	0	0
T3	715	1	0	0
T4	90858	687	0	0
T5	141980	3553	0	0
T14	51895	848	0	0
T17	16847	459	0	0
T18	337359	1938	0	0
T19	809	7	0	0
T20	138669	18383	0	0
T21	74426	513	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1378862	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1378862	0	0
T2	5798	74	0	0
T3	715	10	0	0
T4	90858	875	0	0
T5	141980	19912	0	0
T14	51895	2280	0	0
T17	16847	710	0	0
T18	337359	2697	0	0
T19	809	4	0	0
T20	138669	220	0	0
T21	74426	575	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2822007	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2822007	0	0
T2	5798	27	0	0
T3	715	10	0	0
T4	90858	887	0	0
T5	141980	5382	0	0
T14	51895	1083	0	0
T17	16847	710	0	0
T18	337359	1279	0	0
T19	809	4	0	0
T20	138669	22320	0	0
T21	74426	625	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1388906	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1388906	0	0
T2	5798	23	0	0
T3	715	0	0	0
T4	90858	817	0	0
T5	141980	12471	0	0
T14	51895	0	0	0
T15	0	291	0	0
T17	16847	424	0	0
T18	337359	4569	0	0
T19	809	7	0	0
T20	138669	260	0	0
T21	74426	515	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2871006	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2871006	0	0
T2	5798	24	0	0
T3	715	0	0	0
T4	90858	825	0	0
T5	141980	5245	0	0
T14	51895	0	0	0
T15	0	246	0	0
T17	16847	424	0	0
T18	337359	2106	0	0
T19	809	7	0	0
T20	138669	17932	0	0
T21	74426	611	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1359012	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1359012	0	0
T1	170516	1026	0	0
T2	5798	20	0	0
T3	715	6	0	0
T4	90858	902	0	0
T5	141980	19075	0	0
T14	51895	0	0	0
T17	16847	172	0	0
T18	0	7204	0	0
T19	809	1	0	0
T20	138669	288	0	0
T21	74426	422	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2786267	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2786267	0	0
T1	170516	82301	0	0
T2	5798	28	0	0
T3	715	6	0	0
T4	90858	793	0	0
T5	141980	7122	0	0
T14	51895	0	0	0
T17	16847	172	0	0
T18	0	4125	0	0
T19	809	1	0	0
T20	138669	25286	0	0
T21	74426	551	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1405830	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1405830	0	0
T2	5798	40	0	0
T3	715	4	0	0
T4	90858	970	0	0
T5	141980	22590	0	0
T14	51895	1226	0	0
T17	16847	193	0	0
T18	337359	4264	0	0
T19	809	8	0	0
T20	138669	234	0	0
T21	74426	600	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2836678	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2836678	0	0
T2	5798	32	0	0
T3	715	4	0	0
T4	90858	1019	0	0
T5	141980	5839	0	0
T14	51895	982	0	0
T17	16847	193	0	0
T18	337359	2177	0	0
T19	809	8	0	0
T20	138669	18290	0	0
T21	74426	566	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1382229	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1382229	0	0
T2	5798	26	0	0
T3	715	6	0	0
T4	90858	924	0	0
T5	141980	17592	0	0
T14	51895	1669	0	0
T17	16847	441	0	0
T18	337359	2141	0	0
T19	809	1	0	0
T20	138669	237	0	0
T21	74426	421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2392673	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2392673	0	0
T2	5798	30	0	0
T3	715	6	0	0
T4	90858	1020	0	0
T5	141980	5510	0	0
T14	51895	789	0	0
T17	16847	441	0	0
T18	337359	1128	0	0
T19	809	1	0	0
T20	138669	20576	0	0
T21	74426	449	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1385831	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1385831	0	0
T2	5798	53	0	0
T3	715	9	0	0
T4	90858	805	0	0
T5	141980	14363	0	0
T14	51895	0	0	0
T15	0	239	0	0
T17	16847	458	0	0
T18	337359	4695	0	0
T19	809	4	0	0
T20	138669	225	0	0
T21	74426	525	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2004607	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2004607	0	0
T2	5798	53	0	0
T3	715	9	0	0
T4	90858	824	0	0
T5	141980	4306	0	0
T14	51895	0	0	0
T15	0	193	0	0
T17	16847	458	0	0
T18	337359	2247	0	0
T19	809	4	0	0
T20	138669	19212	0	0
T21	74426	595	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1426321	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1426321	0	0
T2	5798	37	0	0
T3	715	3	0	0
T4	90858	1012	0	0
T5	141980	16835	0	0
T14	51895	0	0	0
T15	0	260	0	0
T17	16847	667	0	0
T18	337359	6460	0	0
T19	809	1	0	0
T20	138669	217	0	0
T21	74426	584	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2679396	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2679396	0	0
T2	5798	58	0	0
T3	715	3	0	0
T4	90858	953	0	0
T5	141980	5340	0	0
T14	51895	0	0	0
T15	0	166	0	0
T17	16847	667	0	0
T18	337359	2922	0	0
T19	809	1	0	0
T20	138669	21063	0	0
T21	74426	530	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1450417	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1450417	0	0
T2	5798	37	0	0
T3	715	4	0	0
T4	90858	794	0	0
T5	141980	20559	0	0
T14	51895	0	0	0
T15	0	214	0	0
T17	16847	169	0	0
T18	337359	2446	0	0
T19	809	4	0	0
T20	138669	244	0	0
T21	74426	541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2786785	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2786785	0	0
T2	5798	45	0	0
T3	715	4	0	0
T4	90858	858	0	0
T5	141980	7944	0	0
T14	51895	0	0	0
T15	0	141	0	0
T17	16847	169	0	0
T18	337359	1117	0	0
T19	809	4	0	0
T20	138669	19422	0	0
T21	74426	545	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1347155	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1347155	0	0
T2	5798	59	0	0
T3	715	6	0	0
T4	90858	767	0	0
T5	141980	19410	0	0
T14	51895	0	0	0
T15	0	192	0	0
T17	16847	167	0	0
T18	337359	2708	0	0
T19	809	5	0	0
T20	138669	244	0	0
T21	74426	740	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2984819	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2984819	0	0
T2	5798	79	0	0
T3	715	6	0	0
T4	90858	711	0	0
T5	141980	8308	0	0
T14	51895	0	0	0
T15	0	191	0	0
T17	16847	167	0	0
T18	337359	1205	0	0
T19	809	5	0	0
T20	138669	20287	0	0
T21	74426	730	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1396049	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1396049	0	0
T2	5798	61	0	0
T3	715	4	0	0
T4	90858	873	0	0
T5	141980	16055	0	0
T14	51895	2115	0	0
T17	16847	161	0	0
T18	337359	3462	0	0
T19	809	3	0	0
T20	138669	247	0	0
T21	74426	482	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2485913	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2485913	0	0
T2	5798	29	0	0
T3	715	4	0	0
T4	90858	772	0	0
T5	141980	4774	0	0
T14	51895	1043	0	0
T17	16847	161	0	0
T18	337359	2190	0	0
T19	809	3	0	0
T20	138669	21741	0	0
T21	74426	487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1384898	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1384898	0	0
T1	170516	3556	0	0
T2	5798	48	0	0
T3	715	6	0	0
T4	90858	843	0	0
T5	141980	13806	0	0
T14	51895	0	0	0
T17	16847	397	0	0
T18	0	2613	0	0
T19	809	8	0	0
T20	138669	288	0	0
T21	74426	458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	3287359	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	3287359	0	0
T1	170516	282519	0	0
T2	5798	38	0	0
T3	715	6	0	0
T4	90858	957	0	0
T5	141980	3465	0	0
T14	51895	0	0	0
T17	16847	397	0	0
T18	0	1280	0	0
T19	809	8	0	0
T20	138669	24584	0	0
T21	74426	578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1417779	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1417779	0	0
T1	170516	961	0	0
T2	5798	24	0	0
T3	715	4	0	0
T4	90858	833	0	0
T5	141980	16680	0	0
T14	51895	0	0	0
T17	16847	161	0	0
T18	0	2375	0	0
T19	809	9	0	0
T20	138669	260	0	0
T21	74426	562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	3422686	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	3422686	0	0
T1	170516	74661	0	0
T2	5798	41	0	0
T3	715	4	0	0
T4	90858	765	0	0
T5	141980	4506	0	0
T14	51895	0	0	0
T17	16847	161	0	0
T18	0	1173	0	0
T19	809	9	0	0
T20	138669	25265	0	0
T21	74426	691	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1408940	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1408940	0	0
T2	5798	32	0	0
T3	715	7	0	0
T4	90858	858	0	0
T5	141980	17815	0	0
T14	51895	0	0	0
T15	0	204	0	0
T17	16847	179	0	0
T18	337359	4583	0	0
T19	809	7	0	0
T20	138669	266	0	0
T21	74426	547	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2429017	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2429017	0	0
T2	5798	34	0	0
T3	715	7	0	0
T4	90858	907	0	0
T5	141980	3682	0	0
T14	51895	0	0	0
T15	0	134	0	0
T17	16847	179	0	0
T18	337359	1926	0	0
T19	809	7	0	0
T20	138669	22681	0	0
T21	74426	637	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1384038	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1384038	0	0
T2	5798	24	0	0
T3	715	8	0	0
T4	90858	885	0	0
T5	141980	17005	0	0
T14	51895	0	0	0
T15	0	237	0	0
T17	16847	679	0	0
T18	337359	2597	0	0
T19	809	6	0	0
T20	138669	316	0	0
T21	74426	641	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2522652	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2522652	0	0
T2	5798	31	0	0
T3	715	8	0	0
T4	90858	779	0	0
T5	141980	5856	0	0
T14	51895	0	0	0
T15	0	251	0	0
T17	16847	679	0	0
T18	337359	1279	0	0
T19	809	6	0	0
T20	138669	29864	0	0
T21	74426	612	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1364650	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1364650	0	0
T1	170516	1282	0	0
T2	5798	74	0	0
T3	715	6	0	0
T4	90858	801	0	0
T5	141980	15177	0	0
T14	51895	2235	0	0
T17	16847	170	0	0
T19	809	2	0	0
T20	138669	295	0	0
T21	74426	554	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2556354	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2556354	0	0
T1	170516	106321	0	0
T2	5798	73	0	0
T3	715	6	0	0
T4	90858	917	0	0
T5	141980	7577	0	0
T14	51895	1025	0	0
T17	16847	170	0	0
T19	809	2	0	0
T20	138669	22353	0	0
T21	74426	639	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1434010	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1434010	0	0
T3	715	4	0	0
T4	90858	708	0	0
T5	141980	20670	0	0
T14	51895	0	0	0
T15	21650	290	0	0
T17	16847	160	0	0
T18	337359	2320	0	0
T19	809	6	0	0
T20	138669	315	0	0
T21	74426	550	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	3543335	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	3543335	0	0
T3	715	4	0	0
T4	90858	706	0	0
T5	141980	7604	0	0
T14	51895	0	0	0
T15	21650	289	0	0
T17	16847	160	0	0
T18	337359	1195	0	0
T19	809	6	0	0
T20	138669	23500	0	0
T21	74426	524	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1347692	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1347692	0	0
T2	5798	31	0	0
T3	715	5	0	0
T4	90858	990	0	0
T5	141980	16048	0	0
T14	51895	0	0	0
T15	0	220	0	0
T17	16847	397	0	0
T18	337359	4426	0	0
T19	809	4	0	0
T20	138669	245	0	0
T21	74426	395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	3013185	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	3013185	0	0
T2	5798	17	0	0
T3	715	5	0	0
T4	90858	948	0	0
T5	141980	7107	0	0
T14	51895	0	0	0
T15	0	177	0	0
T17	16847	397	0	0
T18	337359	2284	0	0
T19	809	4	0	0
T20	138669	24087	0	0
T21	74426	368	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1478187	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1478187	0	0
T2	5798	76	0	0
T3	715	6	0	0
T4	90858	948	0	0
T5	141980	14874	0	0
T14	51895	2510	0	0
T17	16847	432	0	0
T18	337359	3821	0	0
T19	809	3	0	0
T20	138669	384	0	0
T21	74426	651	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2916373	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2916373	0	0
T2	5798	83	0	0
T3	715	6	0	0
T4	90858	984	0	0
T5	141980	5260	0	0
T14	51895	2130	0	0
T17	16847	432	0	0
T18	337359	1807	0	0
T19	809	3	0	0
T20	138669	27093	0	0
T21	74426	733	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1368484	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1368484	0	0
T2	5798	37	0	0
T3	715	8	0	0
T4	90858	844	0	0
T5	141980	15048	0	0
T14	51895	4281	0	0
T17	16847	181	0	0
T18	337359	2923	0	0
T19	809	5	0	0
T20	138669	198	0	0
T21	74426	546	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2967754	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2967754	0	0
T2	5798	40	0	0
T3	715	8	0	0
T4	90858	885	0	0
T5	141980	3654	0	0
T14	51895	2036	0	0
T17	16847	181	0	0
T18	337359	1259	0	0
T19	809	5	0	0
T20	138669	16178	0	0
T21	74426	513	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1408048	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1408048	0	0
T2	5798	41	0	0
T3	715	6	0	0
T4	90858	767	0	0
T5	141980	19044	0	0
T14	51895	0	0	0
T15	0	234	0	0
T17	16847	178	0	0
T18	337359	6947	0	0
T19	809	1	0	0
T20	138669	326	0	0
T21	74426	608	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2662721	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2662721	0	0
T2	5798	40	0	0
T3	715	6	0	0
T4	90858	964	0	0
T5	141980	6525	0	0
T14	51895	0	0	0
T15	0	202	0	0
T17	16847	178	0	0
T18	337359	3382	0	0
T19	809	1	0	0
T20	138669	22137	0	0
T21	74426	701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1369471	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1369471	0	0
T1	170516	1454	0	0
T2	5798	33	0	0
T3	715	2	0	0
T4	90858	698	0	0
T5	141980	17127	0	0
T14	51895	0	0	0
T17	16847	403	0	0
T18	0	4660	0	0
T19	809	5	0	0
T20	138669	239	0	0
T21	74426	498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	3278728	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	3278728	0	0
T1	170516	101235	0	0
T2	5798	34	0	0
T3	715	2	0	0
T4	90858	709	0	0
T5	141980	6543	0	0
T14	51895	0	0	0
T17	16847	403	0	0
T18	0	2126	0	0
T19	809	5	0	0
T20	138669	19967	0	0
T21	74426	469	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1331518	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1331518	0	0
T2	5798	12	0	0
T3	715	10	0	0
T4	90858	885	0	0
T5	141980	19462	0	0
T14	51895	2138	0	0
T17	16847	387	0	0
T18	337359	5017	0	0
T19	809	8	0	0
T20	138669	212	0	0
T21	74426	478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2700406	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2700406	0	0
T2	5798	13	0	0
T3	715	10	0	0
T4	90858	952	0	0
T5	141980	7891	0	0
T14	51895	1090	0	0
T17	16847	387	0	0
T18	337359	2418	0	0
T19	809	8	0	0
T20	138669	18093	0	0
T21	74426	633	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	1439621	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	1439621	0	0
T2	5798	11	0	0
T3	715	5	0	0
T4	90858	793	0	0
T5	141980	19933	0	0
T14	51895	0	0	0
T15	0	169	0	0
T17	16847	163	0	0
T18	337359	2966	0	0
T19	809	3	0	0
T20	138669	209	0	0
T21	74426	541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282279256	2995242	0	0
DepthKnown_A	282279256	282149835	0	0
RvalidKnown_A	282279256	282149835	0	0
WreadyKnown_A	282279256	282149835	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	2995242	0	0
T2	5798	9	0	0
T3	715	5	0	0
T4	90858	773	0	0
T5	141980	8357	0	0
T14	51895	0	0	0
T15	0	145	0	0
T17	16847	163	0	0
T18	337359	1265	0	0
T19	809	3	0	0
T20	138669	16727	0	0
T21	74426	751	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282279256	282149835	0	0
T1	170516	170513	0	0
T2	5798	5785	0	0
T3	715	671	0	0
T4	90858	90781	0	0
T5	141980	141972	0	0
T14	51895	51886	0	0
T17	16847	16819	0	0
T19	809	716	0	0
T20	138669	138667	0	0
T21	74426	74393	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0