Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1690533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

265945

1

T1

38

T2

199

T3

176

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	662572	1			T1	93		T2	473		T3	367
values[0x0]	630866	1			T1	98		T2	489		T3	365
values[0x1]	663040	1			T1	75		T2	491		T3	383

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1310459	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

646019

1

T1

86

T2

468

T3

391

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7639	1			T2	7		T3	5		T5	8
valid_sources[0x01]	7069	1			T2	6		T3	4		T5	8
valid_sources[0x02]	7667	1			T1	2		T2	4		T3	6
valid_sources[0x03]	7099	1			T1	1		T2	6		T3	2
valid_sources[0x04]	6891	1			T1	2		T2	6		T3	5
valid_sources[0x05]	7156	1			T1	4		T2	6		T3	4
valid_sources[0x06]	7194	1			T1	1		T2	5		T3	3
valid_sources[0x07]	7547	1			T2	5		T3	3		T5	8
valid_sources[0x08]	8536	1			T2	6		T3	7		T5	9
valid_sources[0x09]	7054	1			T2	5		T3	2		T5	8
valid_sources[0x0a]	7306	1			T2	6		T3	2		T5	8
valid_sources[0x0b]	7187	1			T2	5		T3	4		T5	8
valid_sources[0x0c]	7493	1			T2	6		T3	4		T5	8
valid_sources[0x0d]	8046	1			T2	6		T3	4		T5	9
valid_sources[0x0e]	7859	1			T2	6		T3	2		T5	8
valid_sources[0x0f]	8640	1			T2	4		T3	7		T5	6
valid_sources[0x10]	7611	1			T1	4		T2	6		T3	2
valid_sources[0x11]	7190	1			T2	6		T3	5		T5	9
valid_sources[0x12]	8359	1			T2	6		T3	2		T5	7
valid_sources[0x13]	7216	1			T1	3		T2	6		T3	1
valid_sources[0x14]	7254	1			T1	2		T2	5		T3	3
valid_sources[0x15]	7157	1			T2	5		T3	4		T5	8
valid_sources[0x16]	7145	1			T2	6		T5	10		T4	9
valid_sources[0x17]	8653	1			T2	6		T3	5		T5	6
valid_sources[0x18]	7707	1			T2	6		T3	2		T5	9
valid_sources[0x19]	7387	1			T2	6		T3	4		T5	10
valid_sources[0x1a]	7833	1			T2	5		T3	3		T5	8
valid_sources[0x1b]	7551	1			T1	4		T2	6		T3	3
valid_sources[0x1c]	7350	1			T2	6		T3	3		T5	7
valid_sources[0x1d]	7433	1			T2	6		T3	1		T5	7
valid_sources[0x1e]	7876	1			T2	5		T3	1		T5	8
valid_sources[0x1f]	8152	1			T1	1		T2	5		T3	1
valid_sources[0x20]	7946	1			T1	1		T2	5		T3	1
valid_sources[0x21]	7687	1			T1	3		T2	6		T3	2
valid_sources[0x22]	7183	1			T1	1		T2	7		T3	4
valid_sources[0x23]	7164	1			T1	1		T2	6		T3	2
valid_sources[0x24]	8005	1			T2	5		T3	5		T5	6
valid_sources[0x25]	8112	1			T1	3		T2	6		T3	4
valid_sources[0x26]	8573	1			T1	1		T2	5		T3	27
valid_sources[0x27]	7591	1			T2	5		T3	3		T5	8
valid_sources[0x28]	7392	1			T2	7		T3	1		T5	9
valid_sources[0x29]	7564	1			T1	3		T2	6		T3	1
valid_sources[0x2a]	7467	1			T1	5		T2	6		T3	4
valid_sources[0x2b]	8779	1			T2	6		T3	4		T5	9
valid_sources[0x2c]	9446	1			T2	7		T3	4		T5	6
valid_sources[0x2d]	6921	1			T1	3		T2	4		T3	4
valid_sources[0x2e]	8132	1			T2	6		T3	4		T5	8
valid_sources[0x2f]	7803	1			T1	2		T2	5		T3	3
valid_sources[0x30]	8560	1			T2	6		T3	4		T5	8
valid_sources[0x31]	9161	1			T2	5		T3	4		T5	10
valid_sources[0x32]	8475	1			T2	5		T3	3		T5	9
valid_sources[0x33]	8442	1			T1	3		T2	5		T3	5
valid_sources[0x34]	7030	1			T1	3		T2	7		T3	3
valid_sources[0x35]	7808	1			T1	2		T2	6		T3	3
valid_sources[0x36]	6842	1			T2	7		T3	7		T5	8
valid_sources[0x37]	7476	1			T2	6		T3	4		T5	8
valid_sources[0x38]	7686	1			T2	6		T3	1		T5	8
valid_sources[0x39]	7620	1			T1	1		T2	6		T3	4
valid_sources[0x3a]	7156	1			T2	6		T3	5		T5	8
valid_sources[0x3b]	8237	1			T1	2		T2	4		T3	2
valid_sources[0x3c]	7111	1			T2	6		T3	2		T5	7
valid_sources[0x3d]	8313	1			T1	5		T2	7		T5	9
valid_sources[0x3e]	8476	1			T1	1		T2	6		T3	4
valid_sources[0x3f]	7279	1			T1	4		T2	7		T3	7
valid_sources[0x40]	6916	1			T1	2		T2	6		T3	2
valid_sources[0x41]	7989	1			T2	6		T3	21		T5	8
valid_sources[0x42]	7280	1			T1	2		T2	5		T3	22
valid_sources[0x43]	8534	1			T2	6		T3	3		T5	7
valid_sources[0x44]	8589	1			T2	6		T3	6		T5	9
valid_sources[0x45]	7442	1			T1	1		T2	5		T3	4
valid_sources[0x46]	7447	1			T1	5		T2	6		T3	3
valid_sources[0x47]	8146	1			T2	6		T5	8		T6	5
valid_sources[0x48]	8166	1			T1	1		T2	7		T3	15
valid_sources[0x49]	7559	1			T1	1		T2	6		T3	1
valid_sources[0x4a]	7137	1			T1	3		T2	5		T3	3
valid_sources[0x4b]	6716	1			T1	1		T2	6		T3	3
valid_sources[0x4c]	7729	1			T2	6		T3	1		T5	8
valid_sources[0x4d]	7441	1			T2	6		T3	5		T5	8
valid_sources[0x4e]	7766	1			T2	9		T3	22		T5	8
valid_sources[0x4f]	7971	1			T1	8		T2	5		T3	2
valid_sources[0x50]	7485	1			T2	6		T3	3		T5	6
valid_sources[0x51]	7021	1			T1	2		T2	6		T3	5
valid_sources[0x52]	7577	1			T1	2		T2	5		T3	7
valid_sources[0x53]	7708	1			T2	5		T3	3		T5	9
valid_sources[0x54]	7276	1			T2	6		T3	2		T5	8
valid_sources[0x55]	7022	1			T1	2		T2	6		T3	4
valid_sources[0x56]	7055	1			T1	10		T2	5		T3	3
valid_sources[0x57]	10231	1			T2	6		T3	3		T5	7
valid_sources[0x58]	7226	1			T2	4		T3	2		T5	8
valid_sources[0x59]	7163	1			T2	5		T3	2		T5	9
valid_sources[0x5a]	7609	1			T2	6		T3	3		T5	6
valid_sources[0x5b]	6923	1			T1	4		T2	7		T3	4
valid_sources[0x5c]	7030	1			T2	6		T3	16		T5	8
valid_sources[0x5d]	6998	1			T2	4		T3	7		T5	9
valid_sources[0x5e]	7097	1			T2	6		T3	4		T5	8
valid_sources[0x5f]	7882	1			T2	5		T3	2		T5	7
valid_sources[0x60]	7189	1			T2	5		T3	3		T5	9
valid_sources[0x61]	8150	1			T1	1		T2	7		T3	3
valid_sources[0x62]	8918	1			T1	1		T2	5		T3	9
valid_sources[0x63]	7377	1			T2	6		T3	4		T5	8
valid_sources[0x64]	7574	1			T2	8		T3	3		T5	8
valid_sources[0x65]	7839	1			T2	4		T3	11		T5	9
valid_sources[0x66]	7383	1			T1	6		T2	6		T3	5
valid_sources[0x67]	7570	1			T1	3		T2	6		T3	3
valid_sources[0x68]	8576	1			T2	7		T5	8		T6	19
valid_sources[0x69]	8922	1			T2	6		T3	9		T5	8
valid_sources[0x6a]	6815	1			T2	6		T3	5		T5	10
valid_sources[0x6b]	8927	1			T2	5		T3	1		T5	10
valid_sources[0x6c]	7124	1			T2	5		T3	5		T5	9
valid_sources[0x6d]	7337	1			T1	6		T2	7		T3	5
valid_sources[0x6e]	7192	1			T2	3		T3	8		T5	7
valid_sources[0x6f]	7562	1			T2	5		T3	3		T5	7
valid_sources[0x70]	7475	1			T2	6		T3	3		T5	8
valid_sources[0x71]	6978	1			T1	2		T2	4		T3	6
valid_sources[0x72]	6974	1			T2	6		T3	2		T5	8
valid_sources[0x73]	8379	1			T2	6		T3	5		T5	7
valid_sources[0x74]	7775	1			T1	4		T2	6		T3	4
valid_sources[0x75]	7852	1			T1	3		T2	4		T3	4
valid_sources[0x76]	7509	1			T2	6		T5	9		T6	6
valid_sources[0x77]	7638	1			T2	6		T3	15		T5	8
valid_sources[0x78]	7340	1			T1	5		T2	6		T3	3
valid_sources[0x79]	8218	1			T2	5		T3	7		T5	8
valid_sources[0x7a]	7862	1			T2	5		T3	6		T5	7
valid_sources[0x7b]	7699	1			T1	2		T2	5		T3	6
valid_sources[0x7c]	7064	1			T1	1		T2	5		T3	6
valid_sources[0x7d]	7402	1			T1	1		T2	5		T3	4
valid_sources[0x7e]	7779	1			T2	5		T3	3		T5	9
valid_sources[0x7f]	7810	1			T1	2		T2	5		T3	3
valid_sources[0x80]	7438	1			T2	6		T3	2		T5	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28412

1

T1

2

T2

22

T3

20

values[0x0]

all_enables

biggest_size

209249

1

T1

32

T2

157

T3

137

values[0x1]

all_enables

biggest_size

28284

1

T1

4

T2

20

T3

19