Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	342046109	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	342046109	0	0
T1	14812728	281185	0	0
T2	6954192	1018168	0	0
T3	1468208	27502	0	0
T4	14047656	1491926	0	0
T5	11354112	1543338	0	0
T6	86016	4600	0	0
T17	93072	2898	0	0
T18	1471512	68052	0	0
T19	5736584	171666	0	0
T20	3188920	56600	0	0
T21	0	39555	0	0
T22	0	31780	0	0
T23	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14812728	14809704	0	0
T2	6954192	6953856	0	0
T3	1468208	1429400	0	0
T4	14047656	14047600	0	0
T5	11354112	11354000	0	0
T6	86016	84000	0	0
T17	93072	91560	0	0
T18	1471512	1469328	0	0
T19	5736584	5736192	0	0
T20	3188920	3188136	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14812728	14809704	0	0
T2	6954192	6953856	0	0
T3	1468208	1429400	0	0
T4	14047656	14047600	0	0
T5	11354112	11354000	0	0
T6	86016	84000	0	0
T17	93072	91560	0	0
T18	1471512	1469328	0	0
T19	5736584	5736192	0	0
T20	3188920	3188136	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14812728	14809704	0	0
T2	6954192	6953856	0	0
T3	1468208	1429400	0	0
T4	14047656	14047600	0	0
T5	11354112	11354000	0	0
T6	86016	84000	0	0
T17	93072	91560	0	0
T18	1471512	1469328	0	0
T19	5736584	5736192	0	0
T20	3188920	3188136	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	125373159	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	125373159	0	0
T1	264513	134279	0	0
T2	124182	6801	0	0
T3	26218	12803	0	0
T4	250851	108508	0	0
T5	202752	9315	0	0
T6	1536	1150	0	0
T17	1662	1424	0	0
T18	26277	25938	0	0
T19	102439	99738	0	0
T20	56945	55058	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	87706884	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	87706884	0	0
T1	264513	29973	0	0
T2	124182	502283	0	0
T3	26218	3484	0	0
T4	250851	304625	0	0
T5	202752	762354	0	0
T6	1536	1150	0	0
T17	1662	728	0	0
T18	26277	15532	0	0
T19	102439	35751	0	0
T20	56945	515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1590582	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1590582	0	0
T1	264513	3658	0	0
T2	124182	0	0	0
T3	26218	290	0	0
T4	250851	35487	0	0
T5	202752	1042	0	0
T6	1536	0	0	0
T17	1662	16	0	0
T18	26277	616	0	0
T19	102439	8	0	0
T20	56945	16	0	0
T21	0	715	0	0
T22	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3621535	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3621535	0	0
T1	264513	2484	0	0
T2	124182	0	0	0
T3	26218	88	0	0
T4	250851	11692	0	0
T5	202752	81260	0	0
T6	1536	0	0	0
T17	1662	16	0	0
T18	26277	616	0	0
T19	102439	1060	0	0
T20	56945	4	0	0
T21	0	714	0	0
T22	0	3333	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1537975	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1537975	0	0
T1	264513	5044	0	0
T2	124182	1066	0	0
T3	26218	245	0	0
T4	250851	21508	0	0
T5	202752	0	0	0
T6	1536	208	0	0
T17	1662	16	0	0
T18	26277	190	0	0
T19	102439	12	0	0
T20	56945	9	0	0
T21	0	537	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	2855282	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	2855282	0	0
T1	264513	1476	0	0
T2	124182	78565	0	0
T3	26218	117	0	0
T4	250851	8833	0	0
T5	202752	0	0	0
T6	1536	208	0	0
T17	1662	16	0	0
T18	26277	190	0	0
T19	102439	1481	0	0
T20	56945	1	0	0
T21	0	536	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1564260	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1564260	0	0
T1	264513	4853	0	0
T2	124182	1116	0	0
T3	26218	225	0	0
T4	250851	31028	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	13	0	0
T18	26277	410	0	0
T19	102439	27	0	0
T20	56945	13	0	0
T21	0	613	0	0
T22	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3269919	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3269919	0	0
T1	264513	1766	0	0
T2	124182	85188	0	0
T3	26218	161	0	0
T4	250851	12761	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	13	0	0
T18	26277	410	0	0
T19	102439	2433	0	0
T20	56945	4	0	0
T21	0	613	0	0
T22	0	1365	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1550734	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1550734	0	0
T1	264513	2462	0	0
T2	124182	0	0	0
T3	26218	169	0	0
T4	250851	31934	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	17	0	0
T18	26277	172	0	0
T19	102439	24	0	0
T20	56945	16	0	0
T21	0	597	0	0
T22	0	6	0	0
T23	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3184303	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3184303	0	0
T1	264513	541	0	0
T2	124182	0	0	0
T3	26218	109	0	0
T4	250851	13603	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	17	0	0
T18	26277	172	0	0
T19	102439	3151	0	0
T20	56945	5	0	0
T21	0	597	0	0
T22	0	831	0	0
T23	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1521935	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1521935	0	0
T1	264513	2426	0	0
T2	124182	0	0	0
T3	26218	232	0	0
T4	250851	22606	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	12	0	0
T18	26277	1187	0	0
T19	102439	15	0	0
T20	56945	32	0	0
T21	0	830	0	0
T22	0	4	0	0
T23	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	2985628	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	2985628	0	0
T1	264513	1631	0	0
T2	124182	0	0	0
T3	26218	114	0	0
T4	250851	8348	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	12	0	0
T18	26277	1187	0	0
T19	102439	610	0	0
T20	56945	6	0	0
T21	0	830	0	0
T22	0	541	0	0
T23	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1536799	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1536799	0	0
T1	264513	4707	0	0
T2	124182	0	0	0
T3	26218	238	0	0
T4	250851	28516	0	0
T5	202752	0	0	0
T6	1536	268	0	0
T17	1662	11	0	0
T18	26277	474	0	0
T19	102439	18	0	0
T20	56945	20	0	0
T21	0	940	0	0
T22	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3184344	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3184344	0	0
T1	264513	1103	0	0
T2	124182	0	0	0
T3	26218	92	0	0
T4	250851	11841	0	0
T5	202752	0	0	0
T6	1536	268	0	0
T17	1662	11	0	0
T18	26277	474	0	0
T19	102439	1352	0	0
T20	56945	6	0	0
T21	0	940	0	0
T22	0	1060	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1572812	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1572812	0	0
T1	264513	1500	0	0
T2	124182	0	0	0
T3	26218	177	0	0
T4	250851	23649	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	13	0	0
T18	26277	915	0	0
T19	102439	12	0	0
T20	56945	34	0	0
T21	0	841	0	0
T22	0	19	0	0
T23	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3639220	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3639220	0	0
T1	264513	773	0	0
T2	124182	0	0	0
T3	26218	65	0	0
T4	250851	8455	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	13	0	0
T18	26277	915	0	0
T19	102439	658	0	0
T20	56945	6	0	0
T21	0	841	0	0
T22	0	706	0	0
T23	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1527446	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1527446	0	0
T1	264513	2560	0	0
T2	124182	0	0	0
T3	26218	213	0	0
T4	250851	18293	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	14	0	0
T18	26277	688	0	0
T19	102439	9	0	0
T20	56945	31	0	0
T21	0	583	0	0
T22	0	3	0	0
T23	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3273447	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3273447	0	0
T1	264513	2308	0	0
T2	124182	0	0	0
T3	26218	95	0	0
T4	250851	7615	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	14	0	0
T18	26277	688	0	0
T19	102439	437	0	0
T20	56945	7	0	0
T21	0	583	0	0
T22	0	958	0	0
T23	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1570486	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1570486	0	0
T1	264513	5818	0	0
T2	124182	0	0	0
T3	26218	270	0	0
T4	250851	27826	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	16	0	0
T18	26277	487	0	0
T19	102439	10	0	0
T20	56945	13	0	0
T21	0	349	0	0
T22	0	4	0	0
T23	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3334304	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3334304	0	0
T1	264513	2495	0	0
T2	124182	0	0	0
T3	26218	86	0	0
T4	250851	10239	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	16	0	0
T18	26277	487	0	0
T19	102439	790	0	0
T20	56945	4	0	0
T21	0	349	0	0
T22	0	641	0	0
T23	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1619249	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1619249	0	0
T1	264513	4808	0	0
T2	124182	0	0	0
T3	26218	708	0	0
T4	250851	28994	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	7	0	0
T18	26277	177	0	0
T19	102439	27	0	0
T20	56945	15	0	0
T21	0	582	0	0
T22	0	18	0	0
T23	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	2941207	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	2941207	0	0
T1	264513	1866	0	0
T2	124182	0	0	0
T3	26218	328	0	0
T4	250851	10972	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	7	0	0
T18	26277	177	0	0
T19	102439	1697	0	0
T20	56945	3	0	0
T21	0	582	0	0
T22	0	1445	0	0
T23	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1591050	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1591050	0	0
T1	264513	1976	0	0
T2	124182	0	0	0
T3	26218	167	0	0
T4	250851	37073	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	16	0	0
T18	26277	674	0	0
T19	102439	4	0	0
T20	56945	17	0	0
T21	0	1052	0	0
T22	0	22	0	0
T23	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	2661782	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	2661782	0	0
T1	264513	866	0	0
T2	124182	0	0	0
T3	26218	45	0	0
T4	250851	15314	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	16	0	0
T18	26277	674	0	0
T19	102439	402	0	0
T20	56945	3	0	0
T21	0	1052	0	0
T22	0	2671	0	0
T23	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1567983	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1567983	0	0
T1	264513	1602	0	0
T2	124182	0	0	0
T3	26218	206	0	0
T4	250851	33746	0	0
T5	202752	0	0	0
T6	1536	234	0	0
T17	1662	13	0	0
T18	26277	431	0	0
T19	102439	19	0	0
T20	56945	14	0	0
T21	0	1340	0	0
T22	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3952951	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3952951	0	0
T1	264513	218	0	0
T2	124182	0	0	0
T3	26218	84	0	0
T4	250851	9932	0	0
T5	202752	0	0	0
T6	1536	234	0	0
T17	1662	13	0	0
T18	26277	431	0	0
T19	102439	1351	0	0
T20	56945	4	0	0
T21	0	1340	0	0
T22	0	1474	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1577269	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1577269	0	0
T1	264513	1702	0	0
T2	124182	0	0	0
T3	26218	210	0	0
T4	250851	30613	0	0
T5	202752	967	0	0
T6	1536	0	0	0
T17	1662	13	0	0
T18	26277	191	0	0
T19	102439	19	0	0
T20	56945	19	0	0
T21	0	605	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3458334	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3458334	0	0
T1	264513	761	0	0
T2	124182	0	0	0
T3	26218	84	0	0
T4	250851	11484	0	0
T5	202752	83833	0	0
T6	1536	0	0	0
T17	1662	13	0	0
T18	26277	191	0	0
T19	102439	2357	0	0
T20	56945	5	0	0
T21	0	604	0	0
T22	0	1120	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1553668	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1553668	0	0
T1	264513	2346	0	0
T2	124182	1019	0	0
T3	26218	144	0	0
T4	250851	27002	0	0
T5	202752	1151	0	0
T6	1536	0	0	0
T17	1662	24	0	0
T18	26277	368	0	0
T19	102439	17	0	0
T20	56945	11	0	0
T21	0	887	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	4095602	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	4095602	0	0
T1	264513	1196	0	0
T2	124182	68319	0	0
T3	26218	55	0	0
T4	250851	9742	0	0
T5	202752	90374	0	0
T6	1536	0	0	0
T17	1662	24	0	0
T18	26277	368	0	0
T19	102439	922	0	0
T20	56945	5	0	0
T21	0	886	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1623209	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1623209	0	0
T1	264513	3891	0	0
T2	124182	0	0	0
T3	26218	1333	0	0
T4	250851	23173	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	11	0	0
T18	26277	193	0	0
T19	102439	21	0	0
T20	56945	24	0	0
T21	0	369	0	0
T22	0	19	0	0
T23	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3603043	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3603043	0	0
T1	264513	308	0	0
T2	124182	0	0	0
T3	26218	566	0	0
T4	250851	14075	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	11	0	0
T18	26277	193	0	0
T19	102439	1577	0	0
T20	56945	401	0	0
T21	0	369	0	0
T22	0	1247	0	0
T23	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1605875	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1605875	0	0
T1	264513	4034	0	0
T2	124182	1352	0	0
T3	26218	171	0	0
T4	250851	30778	0	0
T5	202752	3285	0	0
T6	1536	0	0	0
T17	1662	9	0	0
T18	26277	1009	0	0
T19	102439	19	0	0
T20	56945	25	0	0
T21	0	379	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3375884	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3375884	0	0
T1	264513	1214	0	0
T2	124182	100798	0	0
T3	26218	69	0	0
T4	250851	8988	0	0
T5	202752	265212	0	0
T6	1536	0	0	0
T17	1662	9	0	0
T18	26277	1009	0	0
T19	102439	2775	0	0
T20	56945	4	0	0
T21	0	379	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1530799	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1530799	0	0
T1	264513	4289	0	0
T2	124182	0	0	0
T3	26218	249	0	0
T4	250851	27893	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	14	0	0
T18	26277	691	0	0
T19	102439	21	0	0
T20	56945	9	0	0
T21	0	362	0	0
T22	0	10	0	0
T23	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	2681997	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	2681997	0	0
T1	264513	1641	0	0
T2	124182	0	0	0
T3	26218	120	0	0
T4	250851	12509	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	14	0	0
T18	26277	691	0	0
T19	102439	1799	0	0
T20	56945	3	0	0
T21	0	362	0	0
T22	0	1133	0	0
T23	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1580688	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1580688	0	0
T1	264513	2645	0	0
T2	124182	0	0	0
T3	26218	241	0	0
T4	250851	23948	0	0
T5	202752	1068	0	0
T6	1536	0	0	0
T17	1662	8	0	0
T18	26277	786	0	0
T19	102439	39	0	0
T20	56945	13	0	0
T21	0	346	0	0
T22	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3085627	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3085627	0	0
T1	264513	1038	0	0
T2	124182	0	0	0
T3	26218	111	0	0
T4	250851	10778	0	0
T5	202752	86621	0	0
T6	1536	0	0	0
T17	1662	8	0	0
T18	26277	786	0	0
T19	102439	1592	0	0
T20	56945	3	0	0
T21	0	346	0	0
T22	0	1134	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1578810	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1578810	0	0
T1	264513	2918	0	0
T2	124182	0	0	0
T3	26218	489	0	0
T4	250851	25601	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	13	0	0
T18	26277	415	0	0
T19	102439	12	0	0
T20	56945	30	0	0
T21	0	592	0	0
T22	0	12	0	0
T23	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	2601244	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	2601244	0	0
T1	264513	711	0	0
T2	124182	0	0	0
T3	26218	221	0	0
T4	250851	11219	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	13	0	0
T18	26277	415	0	0
T19	102439	665	0	0
T20	56945	8	0	0
T21	0	592	0	0
T22	0	818	0	0
T23	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1573235	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1573235	0	0
T1	264513	1742	0	0
T2	124182	0	0	0
T3	26218	191	0	0
T4	250851	22682	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	13	0	0
T18	26277	635	0	0
T19	102439	21	0	0
T20	56945	22	0	0
T21	0	454	0	0
T22	0	2	0	0
T23	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3317474	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3317474	0	0
T1	264513	290	0	0
T2	124182	0	0	0
T3	26218	55	0	0
T4	250851	8423	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	13	0	0
T18	26277	635	0	0
T19	102439	857	0	0
T20	56945	4	0	0
T21	0	453	0	0
T22	0	299	0	0
T23	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1581517	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1581517	0	0
T1	264513	2495	0	0
T2	124182	0	0	0
T3	26218	221	0	0
T4	250851	34454	0	0
T5	202752	903	0	0
T6	1536	0	0	0
T17	1662	15	0	0
T18	26277	179	0	0
T19	102439	15	0	0
T20	56945	28	0	0
T21	0	836	0	0
T22	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3037650	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3037650	0	0
T1	264513	1104	0	0
T2	124182	0	0	0
T3	26218	98	0	0
T4	250851	13615	0	0
T5	202752	76049	0	0
T6	1536	0	0	0
T17	1662	15	0	0
T18	26277	179	0	0
T19	102439	1344	0	0
T20	56945	6	0	0
T21	0	836	0	0
T22	0	1982	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1591252	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1591252	0	0
T1	264513	3796	0	0
T2	124182	0	0	0
T3	26218	207	0	0
T4	250851	34434	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	17	0	0
T18	26277	189	0	0
T19	102439	8	0	0
T20	56945	27	0	0
T21	0	1235	0	0
T22	0	15	0	0
T23	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	2985100	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	2985100	0	0
T1	264513	1126	0	0
T2	124182	0	0	0
T3	26218	60	0	0
T4	250851	15334	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	17	0	0
T18	26277	189	0	0
T19	102439	2428	0	0
T20	56945	4	0	0
T21	0	1235	0	0
T22	0	513	0	0
T23	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1490520	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1490520	0	0
T1	264513	5343	0	0
T2	124182	0	0	0
T3	26218	197	0	0
T4	250851	29957	0	0
T5	202752	0	0	0
T6	1536	232	0	0
T17	1662	17	0	0
T18	26277	182	0	0
T19	102439	0	0	0
T20	56945	7	0	0
T21	0	775	0	0
T22	0	9	0	0
T23	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3200844	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3200844	0	0
T1	264513	373	0	0
T2	124182	0	0	0
T3	26218	58	0	0
T4	250851	10991	0	0
T5	202752	0	0	0
T6	1536	232	0	0
T17	1662	17	0	0
T18	26277	182	0	0
T19	102439	0	0	0
T20	56945	3	0	0
T21	0	775	0	0
T22	0	573	0	0
T23	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1577085	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1577085	0	0
T1	264513	2384	0	0
T2	124182	0	0	0
T3	26218	196	0	0
T4	250851	33650	0	0
T5	202752	0	0	0
T6	1536	208	0	0
T17	1662	12	0	0
T18	26277	691	0	0
T19	102439	8	0	0
T20	56945	17	0	0
T21	0	901	0	0
T22	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3113510	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3113510	0	0
T1	264513	214	0	0
T2	124182	0	0	0
T3	26218	55	0	0
T4	250851	13188	0	0
T5	202752	0	0	0
T6	1536	208	0	0
T17	1662	12	0	0
T18	26277	691	0	0
T19	102439	889	0	0
T20	56945	4	0	0
T21	0	901	0	0
T22	0	3518	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1565960	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1565960	0	0
T1	264513	1834	0	0
T2	124182	2248	0	0
T3	26218	446	0	0
T4	250851	30793	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	8	0	0
T18	26277	160	0	0
T19	102439	17	0	0
T20	56945	34	0	0
T21	0	906	0	0
T22	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	2591267	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	2591267	0	0
T1	264513	476	0	0
T2	124182	169413	0	0
T3	26218	255	0	0
T4	250851	13870	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	8	0	0
T18	26277	160	0	0
T19	102439	1537	0	0
T20	56945	6	0	0
T21	0	906	0	0
T22	0	2136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1511187	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1511187	0	0
T1	264513	1877	0	0
T2	124182	0	0	0
T3	26218	166	0	0
T4	250851	28017	0	0
T5	202752	899	0	0
T6	1536	0	0	0
T17	1662	20	0	0
T18	26277	993	0	0
T19	102439	16	0	0
T20	56945	5	0	0
T21	0	938	0	0
T22	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3419279	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3419279	0	0
T1	264513	821	0	0
T2	124182	0	0	0
T3	26218	90	0	0
T4	250851	10146	0	0
T5	202752	79005	0	0
T6	1536	0	0	0
T17	1662	20	0	0
T18	26277	993	0	0
T19	102439	1203	0	0
T20	56945	2	0	0
T21	0	938	0	0
T22	0	1190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	1589007	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	1589007	0	0
T1	264513	4250	0	0
T2	124182	0	0	0
T3	26218	223	0	0
T4	250851	30513	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	15	0	0
T18	26277	188	0	0
T19	102439	8	0	0
T20	56945	11	0	0
T21	0	1216	0	0
T22	0	19	0	0
T23	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	305268917	3213897	0	0
DepthKnown_A	305268917	305141454	0	0
RvalidKnown_A	305268917	305141454	0	0
WreadyKnown_A	305268917	305141454	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	3213897	0	0
T1	264513	1173	0	0
T2	124182	0	0	0
T3	26218	110	0	0
T4	250851	10658	0	0
T5	202752	0	0	0
T6	1536	0	0	0
T17	1662	15	0	0
T18	26277	188	0	0
T19	102439	384	0	0
T20	56945	4	0	0
T21	0	1216	0	0
T22	0	735	0	0
T23	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305268917	305141454	0	0
T1	264513	264459	0	0
T2	124182	124176	0	0
T3	26218	25525	0	0
T4	250851	250850	0	0
T5	202752	202750	0	0
T6	1536	1500	0	0
T17	1662	1635	0	0
T18	26277	26238	0	0
T19	102439	102432	0	0
T20	56945	56931	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0