Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1692014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

266212

1

T1

336

T4

602

T2

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	662202	1			T1	767		T4	1553		T2	63
values[0x0]	633406	1			T1	753		T4	1463		T2	55
values[0x1]	662618	1			T1	780		T4	1411		T2	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1310942	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

647284

1

T1

789

T4

1425

T2

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7514	1			T1	8		T4	21		T2	1
valid_sources[0x01]	7422	1			T1	11		T4	16		T3	1
valid_sources[0x02]	6779	1			T1	13		T4	9		T2	4
valid_sources[0x03]	7370	1			T1	13		T4	21		T13	1
valid_sources[0x04]	7985	1			T1	15		T4	21		T3	1
valid_sources[0x05]	7138	1			T1	12		T4	28		T3	1
valid_sources[0x06]	8387	1			T1	8		T4	13		T2	2
valid_sources[0x07]	7619	1			T1	10		T4	18		T13	1
valid_sources[0x08]	7166	1			T1	10		T4	14		T3	2
valid_sources[0x09]	7399	1			T1	7		T4	23		T14	14
valid_sources[0x0a]	8562	1			T1	9		T4	12		T13	2
valid_sources[0x0b]	7333	1			T1	9		T4	15		T13	3
valid_sources[0x0c]	8673	1			T1	13		T4	27		T14	18
valid_sources[0x0d]	7498	1			T1	6		T4	13		T3	1
valid_sources[0x0e]	7400	1			T1	6		T4	15		T2	2
valid_sources[0x0f]	6829	1			T1	11		T4	18		T13	1
valid_sources[0x10]	7657	1			T1	12		T4	22		T3	1
valid_sources[0x11]	7699	1			T1	7		T4	21		T3	1
valid_sources[0x12]	6995	1			T1	5		T4	10		T2	4
valid_sources[0x13]	6989	1			T1	12		T4	16		T3	2
valid_sources[0x14]	7635	1			T1	11		T4	19		T2	5
valid_sources[0x15]	7992	1			T1	6		T4	23		T3	1
valid_sources[0x16]	7392	1			T1	8		T4	14		T2	3
valid_sources[0x17]	7031	1			T1	10		T4	12		T3	1
valid_sources[0x18]	7868	1			T1	7		T4	24		T3	2
valid_sources[0x19]	7427	1			T1	5		T4	15		T2	1
valid_sources[0x1a]	7077	1			T1	11		T4	23		T3	1
valid_sources[0x1b]	7687	1			T1	9		T4	30		T13	2
valid_sources[0x1c]	7592	1			T1	5		T4	14		T3	2
valid_sources[0x1d]	7179	1			T1	8		T4	38		T3	1
valid_sources[0x1e]	8446	1			T1	18		T4	22		T13	2
valid_sources[0x1f]	7185	1			T1	8		T4	16		T3	1
valid_sources[0x20]	7334	1			T1	5		T4	14		T13	6
valid_sources[0x21]	7904	1			T1	8		T4	32		T2	1
valid_sources[0x22]	7949	1			T1	8		T4	22		T13	2
valid_sources[0x23]	7871	1			T1	7		T4	22		T2	5
valid_sources[0x24]	7352	1			T1	9		T4	11		T2	1
valid_sources[0x25]	7486	1			T1	7		T4	13		T13	2
valid_sources[0x26]	7070	1			T1	10		T4	18		T13	1
valid_sources[0x27]	7131	1			T1	8		T4	18		T13	2
valid_sources[0x28]	8155	1			T1	12		T4	14		T2	2
valid_sources[0x29]	8483	1			T1	5		T4	20		T3	2
valid_sources[0x2a]	7768	1			T1	8		T4	20		T13	4
valid_sources[0x2b]	6879	1			T1	10		T4	23		T3	1
valid_sources[0x2c]	7067	1			T1	11		T4	24		T13	5
valid_sources[0x2d]	7756	1			T1	11		T4	10		T3	1
valid_sources[0x2e]	7266	1			T1	12		T4	15		T13	1
valid_sources[0x2f]	7510	1			T1	11		T4	10		T3	3
valid_sources[0x30]	8232	1			T1	12		T4	17		T13	2
valid_sources[0x31]	7716	1			T1	14		T4	18		T2	4
valid_sources[0x32]	7423	1			T1	6		T4	11		T3	2
valid_sources[0x33]	6792	1			T1	5		T4	8		T3	2
valid_sources[0x34]	7311	1			T1	4		T4	21		T2	3
valid_sources[0x35]	7960	1			T1	9		T4	15		T3	2
valid_sources[0x36]	7086	1			T1	11		T4	11		T2	3
valid_sources[0x37]	7179	1			T1	9		T4	19		T3	1
valid_sources[0x38]	8326	1			T1	6		T4	18		T3	1
valid_sources[0x39]	7806	1			T1	8		T4	22		T2	3
valid_sources[0x3a]	7933	1			T1	7		T4	21		T3	1
valid_sources[0x3b]	6725	1			T1	5		T4	16		T2	2
valid_sources[0x3c]	8917	1			T1	11		T4	16		T3	1
valid_sources[0x3d]	6711	1			T1	5		T4	15		T2	3
valid_sources[0x3e]	7172	1			T1	6		T4	16		T3	1
valid_sources[0x3f]	7791	1			T1	13		T4	21		T2	1
valid_sources[0x40]	9207	1			T1	13		T4	18		T13	4
valid_sources[0x41]	6758	1			T1	13		T4	11		T2	1
valid_sources[0x42]	8527	1			T1	1		T4	10		T3	1
valid_sources[0x43]	7156	1			T1	8		T4	9		T2	2
valid_sources[0x44]	7564	1			T1	9		T4	17		T2	1
valid_sources[0x45]	8563	1			T1	9		T4	17		T13	1
valid_sources[0x46]	7530	1			T1	6		T4	13		T3	1
valid_sources[0x47]	7371	1			T1	13		T4	13		T2	5
valid_sources[0x48]	8435	1			T1	13		T4	11		T3	2
valid_sources[0x49]	8003	1			T1	7		T4	18		T3	1
valid_sources[0x4a]	9133	1			T1	8		T4	21		T3	2
valid_sources[0x4b]	8227	1			T1	8		T4	15		T2	4
valid_sources[0x4c]	7624	1			T1	8		T4	27		T13	2
valid_sources[0x4d]	8117	1			T1	6		T4	16		T3	1
valid_sources[0x4e]	8605	1			T1	14		T4	5		T2	5
valid_sources[0x4f]	8139	1			T1	10		T4	11		T13	2
valid_sources[0x50]	9108	1			T1	7		T4	12		T13	2
valid_sources[0x51]	7073	1			T1	10		T4	21		T13	2
valid_sources[0x52]	6918	1			T1	8		T4	12		T12	86
valid_sources[0x53]	7324	1			T1	8		T4	14		T13	3
valid_sources[0x54]	7545	1			T1	5		T4	7		T3	2
valid_sources[0x55]	7938	1			T1	7		T4	13		T3	2
valid_sources[0x56]	7609	1			T1	19		T4	22		T3	1
valid_sources[0x57]	7127	1			T1	11		T4	23		T13	1
valid_sources[0x58]	7591	1			T1	8		T4	18		T13	1
valid_sources[0x59]	7299	1			T1	15		T4	30		T2	5
valid_sources[0x5a]	7670	1			T1	6		T4	16		T14	16
valid_sources[0x5b]	9122	1			T1	7		T4	19		T13	1
valid_sources[0x5c]	7397	1			T1	17		T4	27		T3	1
valid_sources[0x5d]	7404	1			T1	10		T4	22		T3	2
valid_sources[0x5e]	7871	1			T1	13		T4	16		T13	2
valid_sources[0x5f]	7543	1			T1	7		T4	25		T13	3
valid_sources[0x60]	7453	1			T1	3		T4	11		T13	3
valid_sources[0x61]	7012	1			T1	8		T4	14		T3	2
valid_sources[0x62]	8142	1			T1	11		T4	20		T14	15
valid_sources[0x63]	7340	1			T1	2		T4	19		T13	4
valid_sources[0x64]	7113	1			T1	20		T4	12		T3	2
valid_sources[0x65]	7205	1			T1	7		T4	18		T3	1
valid_sources[0x66]	6535	1			T1	10		T4	24		T2	5
valid_sources[0x67]	7454	1			T1	9		T4	17		T15	2
valid_sources[0x68]	7735	1			T1	14		T4	27		T13	5
valid_sources[0x69]	7099	1			T1	4		T4	20		T13	1
valid_sources[0x6a]	8373	1			T1	20		T4	11		T13	1
valid_sources[0x6b]	6999	1			T1	9		T4	15		T2	2
valid_sources[0x6c]	8236	1			T1	11		T4	11		T3	2
valid_sources[0x6d]	7806	1			T1	5		T4	16		T3	2
valid_sources[0x6e]	7638	1			T1	9		T4	11		T3	1
valid_sources[0x6f]	7707	1			T1	9		T4	13		T2	2
valid_sources[0x70]	8593	1			T1	11		T4	15		T13	2
valid_sources[0x71]	8163	1			T1	9		T4	12		T13	2
valid_sources[0x72]	7830	1			T1	13		T4	19		T3	3
valid_sources[0x73]	8323	1			T1	6		T4	10		T3	1
valid_sources[0x74]	7164	1			T1	4		T4	24		T2	1
valid_sources[0x75]	7540	1			T1	7		T4	10		T13	3
valid_sources[0x76]	8715	1			T1	5		T4	11		T13	4
valid_sources[0x77]	7660	1			T1	19		T4	19		T13	1
valid_sources[0x78]	7150	1			T1	9		T4	22		T3	1
valid_sources[0x79]	7636	1			T1	5		T4	21		T3	1
valid_sources[0x7a]	7745	1			T1	6		T4	16		T13	4
valid_sources[0x7b]	7361	1			T1	12		T4	12		T2	1
valid_sources[0x7c]	7687	1			T1	9		T4	15		T3	2
valid_sources[0x7d]	7138	1			T1	5		T4	16		T3	2
valid_sources[0x7e]	7099	1			T1	9		T4	22		T3	2
valid_sources[0x7f]	7429	1			T1	9		T4	17		T13	2
valid_sources[0x80]	8149	1			T1	8		T4	25		T2	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28095

1

T1

39

T4

54

T2

4

values[0x0]

all_enables

biggest_size

210092

1

T1

264

T4

483

T2

16

values[0x1]

all_enables

biggest_size

28025

1

T1

33

T4

65

T2

1