Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	340609828	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	340609828	0	0
T1	2319408	33938	0	0
T2	36064	907	0	0
T3	9905504	313036	0	0
T4	264992	17708	0	0
T12	43680	844	0	0
T13	12697160	242351	0	0
T14	550424	25150	0	0
T15	10820096	252820	0	0
T16	45080	906	0	0
T17	10392928	206180	0	0
T18	0	9128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2319408	2314256	0	0
T2	36064	33712	0	0
T3	9905504	9903208	0	0
T4	264992	262920	0	0
T12	43680	40264	0	0
T13	12697160	12656056	0	0
T14	550424	548464	0	0
T15	10820096	10816512	0	0
T16	45080	41328	0	0
T17	10392928	10390968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2319408	2314256	0	0
T2	36064	33712	0	0
T3	9905504	9903208	0	0
T4	264992	262920	0	0
T12	43680	40264	0	0
T13	12697160	12656056	0	0
T14	550424	548464	0	0
T15	10820096	10816512	0	0
T16	45080	41328	0	0
T17	10392928	10390968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2319408	2314256	0	0
T2	36064	33712	0	0
T3	9905504	9903208	0	0
T4	264992	262920	0	0
T12	43680	40264	0	0
T13	12697160	12656056	0	0
T14	550424	548464	0	0
T15	10820096	10816512	0	0
T16	45080	41328	0	0
T17	10392928	10390968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	124381466	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	124381466	0	0
T1	41418	15093	0	0
T2	644	355	0	0
T3	176884	174222	0	0
T4	4732	4427	0	0
T12	780	328	0	0
T13	226735	95365	0	0
T14	9829	9202	0	0
T15	193216	116958	0	0
T16	805	351	0	0
T17	185588	91997	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	88551446	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	88551446	0	0
T1	41418	5310	0	0
T2	644	184	0	0
T3	176884	69009	0	0
T4	4732	4427	0	0
T12	780	172	0	0
T13	226735	37848	0	0
T14	9829	5568	0	0
T15	193216	43940	0	0
T16	805	185	0	0
T17	185588	34863	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1516052	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1516052	0	0
T1	41418	340	0	0
T2	644	3	0	0
T3	176884	45	0	0
T4	4732	0	0	0
T12	780	7	0	0
T13	226735	5067	0	0
T14	9829	297	0	0
T15	193216	326	0	0
T16	805	8	0	0
T17	185588	1854	0	0
T18	0	497	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3461693	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3461693	0	0
T1	41418	148	0	0
T2	644	3	0	0
T3	176884	4366	0	0
T4	4732	0	0	0
T12	780	7	0	0
T13	226735	2499	0	0
T14	9829	297	0	0
T15	193216	431	0	0
T16	805	8	0	0
T17	185588	1221	0	0
T18	0	182	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1522568	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1522568	0	0
T1	41418	270	0	0
T2	644	6	0	0
T3	176884	28	0	0
T4	4732	0	0	0
T12	780	9	0	0
T13	226735	2654	0	0
T14	9829	76	0	0
T15	193216	1704	0	0
T16	805	7	0	0
T17	185588	78	0	0
T18	0	659	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3180914	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3180914	0	0
T1	41418	115	0	0
T2	644	6	0	0
T3	176884	3118	0	0
T4	4732	0	0	0
T12	780	9	0	0
T13	226735	1959	0	0
T14	9829	76	0	0
T15	193216	3030	0	0
T16	805	7	0	0
T17	185588	294	0	0
T18	0	286	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1512379	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1512379	0	0
T1	41418	437	0	0
T2	644	8	0	0
T3	176884	39	0	0
T4	4732	0	0	0
T12	780	3	0	0
T13	226735	1116	0	0
T14	9829	349	0	0
T15	193216	1376	0	0
T16	805	1	0	0
T17	185588	1685	0	0
T18	0	520	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	2605908	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	2605908	0	0
T1	41418	159	0	0
T2	644	8	0	0
T3	176884	2038	0	0
T4	4732	0	0	0
T12	780	3	0	0
T13	226735	491	0	0
T14	9829	349	0	0
T15	193216	715	0	0
T16	805	1	0	0
T17	185588	1279	0	0
T18	0	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1503853	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1503853	0	0
T1	41418	362	0	0
T2	644	3	0	0
T3	176884	41	0	0
T4	4732	0	0	0
T12	780	6	0	0
T13	226735	3086	0	0
T14	9829	85	0	0
T15	193216	3740	0	0
T16	805	3	0	0
T17	185588	2225	0	0
T18	0	616	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3542786	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3542786	0	0
T1	41418	179	0	0
T2	644	3	0	0
T3	176884	2891	0	0
T4	4732	0	0	0
T12	780	6	0	0
T13	226735	1549	0	0
T14	9829	85	0	0
T15	193216	3354	0	0
T16	805	3	0	0
T17	185588	1692	0	0
T18	0	225	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1445609	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1445609	0	0
T1	41418	376	0	0
T2	644	5	0	0
T3	176884	20	0	0
T4	4732	0	0	0
T12	780	8	0	0
T13	226735	1233	0	0
T14	9829	84	0	0
T15	193216	2597	0	0
T16	805	9	0	0
T17	185588	309	0	0
T18	0	647	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	2792457	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	2792457	0	0
T1	41418	164	0	0
T2	644	5	0	0
T3	176884	578	0	0
T4	4732	0	0	0
T12	780	8	0	0
T13	226735	530	0	0
T14	9829	84	0	0
T15	193216	2637	0	0
T16	805	9	0	0
T17	185588	1	0	0
T18	0	273	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1428546	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1428546	0	0
T1	41418	369	0	0
T2	644	5	0	0
T3	176884	22	0	0
T4	4732	263	0	0
T12	780	5	0	0
T13	226735	2781	0	0
T14	9829	278	0	0
T15	193216	868	0	0
T16	805	8	0	0
T17	185588	1925	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	2997169	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	2997169	0	0
T1	41418	158	0	0
T2	644	5	0	0
T3	176884	1180	0	0
T4	4732	263	0	0
T12	780	5	0	0
T13	226735	1447	0	0
T14	9829	278	0	0
T15	193216	1870	0	0
T16	805	8	0	0
T17	185588	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1467132	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1467132	0	0
T1	41418	269	0	0
T2	644	12	0	0
T3	176884	54	0	0
T4	4732	254	0	0
T12	780	2	0	0
T13	226735	5386	0	0
T14	9829	278	0	0
T15	193216	1121	0	0
T16	805	5	0	0
T17	185588	300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	2897193	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	2897193	0	0
T1	41418	94	0	0
T2	644	12	0	0
T3	176884	4067	0	0
T4	4732	254	0	0
T12	780	2	0	0
T13	226735	2479	0	0
T14	9829	278	0	0
T15	193216	837	0	0
T16	805	5	0	0
T17	185588	965	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1476459	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1476459	0	0
T1	41418	315	0	0
T2	644	5	0	0
T3	176884	41	0	0
T4	4732	0	0	0
T12	780	5	0	0
T13	226735	3056	0	0
T14	9829	72	0	0
T15	193216	1510	0	0
T16	805	7	0	0
T17	185588	1891	0	0
T18	0	506	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3959060	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3959060	0	0
T1	41418	161	0	0
T2	644	5	0	0
T3	176884	2305	0	0
T4	4732	0	0	0
T12	780	5	0	0
T13	226735	1433	0	0
T14	9829	72	0	0
T15	193216	646	0	0
T16	805	7	0	0
T17	185588	1439	0	0
T18	0	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1438428	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1438428	0	0
T1	41418	367	0	0
T2	644	5	0	0
T3	176884	20	0	0
T4	4732	258	0	0
T12	780	4	0	0
T13	226735	3913	0	0
T14	9829	85	0	0
T15	193216	952	0	0
T16	805	9	0	0
T17	185588	1340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3040506	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3040506	0	0
T1	41418	207	0	0
T2	644	5	0	0
T3	176884	1018	0	0
T4	4732	258	0	0
T12	780	4	0	0
T13	226735	2802	0	0
T14	9829	85	0	0
T15	193216	654	0	0
T16	805	9	0	0
T17	185588	2459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1504942	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1504942	0	0
T1	41418	328	0	0
T2	644	10	0	0
T3	176884	14	0	0
T4	4732	0	0	0
T12	780	9	0	0
T13	226735	2589	0	0
T14	9829	298	0	0
T15	193216	2867	0	0
T16	805	4	0	0
T17	185588	738	0	0
T18	0	552	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	2989391	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	2989391	0	0
T1	41418	155	0	0
T2	644	10	0	0
T3	176884	2469	0	0
T4	4732	0	0	0
T12	780	9	0	0
T13	226735	1649	0	0
T14	9829	298	0	0
T15	193216	1411	0	0
T16	805	4	0	0
T17	185588	366	0	0
T18	0	216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1518653	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1518653	0	0
T1	41418	307	0	0
T2	644	8	0	0
T3	176884	8	0	0
T4	4732	216	0	0
T12	780	5	0	0
T13	226735	1040	0	0
T14	9829	301	0	0
T15	193216	3145	0	0
T16	805	7	0	0
T17	185588	2829	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3176824	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3176824	0	0
T1	41418	89	0	0
T2	644	8	0	0
T3	176884	1058	0	0
T4	4732	216	0	0
T12	780	5	0	0
T13	226735	585	0	0
T14	9829	301	0	0
T15	193216	2542	0	0
T16	805	7	0	0
T17	185588	1747	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1457376	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1457376	0	0
T1	41418	331	0	0
T2	644	4	0	0
T3	176884	20	0	0
T4	4732	205	0	0
T12	780	7	0	0
T13	226735	1107	0	0
T14	9829	73	0	0
T15	193216	1230	0	0
T16	805	3	0	0
T17	185588	2693	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3446843	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3446843	0	0
T1	41418	177	0	0
T2	644	4	0	0
T3	176884	1177	0	0
T4	4732	205	0	0
T12	780	7	0	0
T13	226735	619	0	0
T14	9829	73	0	0
T15	193216	706	0	0
T16	805	3	0	0
T17	185588	3106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1511812	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1511812	0	0
T1	41418	215	0	0
T2	644	7	0	0
T3	176884	30	0	0
T4	4732	203	0	0
T12	780	7	0	0
T13	226735	1197	0	0
T14	9829	92	0	0
T15	193216	1845	0	0
T16	805	10	0	0
T17	185588	1592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3351196	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3351196	0	0
T1	41418	94	0	0
T2	644	7	0	0
T3	176884	1622	0	0
T4	4732	203	0	0
T12	780	7	0	0
T13	226735	677	0	0
T14	9829	92	0	0
T15	193216	1658	0	0
T16	805	10	0	0
T17	185588	610	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1461626	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1461626	0	0
T1	41418	268	0	0
T2	644	3	0	0
T3	176884	67	0	0
T4	4732	231	0	0
T12	780	10	0	0
T13	226735	5179	0	0
T14	9829	70	0	0
T15	193216	431	0	0
T16	805	5	0	0
T17	185588	1767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3235694	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3235694	0	0
T1	41418	151	0	0
T2	644	3	0	0
T3	176884	5746	0	0
T4	4732	231	0	0
T12	780	10	0	0
T13	226735	2483	0	0
T14	9829	70	0	0
T15	193216	362	0	0
T16	805	5	0	0
T17	185588	1700	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1506822	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1506822	0	0
T1	41418	474	0	0
T2	644	6	0	0
T3	176884	23	0	0
T4	4732	528	0	0
T12	780	9	0	0
T13	226735	2025	0	0
T14	9829	80	0	0
T15	193216	2489	0	0
T16	805	10	0	0
T17	185588	2166	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3631313	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3631313	0	0
T1	41418	180	0	0
T2	644	6	0	0
T3	176884	1822	0	0
T4	4732	528	0	0
T12	780	9	0	0
T13	226735	1026	0	0
T14	9829	80	0	0
T15	193216	1975	0	0
T16	805	10	0	0
T17	185588	1924	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1474129	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1474129	0	0
T1	41418	473	0	0
T2	644	12	0	0
T3	176884	22	0	0
T4	4732	0	0	0
T12	780	9	0	0
T13	226735	3330	0	0
T14	9829	75	0	0
T15	193216	1372	0	0
T16	805	4	0	0
T17	185588	2138	0	0
T18	0	457	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3294162	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3294162	0	0
T1	41418	200	0	0
T2	644	12	0	0
T3	176884	1843	0	0
T4	4732	0	0	0
T12	780	9	0	0
T13	226735	1513	0	0
T14	9829	75	0	0
T15	193216	570	0	0
T16	805	4	0	0
T17	185588	1917	0	0
T18	0	234	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1514934	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1514934	0	0
T1	41418	336	0	0
T2	644	8	0	0
T3	176884	47	0	0
T4	4732	0	0	0
T12	780	11	0	0
T13	226735	3616	0	0
T14	9829	56	0	0
T15	193216	1607	0	0
T16	805	8	0	0
T17	185588	1432	0	0
T18	0	483	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	2935802	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	2935802	0	0
T1	41418	137	0	0
T2	644	8	0	0
T3	176884	5845	0	0
T4	4732	0	0	0
T12	780	11	0	0
T13	226735	1771	0	0
T14	9829	56	0	0
T15	193216	1193	0	0
T16	805	8	0	0
T17	185588	1019	0	0
T18	0	184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1480646	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1480646	0	0
T1	41418	384	0	0
T2	644	6	0	0
T3	176884	5	0	0
T4	4732	243	0	0
T12	780	7	0	0
T13	226735	1203	0	0
T14	9829	86	0	0
T15	193216	881	0	0
T16	805	6	0	0
T17	185588	2080	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3256719	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3256719	0	0
T1	41418	178	0	0
T2	644	6	0	0
T3	176884	1138	0	0
T4	4732	243	0	0
T12	780	7	0	0
T13	226735	597	0	0
T14	9829	86	0	0
T15	193216	611	0	0
T16	805	6	0	0
T17	185588	1489	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1466700	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1466700	0	0
T1	41418	376	0	0
T2	644	8	0	0
T3	176884	31	0	0
T4	4732	220	0	0
T12	780	6	0	0
T13	226735	4931	0	0
T14	9829	71	0	0
T15	193216	668	0	0
T16	805	6	0	0
T17	185588	1702	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3581127	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3581127	0	0
T1	41418	153	0	0
T2	644	8	0	0
T3	176884	3730	0	0
T4	4732	220	0	0
T12	780	6	0	0
T13	226735	2385	0	0
T14	9829	71	0	0
T15	193216	1046	0	0
T16	805	6	0	0
T17	185588	1381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1446886	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1446886	0	0
T1	41418	350	0	0
T2	644	9	0	0
T3	176884	9	0	0
T4	4732	268	0	0
T12	780	4	0	0
T13	226735	1079	0	0
T14	9829	644	0	0
T15	193216	2468	0	0
T16	805	6	0	0
T17	185588	5112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	2864012	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	2864012	0	0
T1	41418	154	0	0
T2	644	9	0	0
T3	176884	1279	0	0
T4	4732	268	0	0
T12	780	4	0	0
T13	226735	615	0	0
T14	9829	644	0	0
T15	193216	3076	0	0
T16	805	6	0	0
T17	185588	1768	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1481264	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1481264	0	0
T1	41418	411	0	0
T2	644	9	0	0
T3	176884	21	0	0
T4	4732	292	0	0
T12	780	4	0	0
T13	226735	1010	0	0
T14	9829	65	0	0
T15	193216	2340	0	0
T16	805	11	0	0
T17	185588	1924	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	2902179	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	2902179	0	0
T1	41418	229	0	0
T2	644	9	0	0
T3	176884	1262	0	0
T4	4732	292	0	0
T12	780	4	0	0
T13	226735	503	0	0
T14	9829	65	0	0
T15	193216	3159	0	0
T16	805	11	0	0
T17	185588	2382	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1496113	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1496113	0	0
T1	41418	354	0	0
T2	644	5	0	0
T3	176884	25	0	0
T4	4732	216	0	0
T12	780	4	0	0
T13	226735	7573	0	0
T14	9829	71	0	0
T15	193216	1097	0	0
T16	805	5	0	0
T17	185588	1849	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	2583607	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	2583607	0	0
T1	41418	158	0	0
T2	644	5	0	0
T3	176884	3061	0	0
T4	4732	216	0	0
T12	780	4	0	0
T13	226735	3928	0	0
T14	9829	71	0	0
T15	193216	988	0	0
T16	805	5	0	0
T17	185588	1421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1508328	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1508328	0	0
T1	41418	375	0	0
T2	644	5	0	0
T3	176884	31	0	0
T4	4732	0	0	0
T12	780	3	0	0
T13	226735	1166	0	0
T14	9829	86	0	0
T15	193216	3313	0	0
T16	805	13	0	0
T17	185588	586	0	0
T18	0	424	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3977294	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3977294	0	0
T1	41418	154	0	0
T2	644	5	0	0
T3	176884	4112	0	0
T4	4732	0	0	0
T12	780	3	0	0
T13	226735	576	0	0
T14	9829	86	0	0
T15	193216	3300	0	0
T16	805	13	0	0
T17	185588	1047	0	0
T18	0	213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1455106	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1455106	0	0
T1	41418	288	0	0
T2	644	4	0	0
T3	176884	26	0	0
T4	4732	0	0	0
T12	780	8	0	0
T13	226735	1002	0	0
T14	9829	295	0	0
T15	193216	1478	0	0
T16	805	15	0	0
T17	185588	383	0	0
T18	0	541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3348076	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3348076	0	0
T1	41418	115	0	0
T2	644	4	0	0
T3	176884	1885	0	0
T4	4732	0	0	0
T12	780	8	0	0
T13	226735	562	0	0
T14	9829	295	0	0
T15	193216	2561	0	0
T16	805	15	0	0
T17	185588	996	0	0
T18	0	225	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1460179	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1460179	0	0
T1	41418	385	0	0
T2	644	9	0	0
T3	176884	35	0	0
T4	4732	0	0	0
T12	780	9	0	0
T13	226735	2181	0	0
T14	9829	357	0	0
T15	193216	2919	0	0
T16	805	7	0	0
T17	185588	1508	0	0
T18	0	558	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3575681	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3575681	0	0
T1	41418	171	0	0
T2	644	9	0	0
T3	176884	2999	0	0
T4	4732	0	0	0
T12	780	9	0	0
T13	226735	1534	0	0
T14	9829	357	0	0
T15	193216	2187	0	0
T16	805	7	0	0
T17	185588	928	0	0
T18	0	189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1494782	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1494782	0	0
T1	41418	297	0	0
T2	644	13	0	0
T3	176884	37	0	0
T4	4732	559	0	0
T12	780	4	0	0
T13	226735	1219	0	0
T14	9829	562	0	0
T15	193216	1512	0	0
T16	805	3	0	0
T17	185588	1604	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3349500	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3349500	0	0
T1	41418	207	0	0
T2	644	13	0	0
T3	176884	3193	0	0
T4	4732	559	0	0
T12	780	4	0	0
T13	226735	606	0	0
T14	9829	562	0	0
T15	193216	304	0	0
T16	805	3	0	0
T17	185588	363	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	1491520	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	1491520	0	0
T1	41418	283	0	0
T2	644	6	0	0
T3	176884	35	0	0
T4	4732	471	0	0
T12	780	7	0	0
T13	226735	1696	0	0
T14	9829	304	0	0
T15	193216	2126	0	0
T16	805	5	0	0
T17	185588	747	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315484699	3656966	0	0
DepthKnown_A	315484699	315352183	0	0
RvalidKnown_A	315484699	315352183	0	0
WreadyKnown_A	315484699	315352183	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	3656966	0	0
T1	41418	108	0	0
T2	644	6	0	0
T3	176884	3207	0	0
T4	4732	471	0	0
T12	780	7	0	0
T13	226735	885	0	0
T14	9829	304	0	0
T15	193216	2117	0	0
T16	805	5	0	0
T17	185588	1136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315484699	315352183	0	0
T1	41418	41326	0	0
T2	644	602	0	0
T3	176884	176843	0	0
T4	4732	4695	0	0
T12	780	719	0	0
T13	226735	226001	0	0
T14	9829	9794	0	0
T15	193216	193152	0	0
T16	805	738	0	0
T17	185588	185553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0