Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1670759	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262470

1

T1

44

T2

165

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	653327	1			T1	166		T2	404		T3	38
values[0x0]	625779	1			T1	22		T2	415		T3	47
values[0x1]	654123	1			T1	149		T2	397		T3	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1295775	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

637454

1

T1

129

T2

406

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7411	1			T1	3		T2	3		T18	6
valid_sources[0x01]	7064	1			T2	2		T18	14		T5	2
valid_sources[0x02]	8815	1			T2	2		T18	20		T5	2
valid_sources[0x03]	7073	1			T1	1		T2	3		T18	19
valid_sources[0x04]	7184	1			T1	1		T2	9		T18	16
valid_sources[0x05]	7318	1			T2	3		T18	8		T4	2
valid_sources[0x06]	9050	1			T1	1		T2	5		T18	32
valid_sources[0x07]	7668	1			T1	1		T2	5		T18	7
valid_sources[0x08]	7635	1			T1	1		T2	2		T18	15
valid_sources[0x09]	7189	1			T1	1		T2	1		T18	4
valid_sources[0x0a]	7213	1			T1	3		T2	7		T18	33
valid_sources[0x0b]	7151	1			T1	1		T2	4		T18	21
valid_sources[0x0c]	6513	1			T1	1		T2	4		T18	29
valid_sources[0x0d]	7281	1			T1	3		T2	1		T18	41
valid_sources[0x0e]	8488	1			T1	4		T2	4		T18	15
valid_sources[0x0f]	7516	1			T1	1		T2	6		T18	24
valid_sources[0x10]	7884	1			T2	5		T18	21		T4	2
valid_sources[0x11]	7480	1			T1	1		T2	5		T18	32
valid_sources[0x12]	7228	1			T2	4		T18	5		T4	2
valid_sources[0x13]	7439	1			T1	2		T2	3		T18	11
valid_sources[0x14]	7081	1			T1	1		T2	5		T18	16
valid_sources[0x15]	9337	1			T1	1		T2	4		T18	19
valid_sources[0x16]	7404	1			T2	1		T18	34		T4	4
valid_sources[0x17]	8336	1			T1	3		T2	2		T18	20
valid_sources[0x18]	7501	1			T1	2		T2	9		T18	35
valid_sources[0x19]	8583	1			T1	1		T2	5		T18	19
valid_sources[0x1a]	6961	1			T1	3		T2	2		T18	21
valid_sources[0x1b]	6319	1			T1	1		T2	5		T18	7
valid_sources[0x1c]	7224	1			T1	2		T2	3		T18	31
valid_sources[0x1d]	7441	1			T1	2		T2	3		T18	21
valid_sources[0x1e]	7549	1			T1	1		T2	5		T18	6
valid_sources[0x1f]	7713	1			T2	4		T18	24		T4	1
valid_sources[0x20]	9404	1			T1	2		T2	3		T18	17
valid_sources[0x21]	7046	1			T1	1		T2	4		T18	13
valid_sources[0x22]	7991	1			T1	1		T2	5		T18	20
valid_sources[0x23]	8179	1			T2	3		T18	9		T5	2
valid_sources[0x24]	7186	1			T1	1		T2	7		T18	29
valid_sources[0x25]	7542	1			T2	5		T18	17		T4	1
valid_sources[0x26]	7668	1			T2	7		T18	44		T4	1
valid_sources[0x27]	6977	1			T1	1		T2	4		T18	5
valid_sources[0x28]	7406	1			T1	2		T2	4		T18	8
valid_sources[0x29]	7536	1			T1	2		T2	4		T18	30
valid_sources[0x2a]	6647	1			T1	1		T2	9		T18	25
valid_sources[0x2b]	7434	1			T1	1		T2	4		T18	15
valid_sources[0x2c]	10055	1			T2	3		T18	12		T4	3
valid_sources[0x2d]	7544	1			T1	1		T2	11		T18	17
valid_sources[0x2e]	8041	1			T1	2		T2	6		T18	28
valid_sources[0x2f]	7649	1			T1	2		T2	6		T18	16
valid_sources[0x30]	6609	1			T1	3		T2	8		T18	3
valid_sources[0x31]	8905	1			T2	5		T18	12		T4	4
valid_sources[0x32]	7504	1			T2	10		T18	20		T4	1
valid_sources[0x33]	7064	1			T1	1		T2	5		T18	12
valid_sources[0x34]	7780	1			T1	1		T2	2		T18	12
valid_sources[0x35]	7818	1			T1	1		T2	3		T18	9
valid_sources[0x36]	7890	1			T1	2		T2	8		T18	18
valid_sources[0x37]	8547	1			T1	1		T2	7		T18	10
valid_sources[0x38]	7695	1			T1	1		T2	6		T18	21
valid_sources[0x39]	8566	1			T1	1		T2	8		T18	24
valid_sources[0x3a]	7250	1			T2	4		T18	23		T4	2
valid_sources[0x3b]	7547	1			T1	1		T2	6		T18	19
valid_sources[0x3c]	6927	1			T1	2		T2	5		T18	5
valid_sources[0x3d]	7219	1			T2	4		T18	15		T4	4
valid_sources[0x3e]	6886	1			T1	1		T2	9		T18	29
valid_sources[0x3f]	7353	1			T1	1		T2	2		T18	7
valid_sources[0x40]	7289	1			T1	1		T2	7		T18	16
valid_sources[0x41]	7651	1			T2	5		T18	7		T4	2
valid_sources[0x42]	8313	1			T1	1		T2	4		T18	8
valid_sources[0x43]	7364	1			T1	2		T2	3		T3	65
valid_sources[0x44]	7757	1			T1	1		T2	4		T18	20
valid_sources[0x45]	7809	1			T1	1		T2	4		T18	16
valid_sources[0x46]	7915	1			T1	2		T2	3		T18	20
valid_sources[0x47]	7661	1			T1	3		T2	6		T18	22
valid_sources[0x48]	7043	1			T2	7		T18	18		T4	1
valid_sources[0x49]	8375	1			T1	2		T2	3		T18	31
valid_sources[0x4a]	7224	1			T1	1		T2	7		T18	16
valid_sources[0x4b]	8258	1			T2	10		T18	17		T4	5
valid_sources[0x4c]	8062	1			T18	12		T5	2		T19	3
valid_sources[0x4d]	8725	1			T1	1		T2	4		T18	21
valid_sources[0x4e]	6936	1			T2	5		T18	9		T4	1
valid_sources[0x4f]	8468	1			T1	1		T2	10		T18	11
valid_sources[0x50]	8835	1			T1	1		T2	5		T18	12
valid_sources[0x51]	8558	1			T2	7		T18	13		T4	1
valid_sources[0x52]	7690	1			T2	6		T18	3		T4	2
valid_sources[0x53]	7013	1			T2	4		T18	18		T4	2
valid_sources[0x54]	7548	1			T18	15		T4	2		T5	2
valid_sources[0x55]	7150	1			T1	1		T2	6		T18	14
valid_sources[0x56]	7397	1			T1	1		T2	1		T18	9
valid_sources[0x57]	7812	1			T1	1		T2	7		T18	13
valid_sources[0x58]	7164	1			T1	1		T2	2		T18	6
valid_sources[0x59]	7269	1			T2	8		T18	10		T5	2
valid_sources[0x5a]	7253	1			T2	5		T18	12		T5	2
valid_sources[0x5b]	7486	1			T1	1		T2	2		T18	13
valid_sources[0x5c]	7176	1			T1	1		T2	3		T18	29
valid_sources[0x5d]	6892	1			T1	2		T2	2		T18	19
valid_sources[0x5e]	7606	1			T1	3		T2	6		T18	5
valid_sources[0x5f]	7458	1			T1	1		T2	3		T18	24
valid_sources[0x60]	6875	1			T1	2		T2	7		T18	15
valid_sources[0x61]	7815	1			T1	1		T2	5		T18	18
valid_sources[0x62]	8776	1			T1	3		T2	6		T18	13
valid_sources[0x63]	7460	1			T1	2		T2	5		T18	13
valid_sources[0x64]	7661	1			T1	1		T2	2		T18	14
valid_sources[0x65]	7333	1			T1	2		T2	2		T18	29
valid_sources[0x66]	7493	1			T1	1		T2	6		T18	7
valid_sources[0x67]	7591	1			T1	3		T2	7		T18	20
valid_sources[0x68]	7560	1			T1	3		T2	5		T18	28
valid_sources[0x69]	7859	1			T1	1		T2	3		T18	29
valid_sources[0x6a]	7406	1			T2	8		T18	35		T4	3
valid_sources[0x6b]	7820	1			T2	5		T18	10		T4	3
valid_sources[0x6c]	8811	1			T1	1		T2	3		T18	20
valid_sources[0x6d]	7062	1			T1	6		T2	3		T18	11
valid_sources[0x6e]	7686	1			T1	3		T2	9		T18	6
valid_sources[0x6f]	8348	1			T1	1		T2	5		T18	12
valid_sources[0x70]	7560	1			T1	2		T2	9		T18	18
valid_sources[0x71]	7094	1			T1	2		T2	6		T18	10
valid_sources[0x72]	7497	1			T2	7		T18	23		T4	2
valid_sources[0x73]	7374	1			T2	7		T18	13		T5	2
valid_sources[0x74]	6848	1			T1	1		T2	16		T18	19
valid_sources[0x75]	7156	1			T1	1		T2	2		T18	16
valid_sources[0x76]	7471	1			T1	3		T2	3		T18	7
valid_sources[0x77]	7693	1			T1	1		T2	1		T18	10
valid_sources[0x78]	7044	1			T1	2		T2	2		T18	11
valid_sources[0x79]	7712	1			T2	6		T18	20		T5	1
valid_sources[0x7a]	7544	1			T1	2		T2	7		T18	27
valid_sources[0x7b]	7210	1			T1	2		T2	5		T18	13
valid_sources[0x7c]	7404	1			T1	1		T2	8		T18	24
valid_sources[0x7d]	7235	1			T1	1		T2	4		T18	8
valid_sources[0x7e]	7138	1			T1	1		T2	4		T18	29
valid_sources[0x7f]	8011	1			T1	1		T2	5		T18	11
valid_sources[0x80]	8565	1			T2	5		T18	17		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27497

1

T1

22

T2

20

T3

1

values[0x0]

all_enables

biggest_size

207559

1

T1

7

T2

134

T3

12

values[0x1]

all_enables

biggest_size

27414

1

T1

15

T2

11

T3

1