Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	325812723	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	325812723	0	0
T1	803544	34814	0	0
T2	155120	5969	0	0
T3	35560	634	0	0
T4	13228264	362530	0	0
T5	24293584	366510	0	0
T6	35168	918	0	0
T16	7131096	133898	0	0
T17	0	1716	0	0
T18	265272	16771	0	0
T19	3907064	107287	0	0
T20	11059440	1896936	0	0
T21	0	3046	0	0
T22	0	291366	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	803544	800856	0	0
T2	155120	152264	0	0
T3	35560	32760	0	0
T4	13228264	13165152	0	0
T5	24293584	24291288	0	0
T6	35168	33096	0	0
T16	7131096	7129136	0	0
T18	265272	261856	0	0
T19	3907064	3903592	0	0
T20	11059440	11059384	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	803544	800856	0	0
T2	155120	152264	0	0
T3	35560	32760	0	0
T4	13228264	13165152	0	0
T5	24293584	24291288	0	0
T6	35168	33096	0	0
T16	7131096	7129136	0	0
T18	265272	261856	0	0
T19	3907064	3903592	0	0
T20	11059440	11059384	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	803544	800856	0	0
T2	155120	152264	0	0
T3	35560	32760	0	0
T4	13228264	13165152	0	0
T5	24293584	24291288	0	0
T6	35168	33096	0	0
T16	7131096	7129136	0	0
T18	265272	261856	0	0
T19	3907064	3903592	0	0
T20	11059440	11059384	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T16	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	115662314	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	115662314	0	0
T1	14349	14132	0	0
T2	2770	2323	0	0
T3	635	244	0	0
T4	236219	119082	0	0
T5	433814	2475	0	0
T6	628	357	0	0
T16	127341	62072	0	0
T18	4737	4194	0	0
T19	69769	24671	0	0
T20	197490	852220	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	86522664	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	86522664	0	0
T1	14349	7422	0	0
T2	2770	1216	0	0
T3	635	130	0	0
T4	236219	84687	0	0
T5	433814	180780	0	0
T6	628	187	0	0
T16	127341	15664	0	0
T18	4737	4193	0	0
T19	69769	28983	0	0
T20	197490	225438	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1423678	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1423678	0	0
T1	14349	592	0	0
T2	2770	58	0	0
T3	635	4	0	0
T4	236219	679	0	0
T5	433814	0	0	0
T6	628	3	0	0
T16	127341	3223	0	0
T17	0	17	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	26374	0	0
T21	0	59	0	0
T22	0	22062	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3542615	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3542615	0	0
T1	14349	592	0	0
T2	2770	58	0	0
T3	635	4	0	0
T4	236219	765	0	0
T5	433814	0	0	0
T6	628	3	0	0
T16	127341	1732	0	0
T17	0	29	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	8609	0	0
T21	0	59	0	0
T22	0	7930	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1389233	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1389233	0	0
T1	14349	147	0	0
T2	2770	45	0	0
T3	635	5	0	0
T4	236219	5598	0	0
T5	433814	1139	0	0
T6	628	9	0	0
T16	127341	66	0	0
T17	0	13	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	16941	0	0
T21	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	2863960	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	2863960	0	0
T1	14349	147	0	0
T2	2770	45	0	0
T3	635	5	0	0
T4	236219	5493	0	0
T5	433814	81734	0	0
T6	628	9	0	0
T16	127341	395	0	0
T17	0	24	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	6911	0	0
T21	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1379722	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1379722	0	0
T1	14349	438	0	0
T2	2770	34	0	0
T3	635	2	0	0
T4	236219	5795	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	2837	0	0
T17	0	24	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	22170	0	0
T21	0	64	0	0
T22	0	21056	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3699224	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3699224	0	0
T1	14349	438	0	0
T2	2770	34	0	0
T3	635	2	0	0
T4	236219	5982	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	955	0	0
T17	0	29	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	7415	0	0
T21	0	64	0	0
T22	0	6246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1399464	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1399464	0	0
T1	14349	159	0	0
T2	2770	51	0	0
T3	635	6	0	0
T4	236219	922	0	0
T5	433814	0	0	0
T6	628	4	0	0
T16	127341	140	0	0
T17	0	48	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	20264	0	0
T21	0	58	0	0
T22	0	23885	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3135701	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3135701	0	0
T1	14349	159	0	0
T2	2770	51	0	0
T3	635	6	0	0
T4	236219	862	0	0
T5	433814	0	0	0
T6	628	4	0	0
T16	127341	1	0	0
T17	0	64	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	6234	0	0
T21	0	58	0	0
T22	0	6617	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1382612	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1382612	0	0
T1	14349	370	0	0
T2	2770	44	0	0
T3	635	3	0	0
T4	236219	2693	0	0
T5	433814	0	0	0
T6	628	7	0	0
T16	127341	762	0	0
T17	0	14	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	15001	0	0
T21	0	82	0	0
T22	0	20515	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3041540	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3041540	0	0
T1	14349	370	0	0
T2	2770	44	0	0
T3	635	3	0	0
T4	236219	2937	0	0
T5	433814	0	0	0
T6	628	7	0	0
T16	127341	64	0	0
T17	0	32	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	9122	0	0
T21	0	82	0	0
T22	0	8396	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1393111	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1393111	0	0
T1	14349	142	0	0
T2	2770	53	0	0
T3	635	6	0	0
T4	236219	5247	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	301	0	0
T18	4737	579	0	0
T19	69769	1109	0	0
T20	197490	26457	0	0
T21	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3791340	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3791340	0	0
T1	14349	142	0	0
T2	2770	53	0	0
T3	635	6	0	0
T4	236219	4914	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	645	0	0
T18	4737	579	0	0
T19	69769	1855	0	0
T20	197490	5185	0	0
T21	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1392667	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1392667	0	0
T1	14349	436	0	0
T2	2770	43	0	0
T3	635	3	0	0
T4	236219	839	0	0
T5	433814	0	0	0
T6	628	5	0	0
T16	127341	1286	0	0
T17	0	15	0	0
T18	4737	0	0	0
T19	69769	2185	0	0
T20	197490	17826	0	0
T21	0	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3198806	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3198806	0	0
T1	14349	436	0	0
T2	2770	43	0	0
T3	635	3	0	0
T4	236219	889	0	0
T5	433814	0	0	0
T6	628	5	0	0
T16	127341	524	0	0
T17	0	18	0	0
T18	4737	0	0	0
T19	69769	2123	0	0
T20	197490	8814	0	0
T21	0	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1387831	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1387831	0	0
T1	14349	155	0	0
T2	2770	52	0	0
T3	635	1	0	0
T4	236219	2747	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	1048	0	0
T18	4737	0	0	0
T19	69769	1731	0	0
T20	197490	19688	0	0
T21	0	61	0	0
T22	0	17278	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3130566	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3130566	0	0
T1	14349	155	0	0
T2	2770	52	0	0
T3	635	1	0	0
T4	236219	2671	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	515	0	0
T18	4737	0	0	0
T19	69769	2221	0	0
T20	197490	9436	0	0
T21	0	61	0	0
T22	0	5982	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1367671	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1367671	0	0
T1	14349	135	0	0
T2	2770	38	0	0
T3	635	9	0	0
T4	236219	755	0	0
T5	433814	0	0	0
T6	628	5	0	0
T16	127341	926	0	0
T17	0	22	0	0
T18	4737	230	0	0
T19	69769	0	0	0
T20	197490	22821	0	0
T21	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3199393	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3199393	0	0
T1	14349	135	0	0
T2	2770	38	0	0
T3	635	9	0	0
T4	236219	852	0	0
T5	433814	0	0	0
T6	628	5	0	0
T16	127341	774	0	0
T17	0	9	0	0
T18	4737	230	0	0
T19	69769	0	0	0
T20	197490	9567	0	0
T21	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1467554	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1467554	0	0
T1	14349	167	0	0
T2	2770	47	0	0
T3	635	3	0	0
T4	236219	2935	0	0
T5	433814	0	0	0
T6	628	4	0	0
T16	127341	715	0	0
T17	0	47	0	0
T18	4737	260	0	0
T19	69769	0	0	0
T20	197490	26345	0	0
T21	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3263943	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3263943	0	0
T1	14349	167	0	0
T2	2770	47	0	0
T3	635	3	0	0
T4	236219	3124	0	0
T5	433814	0	0	0
T6	628	4	0	0
T16	127341	3	0	0
T17	0	24	0	0
T18	4737	260	0	0
T19	69769	0	0	0
T20	197490	5323	0	0
T21	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1395383	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1395383	0	0
T1	14349	153	0	0
T2	2770	40	0	0
T3	635	3	0	0
T4	236219	651	0	0
T5	433814	0	0	0
T6	628	8	0	0
T16	127341	1420	0	0
T17	0	8	0	0
T18	4737	731	0	0
T19	69769	4315	0	0
T20	197490	14812	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3296340	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3296340	0	0
T1	14349	153	0	0
T2	2770	40	0	0
T3	635	3	0	0
T4	236219	815	0	0
T5	433814	0	0	0
T6	628	8	0	0
T16	127341	429	0	0
T17	0	21	0	0
T18	4737	731	0	0
T19	69769	4682	0	0
T20	197490	7885	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1439101	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1439101	0	0
T1	14349	137	0	0
T2	2770	52	0	0
T3	635	4	0	0
T4	236219	3401	0	0
T5	433814	0	0	0
T6	628	5	0	0
T16	127341	239	0	0
T17	0	1	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	21036	0	0
T21	0	81	0	0
T22	0	16614	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3058285	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3058285	0	0
T1	14349	137	0	0
T2	2770	52	0	0
T3	635	4	0	0
T4	236219	3463	0	0
T5	433814	0	0	0
T6	628	5	0	0
T16	127341	85	0	0
T17	0	3	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	8239	0	0
T21	0	81	0	0
T22	0	5992	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1392876	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1392876	0	0
T1	14349	146	0	0
T2	2770	49	0	0
T3	635	4	0	0
T4	236219	804	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	1909	0	0
T17	0	46	0	0
T18	4737	0	0	0
T19	69769	4540	0	0
T20	197490	27726	0	0
T21	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3102563	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3102563	0	0
T1	14349	146	0	0
T2	2770	49	0	0
T3	635	4	0	0
T4	236219	813	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	349	0	0
T17	0	45	0	0
T18	4737	0	0	0
T19	69769	4568	0	0
T20	197490	9547	0	0
T21	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1408106	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1408106	0	0
T1	14349	129	0	0
T2	2770	43	0	0
T3	635	2	0	0
T4	236219	862	0	0
T5	433814	0	0	0
T6	628	5	0	0
T16	127341	1851	0	0
T17	0	74	0	0
T18	4737	269	0	0
T19	69769	1685	0	0
T20	197490	21548	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3428656	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3428656	0	0
T1	14349	129	0	0
T2	2770	43	0	0
T3	635	2	0	0
T4	236219	853	0	0
T5	433814	0	0	0
T6	628	5	0	0
T16	127341	659	0	0
T17	0	63	0	0
T18	4737	269	0	0
T19	69769	2499	0	0
T20	197490	7445	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1375690	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1375690	0	0
T1	14349	137	0	0
T2	2770	38	0	0
T3	635	1	0	0
T4	236219	779	0	0
T5	433814	0	0	0
T6	628	14	0	0
T16	127341	993	0	0
T17	0	191	0	0
T18	4737	250	0	0
T19	69769	0	0	0
T20	197490	23797	0	0
T21	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3570002	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3570002	0	0
T1	14349	137	0	0
T2	2770	38	0	0
T3	635	1	0	0
T4	236219	705	0	0
T5	433814	0	0	0
T6	628	14	0	0
T16	127341	940	0	0
T17	0	230	0	0
T18	4737	250	0	0
T19	69769	0	0	0
T20	197490	9916	0	0
T21	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1383902	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1383902	0	0
T1	14349	373	0	0
T2	2770	44	0	0
T3	635	5	0	0
T4	236219	1055	0	0
T5	433814	0	0	0
T6	628	10	0	0
T16	127341	1141	0	0
T17	0	37	0	0
T18	4737	215	0	0
T19	69769	985	0	0
T20	197490	17065	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	2944273	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	2944273	0	0
T1	14349	373	0	0
T2	2770	44	0	0
T3	635	5	0	0
T4	236219	924	0	0
T5	433814	0	0	0
T6	628	10	0	0
T16	127341	812	0	0
T17	0	33	0	0
T18	4737	215	0	0
T19	69769	1515	0	0
T20	197490	7743	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1455095	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1455095	0	0
T1	14349	131	0	0
T2	2770	44	0	0
T3	635	13	0	0
T4	236219	7078	0	0
T5	433814	0	0	0
T6	628	13	0	0
T16	127341	2950	0	0
T17	0	58	0	0
T18	4737	286	0	0
T19	69769	0	0	0
T20	197490	24525	0	0
T21	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3333410	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3333410	0	0
T1	14349	131	0	0
T2	2770	44	0	0
T3	635	13	0	0
T4	236219	6727	0	0
T5	433814	0	0	0
T6	628	13	0	0
T16	127341	766	0	0
T17	0	29	0	0
T18	4737	286	0	0
T19	69769	0	0	0
T20	197490	9359	0	0
T21	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1423842	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1423842	0	0
T1	14349	134	0	0
T2	2770	50	0	0
T3	635	1	0	0
T4	236219	786	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	2931	0	0
T17	0	34	0	0
T18	4737	225	0	0
T19	69769	0	0	0
T20	197490	28592	0	0
T21	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3219123	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3219123	0	0
T1	14349	134	0	0
T2	2770	50	0	0
T3	635	1	0	0
T4	236219	874	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	256	0	0
T17	0	28	0	0
T18	4737	225	0	0
T19	69769	0	0	0
T20	197490	10928	0	0
T21	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1439472	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1439472	0	0
T1	14349	351	0	0
T2	2770	29	0	0
T3	635	7	0	0
T4	236219	4881	0	0
T5	433814	0	0	0
T6	628	7	0	0
T16	127341	688	0	0
T17	0	14	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	17450	0	0
T21	0	73	0	0
T22	0	31115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	2889633	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	2889633	0	0
T1	14349	351	0	0
T2	2770	29	0	0
T3	635	7	0	0
T4	236219	5064	0	0
T5	433814	0	0	0
T6	628	7	0	0
T16	127341	546	0	0
T17	0	27	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	8303	0	0
T21	0	73	0	0
T22	0	14057	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1426161	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1426161	0	0
T1	14349	685	0	0
T2	2770	44	0	0
T3	635	7	0	0
T4	236219	3331	0	0
T5	433814	1336	0	0
T6	628	8	0	0
T16	127341	2238	0	0
T18	4737	224	0	0
T19	69769	2331	0	0
T20	197490	22140	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	2909787	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	2909787	0	0
T1	14349	685	0	0
T2	2770	44	0	0
T3	635	7	0	0
T4	236219	3436	0	0
T5	433814	99046	0	0
T6	628	8	0	0
T16	127341	1137	0	0
T18	4737	224	0	0
T19	69769	2559	0	0
T20	197490	8574	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1403324	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1403324	0	0
T1	14349	417	0	0
T2	2770	44	0	0
T3	635	6	0	0
T4	236219	5130	0	0
T5	433814	0	0	0
T6	628	8	0	0
T16	127341	1360	0	0
T17	0	12	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	23710	0	0
T21	0	66	0	0
T22	0	21157	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3511981	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3511981	0	0
T1	14349	417	0	0
T2	2770	44	0	0
T3	635	6	0	0
T4	236219	5953	0	0
T5	433814	0	0	0
T6	628	8	0	0
T16	127341	671	0	0
T17	0	15	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	7799	0	0
T21	0	66	0	0
T22	0	6848	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1351067	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1351067	0	0
T1	14349	121	0	0
T2	2770	39	0	0
T3	635	7	0	0
T4	236219	5078	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	881	0	0
T17	0	26	0	0
T18	4737	203	0	0
T19	69769	0	0	0
T20	197490	17809	0	0
T21	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	2701928	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	2701928	0	0
T1	14349	121	0	0
T2	2770	39	0	0
T3	635	7	0	0
T4	236219	4761	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	739	0	0
T17	0	42	0	0
T18	4737	203	0	0
T19	69769	0	0	0
T20	197490	7788	0	0
T21	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1329725	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1329725	0	0
T1	14349	387	0	0
T2	2770	50	0	0
T3	635	4	0	0
T4	236219	4365	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	2806	0	0
T17	0	35	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	25353	0	0
T21	0	62	0	0
T22	0	18563	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	2219069	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	2219069	0	0
T1	14349	387	0	0
T2	2770	50	0	0
T3	635	4	0	0
T4	236219	4484	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	228	0	0
T17	0	42	0	0
T18	4737	0	0	0
T19	69769	0	0	0
T20	197490	9709	0	0
T21	0	62	0	0
T22	0	7679	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1391258	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1391258	0	0
T1	14349	140	0	0
T2	2770	45	0	0
T3	635	7	0	0
T4	236219	1953	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	863	0	0
T17	0	12	0	0
T18	4737	473	0	0
T19	69769	0	0	0
T20	197490	21791	0	0
T21	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	2504373	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	2504373	0	0
T1	14349	140	0	0
T2	2770	45	0	0
T3	635	7	0	0
T4	236219	2727	0	0
T5	433814	0	0	0
T6	628	6	0	0
T16	127341	3	0	0
T17	0	55	0	0
T18	4737	473	0	0
T19	69769	0	0	0
T20	197490	6951	0	0
T21	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1449346	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1449346	0	0
T1	14349	148	0	0
T2	2770	52	0	0
T3	635	10	0	0
T4	236219	4751	0	0
T5	433814	0	0	0
T6	628	7	0	0
T16	127341	2259	0	0
T17	0	51	0	0
T18	4737	0	0	0
T19	69769	3183	0	0
T20	197490	24272	0	0
T21	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3593390	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3593390	0	0
T1	14349	148	0	0
T2	2770	52	0	0
T3	635	10	0	0
T4	236219	4684	0	0
T5	433814	0	0	0
T6	628	7	0	0
T16	127341	1309	0	0
T17	0	37	0	0
T18	4737	0	0	0
T19	69769	4588	0	0
T20	197490	8579	0	0
T21	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1411879	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1411879	0	0
T1	14349	152	0	0
T2	2770	39	0	0
T3	635	6	0	0
T4	236219	2701	0	0
T5	433814	0	0	0
T6	628	7	0	0
T16	127341	2829	0	0
T17	0	10	0	0
T18	4737	0	0	0
T19	69769	2602	0	0
T20	197490	22498	0	0
T21	0	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	2848211	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	2848211	0	0
T1	14349	152	0	0
T2	2770	39	0	0
T3	635	6	0	0
T4	236219	2993	0	0
T5	433814	0	0	0
T6	628	7	0	0
T16	127341	395	0	0
T17	0	8	0	0
T18	4737	0	0	0
T19	69769	2357	0	0
T20	197490	10488	0	0
T21	0	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	1448069	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	1448069	0	0
T1	14349	148	0	0
T2	2770	48	0	0
T3	635	1	0	0
T4	236219	2496	0	0
T5	433814	0	0	0
T6	628	10	0	0
T16	127341	1836	0	0
T18	4737	247	0	0
T19	69769	0	0	0
T20	197490	25830	0	0
T21	0	50	0	0
T22	0	21301	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301439264	3721794	0	0
DepthKnown_A	301439264	301321451	0	0
RvalidKnown_A	301439264	301321451	0	0
WreadyKnown_A	301439264	301321451	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	3721794	0	0
T1	14349	148	0	0
T2	2770	48	0	0
T3	635	1	0	0
T4	236219	2684	0	0
T5	433814	0	0	0
T6	628	10	0	0
T16	127341	732	0	0
T18	4737	247	0	0
T19	69769	0	0	0
T20	197490	9568	0	0
T21	0	50	0	0
T22	0	8073	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301439264	301321451	0	0
T1	14349	14301	0	0
T2	2770	2719	0	0
T3	635	585	0	0
T4	236219	235092	0	0
T5	433814	433773	0	0
T6	628	591	0	0
T16	127341	127306	0	0
T18	4737	4676	0	0
T19	69769	69707	0	0
T20	197490	197489	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0