Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1794987	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

282178

1

T1

3

T2

22

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	700443	1			T1	15		T2	30		T3	33
values[0x0]	676373	1			T1	3		T2	43		T3	41
values[0x1]	700349	1			T1	18		T2	51		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1392566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

684599

1

T1

10

T2

43

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8313	1			T4	1		T13	31		T16	11
valid_sources[0x01]	8524	1			T2	2		T4	2		T17	3
valid_sources[0x02]	7608	1			T13	28		T22	1		T16	8
valid_sources[0x03]	7581	1			T4	1		T17	1		T13	20
valid_sources[0x04]	8081	1			T17	1		T13	22		T22	1
valid_sources[0x05]	8474	1			T4	3		T13	47		T16	11
valid_sources[0x06]	8481	1			T13	37		T19	1		T21	1
valid_sources[0x07]	8101	1			T13	40		T22	1		T16	5
valid_sources[0x08]	7852	1			T2	2		T13	32		T16	6
valid_sources[0x09]	9824	1			T2	1		T4	1		T17	1
valid_sources[0x0a]	8630	1			T2	1		T17	1		T13	29
valid_sources[0x0b]	7761	1			T13	19		T23	1		T22	1
valid_sources[0x0c]	7671	1			T3	6		T13	40		T19	1
valid_sources[0x0d]	9557	1			T17	3		T13	31		T14	1
valid_sources[0x0e]	7724	1			T1	6		T13	35		T19	7
valid_sources[0x0f]	7632	1			T2	1		T4	1		T13	55
valid_sources[0x10]	7312	1			T2	1		T13	31		T19	1
valid_sources[0x11]	7796	1			T1	8		T4	4		T13	34
valid_sources[0x12]	8080	1			T17	1		T13	15		T19	1
valid_sources[0x13]	8349	1			T2	1		T4	1		T13	35
valid_sources[0x14]	7663	1			T4	2		T13	21		T19	3
valid_sources[0x15]	7533	1			T13	41		T19	1		T22	2
valid_sources[0x16]	7384	1			T4	3		T17	1		T13	37
valid_sources[0x17]	9752	1			T17	1		T13	22		T20	5
valid_sources[0x18]	8115	1			T4	1		T17	2		T13	21
valid_sources[0x19]	8099	1			T17	1		T13	52		T22	1
valid_sources[0x1a]	7982	1			T2	1		T4	4		T13	31
valid_sources[0x1b]	8013	1			T2	2		T4	1		T13	52
valid_sources[0x1c]	7594	1			T2	1		T4	1		T13	31
valid_sources[0x1d]	7967	1			T2	1		T4	1		T13	74
valid_sources[0x1e]	8351	1			T2	1		T4	1		T13	33
valid_sources[0x1f]	8126	1			T2	4		T4	1		T13	36
valid_sources[0x20]	8450	1			T2	1		T13	41		T14	1
valid_sources[0x21]	7385	1			T2	2		T4	1		T13	41
valid_sources[0x22]	7899	1			T4	1		T13	59		T16	14
valid_sources[0x23]	7414	1			T4	1		T17	2		T13	14
valid_sources[0x24]	8854	1			T2	2		T13	37		T14	1
valid_sources[0x25]	7832	1			T2	1		T4	1		T13	41
valid_sources[0x26]	8366	1			T13	66		T19	2		T23	1
valid_sources[0x27]	7513	1			T13	38		T19	1		T23	1
valid_sources[0x28]	8134	1			T13	25		T16	10		T24	10
valid_sources[0x29]	8810	1			T2	1		T4	3		T17	2
valid_sources[0x2a]	7247	1			T2	1		T17	2		T13	37
valid_sources[0x2b]	7543	1			T4	1		T13	48		T22	1
valid_sources[0x2c]	8390	1			T1	1		T13	10		T20	2
valid_sources[0x2d]	8371	1			T4	1		T13	18		T23	2
valid_sources[0x2e]	8045	1			T2	3		T13	46		T16	10
valid_sources[0x2f]	8164	1			T4	1		T17	1		T13	34
valid_sources[0x30]	9616	1			T4	1		T17	2		T13	22
valid_sources[0x31]	7188	1			T13	35		T16	9		T24	9
valid_sources[0x32]	8037	1			T4	1		T13	52		T19	1
valid_sources[0x33]	7418	1			T4	1		T13	70		T20	3
valid_sources[0x34]	7804	1			T2	2		T4	2		T13	37
valid_sources[0x35]	8246	1			T2	1		T17	1		T13	42
valid_sources[0x36]	7455	1			T4	2		T17	1		T13	33
valid_sources[0x37]	7536	1			T17	1		T13	18		T23	1
valid_sources[0x38]	7839	1			T2	1		T4	2		T17	2
valid_sources[0x39]	8255	1			T4	2		T17	1		T13	36
valid_sources[0x3a]	8699	1			T2	1		T13	50		T16	5
valid_sources[0x3b]	7595	1			T13	36		T16	2		T24	9
valid_sources[0x3c]	7787	1			T2	2		T4	1		T17	1
valid_sources[0x3d]	8539	1			T4	1		T13	27		T19	1
valid_sources[0x3e]	7537	1			T2	1		T4	1		T13	58
valid_sources[0x3f]	8589	1			T2	2		T4	1		T17	1
valid_sources[0x40]	8449	1			T3	12		T4	1		T13	41
valid_sources[0x41]	7856	1			T4	1		T13	51		T19	1
valid_sources[0x42]	7392	1			T4	1		T13	10		T20	10
valid_sources[0x43]	8745	1			T17	1		T13	55		T14	1
valid_sources[0x44]	8036	1			T13	33		T22	1		T16	11
valid_sources[0x45]	8076	1			T4	1		T13	15		T16	6
valid_sources[0x46]	8396	1			T4	1		T13	47		T16	6
valid_sources[0x47]	8554	1			T4	1		T13	30		T19	1
valid_sources[0x48]	8221	1			T13	27		T19	3		T22	1
valid_sources[0x49]	8239	1			T4	3		T13	43		T16	8
valid_sources[0x4a]	7600	1			T17	1		T13	47		T21	1
valid_sources[0x4b]	7460	1			T13	59		T16	6		T24	10
valid_sources[0x4c]	8747	1			T2	1		T4	2		T13	26
valid_sources[0x4d]	8626	1			T4	2		T13	16		T14	1
valid_sources[0x4e]	9213	1			T4	1		T13	21		T23	2
valid_sources[0x4f]	7746	1			T17	1		T13	35		T19	1
valid_sources[0x50]	7825	1			T4	1		T17	1		T13	61
valid_sources[0x51]	7779	1			T13	67		T16	9		T24	11
valid_sources[0x52]	8629	1			T2	1		T13	53		T16	11
valid_sources[0x53]	8203	1			T17	1		T13	23		T19	2
valid_sources[0x54]	7773	1			T2	1		T4	2		T17	1
valid_sources[0x55]	7470	1			T17	1		T13	34		T21	1
valid_sources[0x56]	7756	1			T4	2		T13	31		T19	1
valid_sources[0x57]	8248	1			T1	1		T4	1		T13	47
valid_sources[0x58]	8181	1			T13	54		T19	1		T16	5
valid_sources[0x59]	9658	1			T4	2		T13	30		T19	2
valid_sources[0x5a]	8846	1			T4	1		T13	36		T23	1
valid_sources[0x5b]	7859	1			T4	1		T13	35		T16	4
valid_sources[0x5c]	8038	1			T4	1		T13	17		T19	1
valid_sources[0x5d]	9890	1			T17	2		T13	44		T19	1
valid_sources[0x5e]	9019	1			T13	27		T19	2		T22	1
valid_sources[0x5f]	7434	1			T13	47		T19	1		T20	2
valid_sources[0x60]	8108	1			T2	2		T4	1		T13	48
valid_sources[0x61]	8652	1			T13	36		T19	3		T23	2
valid_sources[0x62]	8728	1			T2	1		T4	1		T13	52
valid_sources[0x63]	6874	1			T4	1		T17	2		T13	20
valid_sources[0x64]	7760	1			T2	1		T13	19		T19	2
valid_sources[0x65]	8644	1			T13	27		T22	1		T16	13
valid_sources[0x66]	9000	1			T2	2		T4	1		T13	23
valid_sources[0x67]	8135	1			T2	1		T17	2		T13	60
valid_sources[0x68]	7875	1			T2	2		T17	1		T13	39
valid_sources[0x69]	7890	1			T2	1		T4	3		T13	27
valid_sources[0x6a]	8221	1			T13	51		T22	1		T16	10
valid_sources[0x6b]	8389	1			T13	22		T16	8		T24	9
valid_sources[0x6c]	9053	1			T13	28		T19	1		T21	1
valid_sources[0x6d]	7913	1			T2	1		T4	1		T13	36
valid_sources[0x6e]	8144	1			T3	3		T4	3		T13	40
valid_sources[0x6f]	7906	1			T17	3		T13	48		T23	1
valid_sources[0x70]	8473	1			T17	5		T13	49		T19	1
valid_sources[0x71]	8335	1			T2	1		T13	32		T18	71
valid_sources[0x72]	7976	1			T4	2		T13	37		T19	1
valid_sources[0x73]	7810	1			T4	1		T13	71		T19	4
valid_sources[0x74]	7922	1			T4	1		T13	59		T19	1
valid_sources[0x75]	8397	1			T4	2		T17	1		T13	15
valid_sources[0x76]	8405	1			T13	35		T19	1		T22	2
valid_sources[0x77]	8143	1			T2	1		T13	13		T22	1
valid_sources[0x78]	7443	1			T4	1		T17	1		T13	53
valid_sources[0x79]	7577	1			T13	26		T16	8		T24	9
valid_sources[0x7a]	7796	1			T17	2		T13	23		T23	1
valid_sources[0x7b]	8633	1			T2	2		T4	2		T13	22
valid_sources[0x7c]	8322	1			T17	1		T13	23		T19	1
valid_sources[0x7d]	8312	1			T13	55		T16	6		T24	10
valid_sources[0x7e]	7661	1			T13	5		T21	1		T22	1
valid_sources[0x7f]	8068	1			T4	2		T17	1		T13	56
valid_sources[0x80]	7370	1			T2	1		T13	25		T22	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29562

1

T2

3

T3

1

T17

2

values[0x0]

all_enables

biggest_size

223479

1

T2

17

T3

8

T4

27

values[0x1]

all_enables

biggest_size

29137

1

T1

3

T2

2

T3

2