Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	348800753	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348800753	0	0
T1	107632	4465	0	0
T2	40880	610	0	0
T3	5204528	166138	0	0
T4	25424	906	0	0
T13	16283456	317959	0	0
T14	46144	692	0	0
T17	8101184	136756	0	0
T18	9586136	166538	0	0
T19	13002360	275197	0	0
T20	216272	4456	0	0
T21	0	1863	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	107632	106064	0	0
T2	40880	36904	0	0
T3	5204528	5201616	0	0
T4	25424	24584	0	0
T13	16283456	16261112	0	0
T14	46144	42952	0	0
T17	8101184	8097936	0	0
T18	9586136	9583504	0	0
T19	13002360	12999112	0	0
T20	216272	212464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	107632	106064	0	0
T2	40880	36904	0	0
T3	5204528	5201616	0	0
T4	25424	24584	0	0
T13	16283456	16261112	0	0
T14	46144	42952	0	0
T17	8101184	8097936	0	0
T18	9586136	9583504	0	0
T19	13002360	12999112	0	0
T20	216272	212464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	107632	106064	0	0
T2	40880	36904	0	0
T3	5204528	5201616	0	0
T4	25424	24584	0	0
T13	16283456	16261112	0	0
T14	46144	42952	0	0
T17	8101184	8097936	0	0
T18	9586136	9583504	0	0
T19	13002360	12999112	0	0
T20	216272	212464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	126012978	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	126012978	0	0
T1	1922	1738	0	0
T2	730	238	0	0
T3	92938	90251	0	0
T4	454	348	0	0
T13	290776	129692	0	0
T14	824	341	0	0
T17	144664	67083	0	0
T18	171181	72637	0	0
T19	232185	115189	0	0
T20	3862	1790	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	91542741	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	91542741	0	0
T1	1922	909	0	0
T2	730	124	0	0
T3	92938	37682	0	0
T4	454	186	0	0
T13	290776	61934	0	0
T14	824	173	0	0
T17	144664	13260	0	0
T18	171181	21404	0	0
T19	232185	52186	0	0
T20	3862	898	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1503984	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1503984	0	0
T1	1922	30	0	0
T2	730	4	0	0
T3	92938	41	0	0
T4	454	4	0	0
T13	290776	3290	0	0
T14	824	4	0	0
T17	144664	23	0	0
T18	171181	1954	0	0
T19	232185	2808	0	0
T20	3862	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3208631	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3208631	0	0
T1	1922	30	0	0
T2	730	4	0	0
T3	92938	1758	0	0
T4	454	4	0	0
T13	290776	2868	0	0
T14	824	4	0	0
T17	144664	1	0	0
T18	171181	97	0	0
T19	232185	1498	0	0
T20	3862	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1483467	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1483467	0	0
T1	1922	28	0	0
T2	730	2	0	0
T3	92938	12	0	0
T4	454	3	0	0
T13	290776	1713	0	0
T14	824	6	0	0
T17	144664	2061	0	0
T18	171181	756	0	0
T19	232185	886	0	0
T20	3862	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3205264	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3205264	0	0
T1	1922	28	0	0
T2	730	2	0	0
T3	92938	1349	0	0
T4	454	3	0	0
T13	290776	1421	0	0
T14	824	6	0	0
T17	144664	922	0	0
T18	171181	267	0	0
T19	232185	1057	0	0
T20	3862	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1469405	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1469405	0	0
T1	1922	34	0	0
T2	730	3	0	0
T3	92938	4	0	0
T4	454	4	0	0
T13	290776	4453	0	0
T14	824	1	0	0
T17	144664	2010	0	0
T18	171181	588	0	0
T19	232185	3088	0	0
T20	3862	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3307428	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3307428	0	0
T1	1922	34	0	0
T2	730	3	0	0
T3	92938	327	0	0
T4	454	4	0	0
T13	290776	3954	0	0
T14	824	1	0	0
T17	144664	1510	0	0
T18	171181	1070	0	0
T19	232185	2411	0	0
T20	3862	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1538042	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1538042	0	0
T1	1922	30	0	0
T2	730	3	0	0
T3	92938	25	0	0
T4	454	3	0	0
T13	290776	1599	0	0
T14	824	3	0	0
T17	144664	3347	0	0
T18	171181	3335	0	0
T19	232185	0	0	0
T20	3862	34	0	0
T21	0	175	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3445029	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3445029	0	0
T1	1922	30	0	0
T2	730	3	0	0
T3	92938	1136	0	0
T4	454	3	0	0
T13	290776	1334	0	0
T14	824	3	0	0
T17	144664	629	0	0
T18	171181	882	0	0
T19	232185	0	0	0
T20	3862	45	0	0
T21	0	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1540021	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1540021	0	0
T1	1922	37	0	0
T2	730	5	0	0
T3	92938	24	0	0
T4	454	7	0	0
T13	290776	1889	0	0
T14	824	2	0	0
T17	144664	1352	0	0
T18	171181	714	0	0
T19	232185	3257	0	0
T20	3862	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3504073	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3504073	0	0
T1	1922	37	0	0
T2	730	5	0	0
T3	92938	1600	0	0
T4	454	7	0	0
T13	290776	1540	0	0
T14	824	2	0	0
T17	144664	354	0	0
T18	171181	72	0	0
T19	232185	2050	0	0
T20	3862	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1486699	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1486699	0	0
T1	1922	25	0	0
T2	730	3	0	0
T3	92938	9	0	0
T4	454	8	0	0
T13	290776	1832	0	0
T14	824	2	0	0
T17	144664	686	0	0
T18	171181	1776	0	0
T19	232185	2267	0	0
T20	3862	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3578514	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3578514	0	0
T1	1922	25	0	0
T2	730	3	0	0
T3	92938	869	0	0
T4	454	8	0	0
T13	290776	1420	0	0
T14	824	2	0	0
T17	144664	755	0	0
T18	171181	731	0	0
T19	232185	2452	0	0
T20	3862	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1545735	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1545735	0	0
T1	1922	25	0	0
T2	730	6	0	0
T3	92938	39	0	0
T4	454	8	0	0
T13	290776	1926	0	0
T14	824	0	0	0
T17	144664	1692	0	0
T18	171181	1686	0	0
T19	232185	4389	0	0
T20	3862	28	0	0
T21	0	200	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3912827	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3912827	0	0
T1	1922	25	0	0
T2	730	6	0	0
T3	92938	2533	0	0
T4	454	8	0	0
T13	290776	1696	0	0
T14	824	0	0	0
T17	144664	572	0	0
T18	171181	826	0	0
T19	232185	5036	0	0
T20	3862	18	0	0
T21	0	139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1474056	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1474056	0	0
T1	1922	32	0	0
T2	730	1	0	0
T3	92938	32	0	0
T4	454	7	0	0
T13	290776	1775	0	0
T14	824	3	0	0
T17	144664	3321	0	0
T18	171181	1953	0	0
T19	232185	1883	0	0
T20	3862	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3349721	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3349721	0	0
T1	1922	32	0	0
T2	730	1	0	0
T3	92938	1955	0	0
T4	454	7	0	0
T13	290776	1625	0	0
T14	824	3	0	0
T17	144664	1126	0	0
T18	171181	518	0	0
T19	232185	1310	0	0
T20	3862	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1510213	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1510213	0	0
T1	1922	31	0	0
T2	730	2	0	0
T3	92938	25	0	0
T4	454	11	0	0
T13	290776	1877	0	0
T14	824	2	0	0
T17	144664	1655	0	0
T18	171181	1367	0	0
T19	232185	297	0	0
T20	3862	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3258967	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3258967	0	0
T1	1922	31	0	0
T2	730	2	0	0
T3	92938	2330	0	0
T4	454	11	0	0
T13	290776	1698	0	0
T14	824	2	0	0
T17	144664	1239	0	0
T18	171181	852	0	0
T19	232185	771	0	0
T20	3862	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1535227	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1535227	0	0
T1	1922	45	0	0
T2	730	5	0	0
T3	92938	14	0	0
T4	454	11	0	0
T13	290776	1798	0	0
T14	824	1	0	0
T17	144664	3371	0	0
T18	171181	2463	0	0
T19	232185	1756	0	0
T20	3862	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3518067	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3518067	0	0
T1	1922	45	0	0
T2	730	5	0	0
T3	92938	367	0	0
T4	454	11	0	0
T13	290776	1681	0	0
T14	824	1	0	0
T17	144664	839	0	0
T18	171181	281	0	0
T19	232185	656	0	0
T20	3862	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1484115	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1484115	0	0
T1	1922	43	0	0
T2	730	5	0	0
T3	92938	18	0	0
T4	454	7	0	0
T13	290776	1917	0	0
T14	824	8	0	0
T17	144664	1355	0	0
T18	171181	3311	0	0
T19	232185	1829	0	0
T20	3862	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3773335	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3773335	0	0
T1	1922	43	0	0
T2	730	5	0	0
T3	92938	539	0	0
T4	454	7	0	0
T13	290776	1727	0	0
T14	824	8	0	0
T17	144664	278	0	0
T18	171181	1666	0	0
T19	232185	2803	0	0
T20	3862	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1490349	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1490349	0	0
T1	1922	39	0	0
T2	730	8	0	0
T3	92938	17	0	0
T4	454	6	0	0
T13	290776	6037	0	0
T14	824	2	0	0
T17	144664	2693	0	0
T18	171181	3807	0	0
T19	232185	2197	0	0
T20	3862	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3349378	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3349378	0	0
T1	1922	39	0	0
T2	730	8	0	0
T3	92938	2573	0	0
T4	454	6	0	0
T13	290776	4608	0	0
T14	824	2	0	0
T17	144664	260	0	0
T18	171181	1368	0	0
T19	232185	2142	0	0
T20	3862	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1472619	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1472619	0	0
T1	1922	30	0	0
T2	730	8	0	0
T3	92938	12	0	0
T4	454	4	0	0
T13	290776	2091	0	0
T14	824	3	0	0
T17	144664	960	0	0
T18	171181	3193	0	0
T19	232185	1485	0	0
T20	3862	0	0	0
T21	0	273	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3350563	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3350563	0	0
T1	1922	30	0	0
T2	730	8	0	0
T3	92938	2051	0	0
T4	454	4	0	0
T13	290776	1778	0	0
T14	824	3	0	0
T17	144664	1	0	0
T18	171181	625	0	0
T19	232185	2066	0	0
T20	3862	0	0	0
T21	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1457334	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1457334	0	0
T1	1922	30	0	0
T2	730	2	0	0
T3	92938	9	0	0
T4	454	6	0	0
T13	290776	2075	0	0
T14	824	1	0	0
T17	144664	359	0	0
T18	171181	1772	0	0
T19	232185	1310	0	0
T20	3862	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3747014	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3747014	0	0
T1	1922	30	0	0
T2	730	2	0	0
T3	92938	648	0	0
T4	454	6	0	0
T13	290776	1530	0	0
T14	824	1	0	0
T17	144664	480	0	0
T18	171181	554	0	0
T19	232185	2061	0	0
T20	3862	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1498780	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1498780	0	0
T1	1922	37	0	0
T2	730	4	0	0
T3	92938	49	0	0
T4	454	8	0	0
T13	290776	3237	0	0
T14	824	7	0	0
T17	144664	1214	0	0
T18	171181	1402	0	0
T19	232185	1120	0	0
T20	3862	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3088728	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3088728	0	0
T1	1922	37	0	0
T2	730	4	0	0
T3	92938	3776	0	0
T4	454	8	0	0
T13	290776	2785	0	0
T14	824	7	0	0
T17	144664	177	0	0
T18	171181	1362	0	0
T19	232185	1747	0	0
T20	3862	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1487736	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1487736	0	0
T1	1922	31	0	0
T2	730	9	0	0
T3	92938	17	0	0
T4	454	1	0	0
T13	290776	2029	0	0
T14	824	5	0	0
T17	144664	877	0	0
T18	171181	2984	0	0
T19	232185	2925	0	0
T20	3862	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	2195138	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	2195138	0	0
T1	1922	31	0	0
T2	730	9	0	0
T3	92938	770	0	0
T4	454	1	0	0
T13	290776	1642	0	0
T14	824	5	0	0
T17	144664	124	0	0
T18	171181	403	0	0
T19	232185	1286	0	0
T20	3862	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1545898	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1545898	0	0
T1	1922	36	0	0
T2	730	7	0	0
T3	92938	25	0	0
T4	454	15	0	0
T13	290776	1965	0	0
T14	824	2	0	0
T17	144664	1172	0	0
T18	171181	2123	0	0
T19	232185	1680	0	0
T20	3862	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3895429	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3895429	0	0
T1	1922	36	0	0
T2	730	7	0	0
T3	92938	1607	0	0
T4	454	15	0	0
T13	290776	1585	0	0
T14	824	2	0	0
T17	144664	559	0	0
T18	171181	1007	0	0
T19	232185	1459	0	0
T20	3862	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1504370	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1504370	0	0
T1	1922	39	0	0
T2	730	6	0	0
T3	92938	0	0	0
T4	454	8	0	0
T13	290776	3506	0	0
T14	824	1	0	0
T17	144664	1122	0	0
T18	171181	1966	0	0
T19	232185	610	0	0
T20	3862	75	0	0
T21	0	186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3783820	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3783820	0	0
T1	1922	39	0	0
T2	730	6	0	0
T3	92938	0	0	0
T4	454	8	0	0
T13	290776	2947	0	0
T14	824	1	0	0
T17	144664	38	0	0
T18	171181	1219	0	0
T19	232185	1451	0	0
T20	3862	46	0	0
T21	0	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1522334	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1522334	0	0
T1	1922	35	0	0
T2	730	5	0	0
T3	92938	5	0	0
T4	454	11	0	0
T13	290776	2668	0	0
T14	824	7	0	0
T17	144664	1271	0	0
T18	171181	1920	0	0
T19	232185	715	0	0
T20	3862	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3174374	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3174374	0	0
T1	1922	35	0	0
T2	730	5	0	0
T3	92938	994	0	0
T4	454	11	0	0
T13	290776	2105	0	0
T14	824	7	0	0
T17	144664	249	0	0
T18	171181	912	0	0
T19	232185	2108	0	0
T20	3862	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1465214	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1465214	0	0
T1	1922	33	0	0
T2	730	6	0	0
T3	92938	13	0	0
T4	454	3	0	0
T13	290776	1792	0	0
T14	824	7	0	0
T17	144664	1885	0	0
T18	171181	1131	0	0
T19	232185	4705	0	0
T20	3862	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3392691	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3392691	0	0
T1	1922	33	0	0
T2	730	6	0	0
T3	92938	345	0	0
T4	454	3	0	0
T13	290776	1650	0	0
T14	824	7	0	0
T17	144664	571	0	0
T18	171181	762	0	0
T19	232185	2515	0	0
T20	3862	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1487821	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1487821	0	0
T1	1922	37	0	0
T2	730	3	0	0
T3	92938	0	0	0
T4	454	3	0	0
T13	290776	4348	0	0
T14	824	3	0	0
T17	144664	1293	0	0
T18	171181	1856	0	0
T19	232185	1520	0	0
T20	3862	21	0	0
T21	0	270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3001581	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3001581	0	0
T1	1922	37	0	0
T2	730	3	0	0
T3	92938	0	0	0
T4	454	3	0	0
T13	290776	3566	0	0
T14	824	3	0	0
T17	144664	383	0	0
T18	171181	1723	0	0
T19	232185	1309	0	0
T20	3862	38	0	0
T21	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1471059	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1471059	0	0
T1	1922	31	0	0
T2	730	2	0	0
T3	92938	16	0	0
T4	454	9	0	0
T13	290776	1567	0	0
T14	824	3	0	0
T17	144664	1291	0	0
T18	171181	1458	0	0
T19	232185	2804	0	0
T20	3862	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3755679	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3755679	0	0
T1	1922	31	0	0
T2	730	2	0	0
T3	92938	446	0	0
T4	454	9	0	0
T13	290776	1272	0	0
T14	824	3	0	0
T17	144664	465	0	0
T18	171181	575	0	0
T19	232185	2421	0	0
T20	3862	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1539497	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1539497	0	0
T1	1922	32	0	0
T2	730	7	0	0
T3	92938	16	0	0
T4	454	8	0	0
T13	290776	2072	0	0
T14	824	0	0	0
T17	144664	2623	0	0
T18	171181	859	0	0
T19	232185	2491	0	0
T20	3862	51	0	0
T21	0	210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3391566	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3391566	0	0
T1	1922	32	0	0
T2	730	7	0	0
T3	92938	1622	0	0
T4	454	8	0	0
T13	290776	1749	0	0
T14	824	0	0	0
T17	144664	735	0	0
T18	171181	497	0	0
T19	232185	2307	0	0
T20	3862	23	0	0
T21	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1510175	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1510175	0	0
T1	1922	40	0	0
T2	730	6	0	0
T3	92938	47	0	0
T4	454	6	0	0
T13	290776	4314	0	0
T14	824	4	0	0
T17	144664	1032	0	0
T18	171181	816	0	0
T19	232185	1863	0	0
T20	3862	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	2762647	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	2762647	0	0
T1	1922	40	0	0
T2	730	6	0	0
T3	92938	3541	0	0
T4	454	6	0	0
T13	290776	3113	0	0
T14	824	4	0	0
T17	144664	128	0	0
T18	171181	120	0	0
T19	232185	2767	0	0
T20	3862	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1538439	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1538439	0	0
T1	1922	39	0	0
T2	730	6	0	0
T3	92938	23	0	0
T4	454	8	0	0
T13	290776	1934	0	0
T14	824	7	0	0
T17	144664	930	0	0
T18	171181	2152	0	0
T19	232185	2788	0	0
T20	3862	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3767103	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3767103	0	0
T1	1922	39	0	0
T2	730	6	0	0
T3	92938	1671	0	0
T4	454	8	0	0
T13	290776	1465	0	0
T14	824	7	0	0
T17	144664	48	0	0
T18	171181	416	0	0
T19	232185	2612	0	0
T20	3862	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1470595	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1470595	0	0
T1	1922	26	0	0
T2	730	3	0	0
T3	92938	9	0	0
T4	454	8	0	0
T13	290776	3683	0	0
T14	824	2	0	0
T17	144664	901	0	0
T18	171181	2639	0	0
T19	232185	4408	0	0
T20	3862	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	3065586	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	3065586	0	0
T1	1922	26	0	0
T2	730	3	0	0
T3	92938	766	0	0
T4	454	8	0	0
T13	290776	2890	0	0
T14	824	2	0	0
T17	144664	243	0	0
T18	171181	2015	0	0
T19	232185	2843	0	0
T20	3862	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	1530689	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	1530689	0	0
T1	1922	34	0	0
T2	730	3	0	0
T3	92938	22	0	0
T4	454	9	0	0
T13	290776	1829	0	0
T14	824	3	0	0
T17	144664	2657	0	0
T18	171181	1112	0	0
T19	232185	555	0	0
T20	3862	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319751892	2898008	0	0
DepthKnown_A	319751892	319630222	0	0
RvalidKnown_A	319751892	319630222	0	0
WreadyKnown_A	319751892	319630222	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	2898008	0	0
T1	1922	34	0	0
T2	730	3	0	0
T3	92938	2109	0	0
T4	454	9	0	0
T13	290776	1468	0	0
T14	824	3	0	0
T17	144664	574	0	0
T18	171181	584	0	0
T19	232185	1048	0	0
T20	3862	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319751892	319630222	0	0
T1	1922	1894	0	0
T2	730	659	0	0
T3	92938	92886	0	0
T4	454	439	0	0
T13	290776	290377	0	0
T14	824	767	0	0
T17	144664	144606	0	0
T18	171181	171134	0	0
T19	232185	232127	0	0
T20	3862	3794	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0