Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1760921	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

277866

1

T1

13

T2

149

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	688982	1			T1	47		T2	338		T3	28
values[0x0]	661040	1			T1	31		T2	356		T3	38
values[0x1]	688765	1			T1	36		T2	372		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1365710	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

673077

1

T1

36

T2

365

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7398	1			T3	1		T5	17		T4	1
valid_sources[0x01]	7154	1			T3	1		T5	18		T4	1
valid_sources[0x02]	8100	1			T2	142		T5	19		T4	1
valid_sources[0x03]	7209	1			T5	19		T4	2		T18	4
valid_sources[0x04]	8477	1			T3	1		T5	18		T18	2
valid_sources[0x05]	7429	1			T3	1		T5	17		T4	1
valid_sources[0x06]	8074	1			T5	21		T18	10		T16	91
valid_sources[0x07]	7798	1			T5	17		T18	6		T15	2
valid_sources[0x08]	8421	1			T5	17		T18	7		T16	72
valid_sources[0x09]	7165	1			T5	20		T18	5		T14	2
valid_sources[0x0a]	8147	1			T5	16		T18	5		T15	6
valid_sources[0x0b]	9674	1			T3	1		T5	21		T18	6
valid_sources[0x0c]	7102	1			T1	1		T3	3		T5	17
valid_sources[0x0d]	7548	1			T1	2		T5	17		T18	6
valid_sources[0x0e]	7134	1			T5	17		T4	1		T18	4
valid_sources[0x0f]	8190	1			T3	1		T5	20		T4	2
valid_sources[0x10]	7799	1			T5	17		T18	7		T14	3
valid_sources[0x11]	7231	1			T1	1		T3	2		T5	16
valid_sources[0x12]	7632	1			T5	18		T18	11		T14	2
valid_sources[0x13]	7073	1			T5	19		T18	7		T15	17
valid_sources[0x14]	7431	1			T3	2		T5	18		T18	11
valid_sources[0x15]	8385	1			T5	15		T18	8		T15	1
valid_sources[0x16]	7911	1			T5	18		T18	5		T14	1
valid_sources[0x17]	7508	1			T5	18		T4	1		T18	8
valid_sources[0x18]	7503	1			T1	1		T5	17		T18	5
valid_sources[0x19]	7347	1			T1	2		T5	20		T18	10
valid_sources[0x1a]	6780	1			T3	2		T5	20		T18	9
valid_sources[0x1b]	8529	1			T3	1		T5	16		T18	6
valid_sources[0x1c]	8377	1			T2	38		T5	21		T4	1
valid_sources[0x1d]	8647	1			T1	3		T5	16		T18	9
valid_sources[0x1e]	7508	1			T1	1		T2	124		T5	17
valid_sources[0x1f]	7637	1			T1	2		T3	1		T5	18
valid_sources[0x20]	8404	1			T3	2		T5	16		T18	4
valid_sources[0x21]	7376	1			T5	18		T18	8		T15	8
valid_sources[0x22]	8973	1			T5	18		T18	3		T16	106
valid_sources[0x23]	7475	1			T5	18		T4	1		T18	8
valid_sources[0x24]	8470	1			T3	1		T5	18		T18	3
valid_sources[0x25]	7749	1			T5	18		T18	9		T14	2
valid_sources[0x26]	7220	1			T1	4		T3	1		T5	18
valid_sources[0x27]	8911	1			T1	1		T3	1		T5	19
valid_sources[0x28]	8225	1			T1	3		T3	1		T5	18
valid_sources[0x29]	8380	1			T3	1		T5	17		T18	4
valid_sources[0x2a]	7248	1			T5	15		T18	10		T15	16
valid_sources[0x2b]	7637	1			T1	2		T5	18		T4	1
valid_sources[0x2c]	7487	1			T5	18		T4	1		T18	5
valid_sources[0x2d]	7433	1			T5	18		T18	3		T15	3
valid_sources[0x2e]	7396	1			T1	2		T5	16		T18	6
valid_sources[0x2f]	7710	1			T5	20		T18	11		T14	1
valid_sources[0x30]	7003	1			T5	19		T4	1		T18	5
valid_sources[0x31]	7804	1			T5	18		T18	8		T14	1
valid_sources[0x32]	8424	1			T5	20		T18	5		T14	1
valid_sources[0x33]	7040	1			T5	17		T18	5		T14	1
valid_sources[0x34]	8480	1			T1	1		T2	62		T3	1
valid_sources[0x35]	8079	1			T1	4		T5	18		T18	5
valid_sources[0x36]	7635	1			T3	3		T5	20		T18	4
valid_sources[0x37]	8237	1			T3	1		T5	16		T18	6
valid_sources[0x38]	7822	1			T3	2		T5	16		T18	3
valid_sources[0x39]	7681	1			T5	19		T18	3		T16	72
valid_sources[0x3a]	8161	1			T5	16		T4	2		T18	9
valid_sources[0x3b]	8527	1			T3	2		T5	18		T4	1
valid_sources[0x3c]	7667	1			T1	1		T5	17		T18	4
valid_sources[0x3d]	7230	1			T5	17		T18	2		T15	12
valid_sources[0x3e]	7957	1			T3	1		T5	20		T18	7
valid_sources[0x3f]	7183	1			T1	3		T5	16		T18	6
valid_sources[0x40]	7934	1			T3	1		T5	17		T18	5
valid_sources[0x41]	8466	1			T5	17		T18	6		T14	1
valid_sources[0x42]	7597	1			T5	18		T18	5		T14	1
valid_sources[0x43]	7609	1			T5	17		T18	9		T15	8
valid_sources[0x44]	7649	1			T1	2		T5	20		T18	6
valid_sources[0x45]	8838	1			T5	19		T18	8		T14	1
valid_sources[0x46]	7836	1			T3	1		T5	18		T18	8
valid_sources[0x47]	8262	1			T1	3		T2	61		T5	16
valid_sources[0x48]	8271	1			T5	19		T18	4		T14	2
valid_sources[0x49]	8664	1			T1	2		T3	1		T5	19
valid_sources[0x4a]	7222	1			T1	3		T3	1		T5	19
valid_sources[0x4b]	9097	1			T5	18		T4	2		T18	7
valid_sources[0x4c]	9142	1			T2	14		T3	1		T5	18
valid_sources[0x4d]	7389	1			T1	1		T5	19		T4	1
valid_sources[0x4e]	7632	1			T5	18		T18	5		T14	1
valid_sources[0x4f]	7716	1			T5	16		T4	1		T18	11
valid_sources[0x50]	7422	1			T5	17		T18	7		T16	80
valid_sources[0x51]	7514	1			T1	1		T3	1		T5	18
valid_sources[0x52]	7716	1			T1	1		T5	19		T4	2
valid_sources[0x53]	8719	1			T1	4		T5	18		T4	1
valid_sources[0x54]	8158	1			T3	1		T5	18		T18	6
valid_sources[0x55]	9717	1			T3	1		T5	19		T18	9
valid_sources[0x56]	7913	1			T1	1		T3	1		T5	19
valid_sources[0x57]	8257	1			T1	2		T5	18		T18	7
valid_sources[0x58]	8864	1			T5	17		T18	5		T16	120
valid_sources[0x59]	9162	1			T3	1		T5	16		T18	10
valid_sources[0x5a]	10579	1			T5	19		T18	10		T15	10
valid_sources[0x5b]	8085	1			T5	19		T18	9		T15	4
valid_sources[0x5c]	7893	1			T5	18		T18	8		T15	13
valid_sources[0x5d]	8413	1			T3	1		T5	17		T18	3
valid_sources[0x5e]	7979	1			T5	16		T18	5		T15	11
valid_sources[0x5f]	9120	1			T3	3		T5	15		T18	11
valid_sources[0x60]	8262	1			T5	17		T18	7		T15	2
valid_sources[0x61]	7681	1			T5	19		T18	9		T14	1
valid_sources[0x62]	7815	1			T5	19		T4	2		T18	11
valid_sources[0x63]	7262	1			T5	17		T18	6		T14	1
valid_sources[0x64]	7786	1			T5	17		T18	6		T15	3
valid_sources[0x65]	7780	1			T1	1		T5	21		T18	5
valid_sources[0x66]	8617	1			T3	1		T5	18		T18	2
valid_sources[0x67]	7634	1			T3	1		T5	17		T4	2
valid_sources[0x68]	8034	1			T3	2		T5	16		T18	8
valid_sources[0x69]	8585	1			T5	16		T18	5		T16	76
valid_sources[0x6a]	8737	1			T1	2		T5	19		T18	9
valid_sources[0x6b]	7961	1			T5	18		T18	8		T15	21
valid_sources[0x6c]	8592	1			T5	19		T18	5		T15	11
valid_sources[0x6d]	6949	1			T1	2		T5	16		T18	7
valid_sources[0x6e]	8504	1			T5	18		T18	7		T15	5
valid_sources[0x6f]	7810	1			T1	2		T5	20		T18	8
valid_sources[0x70]	7459	1			T5	18		T18	5		T14	1
valid_sources[0x71]	8578	1			T5	17		T4	1		T18	8
valid_sources[0x72]	8472	1			T5	19		T18	5		T15	1
valid_sources[0x73]	8579	1			T2	218		T5	18		T4	1
valid_sources[0x74]	7073	1			T3	1		T5	18		T18	4
valid_sources[0x75]	8190	1			T5	17		T18	7		T14	1
valid_sources[0x76]	9891	1			T1	2		T5	17		T18	18
valid_sources[0x77]	7888	1			T3	2		T5	17		T18	3
valid_sources[0x78]	7211	1			T1	3		T5	18		T4	1
valid_sources[0x79]	7443	1			T5	16		T18	5		T15	9
valid_sources[0x7a]	7852	1			T5	19		T18	5		T15	7
valid_sources[0x7b]	8329	1			T5	16		T18	4		T15	14
valid_sources[0x7c]	7646	1			T5	20		T18	7		T14	2
valid_sources[0x7d]	7997	1			T5	18		T18	6		T15	6
valid_sources[0x7e]	8672	1			T5	18		T18	5		T15	5
valid_sources[0x7f]	7868	1			T5	19		T18	6		T15	23
valid_sources[0x80]	7965	1			T1	1		T5	18		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29145

1

T1

2

T2

15

T3

1

values[0x0]

all_enables

biggest_size

219682

1

T1

11

T2

114

T3

11

values[0x1]

all_enables

biggest_size

29039

1

T2

20

T3

2

T5

44