Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	331328658	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	331328658	0	0
T1	5252202	173384	0	0
T2	122640	5237	0	0
T3	4980696	147112	0	0
T4	3218880	56877	0	0
T5	23402680	1884680	0	0
T14	11037992	256249	0	0
T15	1841504	42382	0	0
T16	30052008	737815	0	0
T18	200424	8749	0	0
T19	180712	3286	0	0
T20	742	178	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5446728	5443648	0	0
T2	122640	121352	0	0
T3	4980696	4977784	0	0
T4	3218880	3214456	0	0
T5	23402680	23402512	0	0
T14	11037992	11036368	0	0
T15	1841504	1838816	0	0
T16	30052008	30039688	0	0
T18	200424	199080	0	0
T19	180712	179536	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5446728	5443648	0	0
T2	122640	121352	0	0
T3	4980696	4977784	0	0
T4	3218880	3214456	0	0
T5	23402680	23402512	0	0
T14	11037992	11036368	0	0
T15	1841504	1838816	0	0
T16	30052008	30039688	0	0
T18	200424	199080	0	0
T19	180712	179536	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5446728	5443648	0	0
T2	122640	121352	0	0
T3	4980696	4977784	0	0
T4	3218880	3214456	0	0
T5	23402680	23402512	0	0
T14	11037992	11036368	0	0
T15	1841504	1838816	0	0
T16	30052008	30039688	0	0
T18	200424	199080	0	0
T19	180712	179536	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	129800206	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	129800206	0	0
T1	97263	95830	0	0
T2	2190	2039	0	0
T3	88941	87461	0	0
T4	57480	55414	0	0
T5	417905	21205	0	0
T14	197107	118609	0	0
T15	32884	16302	0	0
T16	536643	295878	0	0
T18	3579	3403	0	0
T19	3227	1438	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	80664489	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	80664489	0	0
T1	97263	38551	0	0
T2	2190	1066	0	0
T3	88941	29604	0	0
T4	57480	509	0	0
T5	417905	167507	0	0
T14	197107	45066	0	0
T15	32884	13817	0	0
T16	536643	145194	0	0
T18	3579	1782	0	0
T19	3227	451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1506191	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1506191	0	0
T1	97263	9	0	0
T2	2190	41	0	0
T3	88941	13	0	0
T4	57480	21	0	0
T5	417905	0	0	0
T14	197107	1862	0	0
T15	32884	299	0	0
T16	536643	12490	0	0
T18	3579	63	0	0
T19	3227	33	0	0
T20	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2404119	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2404119	0	0
T1	97263	973	0	0
T2	2190	41	0	0
T3	88941	1078	0	0
T4	57480	6	0	0
T5	417905	0	0	0
T14	197107	2974	0	0
T15	32884	253	0	0
T16	536643	10041	0	0
T18	3579	63	0	0
T19	3227	17	0	0
T20	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1523514	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1523514	0	0
T1	97263	24	0	0
T2	2190	48	0	0
T3	88941	5	0	0
T4	57480	16	0	0
T5	417905	950	0	0
T14	197107	2260	0	0
T15	32884	293	0	0
T16	536643	4142	0	0
T18	3579	78	0	0
T19	3227	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3176568	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3176568	0	0
T1	97263	1322	0	0
T2	2190	48	0	0
T3	88941	1	0	0
T4	57480	3	0	0
T5	417905	80989	0	0
T14	197107	996	0	0
T15	32884	266	0	0
T16	536643	3650	0	0
T18	3579	78	0	0
T19	3227	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1482992	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1482992	0	0
T1	97263	19	0	0
T2	2190	50	0	0
T3	88941	8	0	0
T4	57480	37	0	0
T5	417905	993	0	0
T14	197107	1357	0	0
T15	32884	126	0	0
T16	536643	9322	0	0
T18	3579	60	0	0
T19	3227	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3053139	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3053139	0	0
T1	97263	553	0	0
T2	2190	50	0	0
T3	88941	190	0	0
T4	57480	10	0	0
T5	417905	75819	0	0
T14	197107	2893	0	0
T15	32884	125	0	0
T16	536643	8387	0	0
T18	3579	60	0	0
T19	3227	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1515808	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1515808	0	0
T1	97263	12	0	0
T2	2190	48	0	0
T3	88941	5	0	0
T4	57480	36	0	0
T5	417905	1358	0	0
T14	197107	1395	0	0
T15	32884	192	0	0
T16	536643	4464	0	0
T18	3579	59	0	0
T19	3227	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3356977	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3356977	0	0
T1	97263	525	0	0
T2	2190	48	0	0
T3	88941	1105	0	0
T4	57480	10	0	0
T5	417905	111699	0	0
T14	197107	897	0	0
T15	32884	163	0	0
T16	536643	3804	0	0
T18	3579	59	0	0
T19	3227	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1554594	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1554594	0	0
T1	97263	23	0	0
T2	2190	46	0	0
T3	88941	17	0	0
T4	57480	13	0	0
T5	417905	1204	0	0
T14	197107	836	0	0
T15	32884	218	0	0
T16	536643	2219	0	0
T18	3579	62	0	0
T19	3227	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2556999	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2556999	0	0
T1	97263	1528	0	0
T2	2190	46	0	0
T3	88941	1943	0	0
T4	57480	4	0	0
T5	417905	90636	0	0
T14	197107	407	0	0
T15	32884	295	0	0
T16	536643	1811	0	0
T18	3579	62	0	0
T19	3227	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1577668	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1577668	0	0
T1	97263	18	0	0
T2	2190	41	0	0
T3	88941	17	0	0
T4	57480	22	0	0
T5	417905	1351	0	0
T14	197107	2957	0	0
T15	32884	315	0	0
T16	536643	7893	0	0
T18	3579	64	0	0
T19	3227	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3459170	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3459170	0	0
T1	97263	1888	0	0
T2	2190	41	0	0
T3	88941	856	0	0
T4	57480	5	0	0
T5	417905	106200	0	0
T14	197107	2139	0	0
T15	32884	292	0	0
T16	536643	7270	0	0
T18	3579	64	0	0
T19	3227	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1535094	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1535094	0	0
T1	97263	10	0	0
T2	2190	42	0	0
T3	88941	9	0	0
T4	57480	18	0	0
T5	417905	1236	0	0
T14	197107	1157	0	0
T15	32884	342	0	0
T16	536643	10761	0	0
T18	3579	76	0	0
T19	3227	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2629249	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2629249	0	0
T1	97263	623	0	0
T2	2190	42	0	0
T3	88941	1068	0	0
T4	57480	5	0	0
T5	417905	97790	0	0
T14	197107	2100	0	0
T15	32884	283	0	0
T16	536643	8965	0	0
T18	3579	76	0	0
T19	3227	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1498279	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1498279	0	0
T1	97263	27	0	0
T2	2190	34	0	0
T3	88941	19	0	0
T4	57480	9	0	0
T5	417905	0	0	0
T14	197107	2254	0	0
T15	32884	204	0	0
T16	536643	3942	0	0
T18	3579	58	0	0
T19	3227	35	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3331991	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3331991	0	0
T1	97263	3698	0	0
T2	2190	34	0	0
T3	88941	2135	0	0
T4	57480	1	0	0
T5	417905	0	0	0
T14	197107	2626	0	0
T15	32884	154	0	0
T16	536643	3376	0	0
T18	3579	58	0	0
T19	3227	14	0	0
T20	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1544800	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1544800	0	0
T1	97263	12	0	0
T2	2190	41	0	0
T3	88941	18	0	0
T4	57480	24	0	0
T5	417905	1152	0	0
T14	197107	2314	0	0
T15	32884	227	0	0
T16	536643	2464	0	0
T18	3579	58	0	0
T19	3227	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3682952	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3682952	0	0
T1	97263	1831	0	0
T2	2190	41	0	0
T3	88941	1117	0	0
T4	57480	5	0	0
T5	417905	88491	0	0
T14	197107	2138	0	0
T15	32884	259	0	0
T16	536643	2027	0	0
T18	3579	58	0	0
T19	3227	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1564097	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1564097	0	0
T1	97263	6	0	0
T2	2190	53	0	0
T3	88941	25	0	0
T4	57480	11	0	0
T5	417905	0	0	0
T14	197107	2935	0	0
T15	32884	228	0	0
T16	536643	3546	0	0
T18	3579	54	0	0
T19	3227	26	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2692755	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2692755	0	0
T1	97263	287	0	0
T2	2190	53	0	0
T3	88941	1209	0	0
T4	57480	3	0	0
T5	417905	0	0	0
T14	197107	2352	0	0
T15	32884	235	0	0
T16	536643	3336	0	0
T18	3579	54	0	0
T19	3227	20	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1562680	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1562680	0	0
T1	97263	12	0	0
T2	2190	36	0	0
T3	88941	8	0	0
T4	57480	18	0	0
T5	417905	0	0	0
T14	197107	2153	0	0
T15	32884	197	0	0
T16	536643	6859	0	0
T18	3579	55	0	0
T19	3227	23	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3020582	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3020582	0	0
T1	97263	2265	0	0
T2	2190	36	0	0
T3	88941	516	0	0
T4	57480	4	0	0
T5	417905	0	0	0
T14	197107	2056	0	0
T15	32884	193	0	0
T16	536643	5491	0	0
T18	3579	55	0	0
T19	3227	18	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1525728	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1525728	0	0
T2	2190	34	0	0
T3	88941	19	0	0
T4	57480	8	0	0
T5	417905	2188	0	0
T14	197107	3474	0	0
T15	32884	154	0	0
T16	536643	4249	0	0
T18	3579	63	0	0
T19	3227	4	0	0
T20	371	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2551120	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2551120	0	0
T2	2190	34	0	0
T3	88941	1863	0	0
T4	57480	2	0	0
T5	417905	173152	0	0
T14	197107	2359	0	0
T15	32884	222	0	0
T16	536643	3484	0	0
T18	3579	63	0	0
T19	3227	3	0	0
T20	371	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1512705	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1512705	0	0
T1	97263	28	0	0
T2	2190	33	0	0
T3	88941	10	0	0
T4	57480	4	0	0
T5	417905	0	0	0
T14	197107	801	0	0
T15	32884	274	0	0
T16	536643	6882	0	0
T18	3579	62	0	0
T19	3227	29	0	0
T20	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3034391	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3034391	0	0
T1	97263	2345	0	0
T2	2190	33	0	0
T3	88941	1121	0	0
T4	57480	2	0	0
T5	417905	0	0	0
T14	197107	1131	0	0
T15	32884	285	0	0
T16	536643	6916	0	0
T18	3579	62	0	0
T19	3227	16	0	0
T20	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1471303	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1471303	0	0
T1	97263	17	0	0
T2	2190	41	0	0
T3	88941	17	0	0
T4	57480	15	0	0
T5	417905	0	0	0
T14	197107	460	0	0
T15	32884	267	0	0
T16	536643	2400	0	0
T18	3579	75	0	0
T19	3227	17	0	0
T20	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2308489	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2308489	0	0
T1	97263	2212	0	0
T2	2190	41	0	0
T3	88941	116	0	0
T4	57480	3	0	0
T5	417905	0	0	0
T14	197107	903	0	0
T15	32884	232	0	0
T16	536643	2193	0	0
T18	3579	75	0	0
T19	3227	2	0	0
T20	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1523898	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1523898	0	0
T1	97263	21	0	0
T2	2190	31	0	0
T3	88941	32	0	0
T4	57480	12	0	0
T5	417905	1098	0	0
T14	197107	1052	0	0
T15	32884	282	0	0
T16	536643	5865	0	0
T18	3579	88	0	0
T19	3227	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2444540	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2444540	0	0
T1	97263	1515	0	0
T2	2190	31	0	0
T3	88941	1386	0	0
T4	57480	2	0	0
T5	417905	84029	0	0
T14	197107	1612	0	0
T15	32884	198	0	0
T16	536643	4987	0	0
T18	3579	88	0	0
T19	3227	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1520762	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1520762	0	0
T1	97263	16	0	0
T2	2190	37	0	0
T3	88941	46	0	0
T4	57480	14	0	0
T5	417905	0	0	0
T14	197107	1947	0	0
T15	32884	265	0	0
T16	536643	4341	0	0
T18	3579	59	0	0
T19	3227	53	0	0
T20	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3113714	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3113714	0	0
T1	97263	328	0	0
T2	2190	37	0	0
T3	88941	3049	0	0
T4	57480	5	0	0
T5	417905	0	0	0
T14	197107	2972	0	0
T15	32884	299	0	0
T16	536643	4162	0	0
T18	3579	59	0	0
T19	3227	30	0	0
T20	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1598590	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1598590	0	0
T1	97263	14	0	0
T2	2190	40	0	0
T3	88941	12	0	0
T4	57480	30	0	0
T5	417905	3518	0	0
T14	197107	1624	0	0
T15	32884	154	0	0
T16	536643	4069	0	0
T18	3579	74	0	0
T19	3227	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3270223	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3270223	0	0
T1	97263	772	0	0
T2	2190	40	0	0
T3	88941	646	0	0
T4	57480	6	0	0
T5	417905	287900	0	0
T14	197107	1034	0	0
T15	32884	150	0	0
T16	536643	3742	0	0
T18	3579	74	0	0
T19	3227	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1553256	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1553256	0	0
T1	97263	17	0	0
T2	2190	46	0	0
T3	88941	35	0	0
T4	57480	10	0	0
T5	417905	0	0	0
T14	197107	1869	0	0
T15	32884	235	0	0
T16	536643	5822	0	0
T18	3579	62	0	0
T19	3227	60	0	0
T20	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2539420	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2539420	0	0
T1	97263	1610	0	0
T2	2190	46	0	0
T3	88941	1675	0	0
T4	57480	1	0	0
T5	417905	0	0	0
T14	197107	2603	0	0
T15	32884	269	0	0
T16	536643	4693	0	0
T18	3579	62	0	0
T19	3227	32	0	0
T20	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1568745	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1568745	0	0
T1	97263	10	0	0
T2	2190	40	0	0
T3	88941	10	0	0
T4	57480	17	0	0
T5	417905	0	0	0
T14	197107	1046	0	0
T15	32884	264	0	0
T16	536643	9860	0	0
T18	3579	76	0	0
T19	3227	61	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3131387	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3131387	0	0
T1	97263	1184	0	0
T2	2190	40	0	0
T3	88941	570	0	0
T4	57480	5	0	0
T5	417905	0	0	0
T14	197107	198	0	0
T15	32884	233	0	0
T16	536643	8231	0	0
T18	3579	76	0	0
T19	3227	21	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1566746	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1566746	0	0
T1	97263	14	0	0
T2	2190	35	0	0
T3	88941	23	0	0
T4	57480	19	0	0
T5	417905	2326	0	0
T14	197107	3226	0	0
T15	32884	201	0	0
T16	536643	2283	0	0
T18	3579	75	0	0
T19	3227	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2840341	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2840341	0	0
T1	97263	704	0	0
T2	2190	35	0	0
T3	88941	772	0	0
T4	57480	3	0	0
T5	417905	192793	0	0
T14	197107	1959	0	0
T15	32884	193	0	0
T16	536643	2143	0	0
T18	3579	75	0	0
T19	3227	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1593371	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1593371	0	0
T1	97263	34	0	0
T2	2190	40	0	0
T3	88941	8	0	0
T4	57480	4	0	0
T5	417905	1293	0	0
T14	197107	2766	0	0
T15	32884	193	0	0
T16	536643	5542	0	0
T18	3579	68	0	0
T19	3227	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2843335	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2843335	0	0
T1	97263	2402	0	0
T2	2190	40	0	0
T3	88941	1009	0	0
T4	57480	2	0	0
T5	417905	101848	0	0
T14	197107	1588	0	0
T15	32884	162	0	0
T16	536643	5015	0	0
T18	3579	68	0	0
T19	3227	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1499176	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1499176	0	0
T1	97263	19	0	0
T2	2190	32	0	0
T3	88941	25	0	0
T4	57480	8	0	0
T5	417905	0	0	0
T14	197107	1246	0	0
T15	32884	164	0	0
T16	536643	4181	0	0
T18	3579	55	0	0
T19	3227	36	0	0
T20	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3015558	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3015558	0	0
T1	97263	1807	0	0
T2	2190	32	0	0
T3	88941	1178	0	0
T4	57480	1	0	0
T5	417905	0	0	0
T14	197107	1691	0	0
T15	32884	219	0	0
T16	536643	4063	0	0
T18	3579	55	0	0
T19	3227	13	0	0
T20	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1455561	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1455561	0	0
T1	97263	9	0	0
T2	2190	41	0	0
T3	88941	17	0	0
T4	57480	23	0	0
T5	417905	0	0	0
T14	197107	1219	0	0
T15	32884	241	0	0
T16	536643	9799	0	0
T18	3579	72	0	0
T19	3227	44	0	0
T20	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2338373	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2338373	0	0
T1	97263	1811	0	0
T2	2190	41	0	0
T3	88941	1548	0	0
T4	57480	4	0	0
T5	417905	0	0	0
T14	197107	956	0	0
T15	32884	211	0	0
T16	536643	8579	0	0
T18	3579	72	0	0
T19	3227	18	0	0
T20	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1499595	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1499595	0	0
T1	97263	36	0	0
T2	2190	32	0	0
T3	88941	8	0	0
T4	57480	18	0	0
T5	417905	0	0	0
T14	197107	826	0	0
T15	32884	144	0	0
T16	536643	5567	0	0
T18	3579	59	0	0
T19	3227	25	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	2791225	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	2791225	0	0
T1	97263	1834	0	0
T2	2190	32	0	0
T3	88941	905	0	0
T4	57480	5	0	0
T5	417905	0	0	0
T14	197107	768	0	0
T15	32884	151	0	0
T16	536643	5379	0	0
T18	3579	59	0	0
T19	3227	21	0	0
T20	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1526579	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1526579	0	0
T1	97263	9	0	0
T2	2190	31	0	0
T3	88941	22	0	0
T4	57480	16	0	0
T5	417905	1038	0	0
T14	197107	2489	0	0
T15	32884	239	0	0
T16	536643	8324	0	0
T18	3579	77	0	0
T19	3227	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3500289	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3500289	0	0
T1	97263	305	0	0
T2	2190	31	0	0
T3	88941	2001	0	0
T4	57480	5	0	0
T5	417905	83003	0	0
T14	197107	1694	0	0
T15	32884	210	0	0
T16	536643	7138	0	0
T18	3579	77	0	0
T19	3227	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1532403	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1532403	0	0
T1	97263	21	0	0
T2	2190	37	0	0
T3	88941	6	0	0
T4	57480	7	0	0
T5	417905	0	0	0
T14	197107	481	0	0
T15	32884	221	0	0
T16	536643	4599	0	0
T18	3579	56	0	0
T19	3227	46	0	0
T20	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3014546	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3014546	0	0
T1	97263	2263	0	0
T2	2190	37	0	0
T3	88941	1	0	0
T4	57480	404	0	0
T5	417905	0	0	0
T14	197107	180	0	0
T15	32884	219	0	0
T16	536643	3698	0	0
T18	3579	56	0	0
T19	3227	20	0	0
T20	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	1499913	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	1499913	0	0
T1	97263	15	0	0
T2	2190	36	0	0
T3	88941	9	0	0
T4	57480	15	0	0
T5	417905	1347	0	0
T14	197107	1502	0	0
T15	32884	290	0	0
T16	536643	6443	0	0
T18	3579	74	0	0
T19	3227	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	290737067	3448463	0	0
DepthKnown_A	290737067	290619374	0	0
RvalidKnown_A	290737067	290619374	0	0
WreadyKnown_A	290737067	290619374	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	3448463	0	0
T1	97263	1966	0	0
T2	2190	36	0	0
T3	88941	546	0	0
T4	57480	3	0	0
T5	417905	100567	0	0
T14	197107	1840	0	0
T15	32884	263	0	0
T16	536643	5834	0	0
T18	3579	74	0	0
T19	3227	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290737067	290619374	0	0
T1	97263	97208	0	0
T2	2190	2167	0	0
T3	88941	88889	0	0
T4	57480	57401	0	0
T5	417905	417902	0	0
T14	197107	197078	0	0
T15	32884	32836	0	0
T16	536643	536423	0	0
T18	3579	3555	0	0
T19	3227	3206	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0