Unified Coverage Report :: Group :: tl_agent_pkg::pending_req_on_rst_cg

Group : tl_agent_pkg::pending_req_on_rst_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

28 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1054

1

T22

1

T236

1

T237

3

values[0x1]

15

1

T197

1

T125

2

T296

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1056

1

T22

1

T236

1

T237

3

values[0x1]

13

1

T286

1

T297

1

T298

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1049

1

T22

1

T236

1

T237

3

values[0x1]

20

1

T296

1

T299

1

T281

3

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1060

1

T22

1

T236

1

T237

3

values[0x1]

9

1

T85

1

T300

2

T298

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1049

1

T22

1

T236

1

T237

3

values[0x1]

20

1

T206

2

T301

1

T302

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1052

1

T22

1

T236

1

T237

3

values[0x1]

17

1

T125

1

T208

1

T300

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1053

1

T22

1

T236

1

T237

3

values[0x1]

16

1

T269

1

T127

1

T303

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1043

1

T22

1

T236

1

T237

3

values[0x1]

26

1

T296

2

T127

1

T265

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1054

1

T22

1

T236

1

T237

3

values[0x1]

15

1

T206

1

T210

1

T304

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1058

1

T22

1

T236

1

T237

3

values[0x1]

11

1

T208

1

T222

1

T305

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

603

1

T22

1

T236

1

T269

3

values[0x1]

466

1

T237

3

T53

1

T269

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1053

1

T22

1

T236

1

T237

3

values[0x1]

16

1

T125

2

T210

1

T281

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1052

1

T22

1

T236

1

T237

2

values[0x1]

17

1

T237

1

T197

1

T252

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1061

1

T22

1

T236

1

T237

3

values[0x1]

8

1

T197

1

T306

1

T307

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1053

1

T22

1

T236

1

T237

3

values[0x1]

16

1

T208

1

T308

1

T297

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1051

1

T22

1

T236

1

T237

2

values[0x1]

18

1

T237

1

T309

1

T79

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1054

1

T22

1

T236

1

T237

3

values[0x1]

15

1

T208

1

T252

1

T286

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1055

1

T22

1

T236

1

T237

3

values[0x1]

14

1

T79

1

T125

1

T208

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1043

1

T22

1

T236

1

T237

3

values[0x1]

26

1

T85

1

T79

1

T208

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1046

1

T22

1

T236

1

T237

2

values[0x1]

23

1

T237

1

T309

1

T197

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1051

1

T22

1

T236

1

T237

3

values[0x1]

18

1

T85

1

T125

1

T210

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1053

1

T22

1

T236

1

T237

3

values[0x1]

16

1

T197

1

T206

1

T310

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1053

1

T22

1

T236

1

T237

3

values[0x1]

16

1

T197

1

T79

1

T206

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1052

1

T22

1

T236

1

T237

3

values[0x1]

17

1

T311

1

T79

1

T210

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1054

1

T22

1

T236

1

T237

3

values[0x1]

15

1

T125

3

T310

1

T312

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1049

1

T22

1

T236

1

T237

3

values[0x1]

20

1

T309

1

T197

1

T87

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1058

1

T22

1

T236

1

T237

3

values[0x1]

11

1

T79

1

T125

1

T296

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1056

1

T22

1

T236

1

T237

3

values[0x1]

13

1

T53

1

T206

1

T301

1